sha512-armv4.pl 17 KB

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  1. #!/usr/bin/env perl
  2. # SPDX-License-Identifier: GPL-2.0
  3. # This code is taken from the OpenSSL project but the author (Andy Polyakov)
  4. # has relicensed it under the GPLv2. Therefore this program is free software;
  5. # you can redistribute it and/or modify it under the terms of the GNU General
  6. # Public License version 2 as published by the Free Software Foundation.
  7. #
  8. # The original headers, including the original license headers, are
  9. # included below for completeness.
  10. # ====================================================================
  11. # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
  12. # project. The module is, however, dual licensed under OpenSSL and
  13. # CRYPTOGAMS licenses depending on where you obtain it. For further
  14. # details see https://www.openssl.org/~appro/cryptogams/.
  15. # ====================================================================
  16. # SHA512 block procedure for ARMv4. September 2007.
  17. # This code is ~4.5 (four and a half) times faster than code generated
  18. # by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
  19. # Xscale PXA250 core].
  20. #
  21. # July 2010.
  22. #
  23. # Rescheduling for dual-issue pipeline resulted in 6% improvement on
  24. # Cortex A8 core and ~40 cycles per processed byte.
  25. # February 2011.
  26. #
  27. # Profiler-assisted and platform-specific optimization resulted in 7%
  28. # improvement on Coxtex A8 core and ~38 cycles per byte.
  29. # March 2011.
  30. #
  31. # Add NEON implementation. On Cortex A8 it was measured to process
  32. # one byte in 23.3 cycles or ~60% faster than integer-only code.
  33. # August 2012.
  34. #
  35. # Improve NEON performance by 12% on Snapdragon S4. In absolute
  36. # terms it's 22.6 cycles per byte, which is disappointing result.
  37. # Technical writers asserted that 3-way S4 pipeline can sustain
  38. # multiple NEON instructions per cycle, but dual NEON issue could
  39. # not be observed, see https://www.openssl.org/~appro/Snapdragon-S4.html
  40. # for further details. On side note Cortex-A15 processes one byte in
  41. # 16 cycles.
  42. # Byte order [in]dependence. =========================================
  43. #
  44. # Originally caller was expected to maintain specific *dword* order in
  45. # h[0-7], namely with most significant dword at *lower* address, which
  46. # was reflected in below two parameters as 0 and 4. Now caller is
  47. # expected to maintain native byte order for whole 64-bit values.
  48. $hi="HI";
  49. $lo="LO";
  50. # ====================================================================
  51. while (($output=shift) && ($output!~/^\w[\w\-]*\.\w+$/)) {}
  52. open STDOUT,">$output";
  53. $ctx="r0"; # parameter block
  54. $inp="r1";
  55. $len="r2";
  56. $Tlo="r3";
  57. $Thi="r4";
  58. $Alo="r5";
  59. $Ahi="r6";
  60. $Elo="r7";
  61. $Ehi="r8";
  62. $t0="r9";
  63. $t1="r10";
  64. $t2="r11";
  65. $t3="r12";
  66. ############ r13 is stack pointer
  67. $Ktbl="r14";
  68. ############ r15 is program counter
  69. $Aoff=8*0;
  70. $Boff=8*1;
  71. $Coff=8*2;
  72. $Doff=8*3;
  73. $Eoff=8*4;
  74. $Foff=8*5;
  75. $Goff=8*6;
  76. $Hoff=8*7;
  77. $Xoff=8*8;
  78. sub BODY_00_15() {
  79. my $magic = shift;
  80. $code.=<<___;
  81. @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
  82. @ LO lo>>14^hi<<18 ^ lo>>18^hi<<14 ^ hi>>9^lo<<23
  83. @ HI hi>>14^lo<<18 ^ hi>>18^lo<<14 ^ lo>>9^hi<<23
  84. mov $t0,$Elo,lsr#14
  85. str $Tlo,[sp,#$Xoff+0]
  86. mov $t1,$Ehi,lsr#14
  87. str $Thi,[sp,#$Xoff+4]
  88. eor $t0,$t0,$Ehi,lsl#18
  89. ldr $t2,[sp,#$Hoff+0] @ h.lo
  90. eor $t1,$t1,$Elo,lsl#18
  91. ldr $t3,[sp,#$Hoff+4] @ h.hi
  92. eor $t0,$t0,$Elo,lsr#18
  93. eor $t1,$t1,$Ehi,lsr#18
  94. eor $t0,$t0,$Ehi,lsl#14
  95. eor $t1,$t1,$Elo,lsl#14
  96. eor $t0,$t0,$Ehi,lsr#9
  97. eor $t1,$t1,$Elo,lsr#9
  98. eor $t0,$t0,$Elo,lsl#23
  99. eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
  100. adds $Tlo,$Tlo,$t0
  101. ldr $t0,[sp,#$Foff+0] @ f.lo
  102. adc $Thi,$Thi,$t1 @ T += Sigma1(e)
  103. ldr $t1,[sp,#$Foff+4] @ f.hi
  104. adds $Tlo,$Tlo,$t2
  105. ldr $t2,[sp,#$Goff+0] @ g.lo
  106. adc $Thi,$Thi,$t3 @ T += h
  107. ldr $t3,[sp,#$Goff+4] @ g.hi
  108. eor $t0,$t0,$t2
  109. str $Elo,[sp,#$Eoff+0]
  110. eor $t1,$t1,$t3
  111. str $Ehi,[sp,#$Eoff+4]
  112. and $t0,$t0,$Elo
  113. str $Alo,[sp,#$Aoff+0]
  114. and $t1,$t1,$Ehi
  115. str $Ahi,[sp,#$Aoff+4]
  116. eor $t0,$t0,$t2
  117. ldr $t2,[$Ktbl,#$lo] @ K[i].lo
  118. eor $t1,$t1,$t3 @ Ch(e,f,g)
  119. ldr $t3,[$Ktbl,#$hi] @ K[i].hi
  120. adds $Tlo,$Tlo,$t0
  121. ldr $Elo,[sp,#$Doff+0] @ d.lo
  122. adc $Thi,$Thi,$t1 @ T += Ch(e,f,g)
  123. ldr $Ehi,[sp,#$Doff+4] @ d.hi
  124. adds $Tlo,$Tlo,$t2
  125. and $t0,$t2,#0xff
  126. adc $Thi,$Thi,$t3 @ T += K[i]
  127. adds $Elo,$Elo,$Tlo
  128. ldr $t2,[sp,#$Boff+0] @ b.lo
  129. adc $Ehi,$Ehi,$Thi @ d += T
  130. teq $t0,#$magic
  131. ldr $t3,[sp,#$Coff+0] @ c.lo
  132. #if __ARM_ARCH__>=7
  133. it eq @ Thumb2 thing, sanity check in ARM
  134. #endif
  135. orreq $Ktbl,$Ktbl,#1
  136. @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
  137. @ LO lo>>28^hi<<4 ^ hi>>2^lo<<30 ^ hi>>7^lo<<25
  138. @ HI hi>>28^lo<<4 ^ lo>>2^hi<<30 ^ lo>>7^hi<<25
  139. mov $t0,$Alo,lsr#28
  140. mov $t1,$Ahi,lsr#28
  141. eor $t0,$t0,$Ahi,lsl#4
  142. eor $t1,$t1,$Alo,lsl#4
  143. eor $t0,$t0,$Ahi,lsr#2
  144. eor $t1,$t1,$Alo,lsr#2
  145. eor $t0,$t0,$Alo,lsl#30
  146. eor $t1,$t1,$Ahi,lsl#30
  147. eor $t0,$t0,$Ahi,lsr#7
  148. eor $t1,$t1,$Alo,lsr#7
  149. eor $t0,$t0,$Alo,lsl#25
  150. eor $t1,$t1,$Ahi,lsl#25 @ Sigma0(a)
  151. adds $Tlo,$Tlo,$t0
  152. and $t0,$Alo,$t2
  153. adc $Thi,$Thi,$t1 @ T += Sigma0(a)
  154. ldr $t1,[sp,#$Boff+4] @ b.hi
  155. orr $Alo,$Alo,$t2
  156. ldr $t2,[sp,#$Coff+4] @ c.hi
  157. and $Alo,$Alo,$t3
  158. and $t3,$Ahi,$t1
  159. orr $Ahi,$Ahi,$t1
  160. orr $Alo,$Alo,$t0 @ Maj(a,b,c).lo
  161. and $Ahi,$Ahi,$t2
  162. adds $Alo,$Alo,$Tlo
  163. orr $Ahi,$Ahi,$t3 @ Maj(a,b,c).hi
  164. sub sp,sp,#8
  165. adc $Ahi,$Ahi,$Thi @ h += T
  166. tst $Ktbl,#1
  167. add $Ktbl,$Ktbl,#8
  168. ___
  169. }
  170. $code=<<___;
  171. #ifndef __KERNEL__
  172. # include "arm_arch.h"
  173. # define VFP_ABI_PUSH vstmdb sp!,{d8-d15}
  174. # define VFP_ABI_POP vldmia sp!,{d8-d15}
  175. #else
  176. # define __ARM_ARCH__ __LINUX_ARM_ARCH__
  177. # define __ARM_MAX_ARCH__ 7
  178. # define VFP_ABI_PUSH
  179. # define VFP_ABI_POP
  180. #endif
  181. #ifdef __ARMEL__
  182. # define LO 0
  183. # define HI 4
  184. # define WORD64(hi0,lo0,hi1,lo1) .word lo0,hi0, lo1,hi1
  185. #else
  186. # define HI 0
  187. # define LO 4
  188. # define WORD64(hi0,lo0,hi1,lo1) .word hi0,lo0, hi1,lo1
  189. #endif
  190. .text
  191. #if __ARM_ARCH__<7
  192. .code 32
  193. #else
  194. .syntax unified
  195. # ifdef __thumb2__
  196. .thumb
  197. # else
  198. .code 32
  199. # endif
  200. #endif
  201. .type K512,%object
  202. .align 5
  203. K512:
  204. WORD64(0x428a2f98,0xd728ae22, 0x71374491,0x23ef65cd)
  205. WORD64(0xb5c0fbcf,0xec4d3b2f, 0xe9b5dba5,0x8189dbbc)
  206. WORD64(0x3956c25b,0xf348b538, 0x59f111f1,0xb605d019)
  207. WORD64(0x923f82a4,0xaf194f9b, 0xab1c5ed5,0xda6d8118)
  208. WORD64(0xd807aa98,0xa3030242, 0x12835b01,0x45706fbe)
  209. WORD64(0x243185be,0x4ee4b28c, 0x550c7dc3,0xd5ffb4e2)
  210. WORD64(0x72be5d74,0xf27b896f, 0x80deb1fe,0x3b1696b1)
  211. WORD64(0x9bdc06a7,0x25c71235, 0xc19bf174,0xcf692694)
  212. WORD64(0xe49b69c1,0x9ef14ad2, 0xefbe4786,0x384f25e3)
  213. WORD64(0x0fc19dc6,0x8b8cd5b5, 0x240ca1cc,0x77ac9c65)
  214. WORD64(0x2de92c6f,0x592b0275, 0x4a7484aa,0x6ea6e483)
  215. WORD64(0x5cb0a9dc,0xbd41fbd4, 0x76f988da,0x831153b5)
  216. WORD64(0x983e5152,0xee66dfab, 0xa831c66d,0x2db43210)
  217. WORD64(0xb00327c8,0x98fb213f, 0xbf597fc7,0xbeef0ee4)
  218. WORD64(0xc6e00bf3,0x3da88fc2, 0xd5a79147,0x930aa725)
  219. WORD64(0x06ca6351,0xe003826f, 0x14292967,0x0a0e6e70)
  220. WORD64(0x27b70a85,0x46d22ffc, 0x2e1b2138,0x5c26c926)
  221. WORD64(0x4d2c6dfc,0x5ac42aed, 0x53380d13,0x9d95b3df)
  222. WORD64(0x650a7354,0x8baf63de, 0x766a0abb,0x3c77b2a8)
  223. WORD64(0x81c2c92e,0x47edaee6, 0x92722c85,0x1482353b)
  224. WORD64(0xa2bfe8a1,0x4cf10364, 0xa81a664b,0xbc423001)
  225. WORD64(0xc24b8b70,0xd0f89791, 0xc76c51a3,0x0654be30)
  226. WORD64(0xd192e819,0xd6ef5218, 0xd6990624,0x5565a910)
  227. WORD64(0xf40e3585,0x5771202a, 0x106aa070,0x32bbd1b8)
  228. WORD64(0x19a4c116,0xb8d2d0c8, 0x1e376c08,0x5141ab53)
  229. WORD64(0x2748774c,0xdf8eeb99, 0x34b0bcb5,0xe19b48a8)
  230. WORD64(0x391c0cb3,0xc5c95a63, 0x4ed8aa4a,0xe3418acb)
  231. WORD64(0x5b9cca4f,0x7763e373, 0x682e6ff3,0xd6b2b8a3)
  232. WORD64(0x748f82ee,0x5defb2fc, 0x78a5636f,0x43172f60)
  233. WORD64(0x84c87814,0xa1f0ab72, 0x8cc70208,0x1a6439ec)
  234. WORD64(0x90befffa,0x23631e28, 0xa4506ceb,0xde82bde9)
  235. WORD64(0xbef9a3f7,0xb2c67915, 0xc67178f2,0xe372532b)
  236. WORD64(0xca273ece,0xea26619c, 0xd186b8c7,0x21c0c207)
  237. WORD64(0xeada7dd6,0xcde0eb1e, 0xf57d4f7f,0xee6ed178)
  238. WORD64(0x06f067aa,0x72176fba, 0x0a637dc5,0xa2c898a6)
  239. WORD64(0x113f9804,0xbef90dae, 0x1b710b35,0x131c471b)
  240. WORD64(0x28db77f5,0x23047d84, 0x32caab7b,0x40c72493)
  241. WORD64(0x3c9ebe0a,0x15c9bebc, 0x431d67c4,0x9c100d4c)
  242. WORD64(0x4cc5d4be,0xcb3e42b6, 0x597f299c,0xfc657e2a)
  243. WORD64(0x5fcb6fab,0x3ad6faec, 0x6c44198c,0x4a475817)
  244. .size K512,.-K512
  245. #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
  246. .LOPENSSL_armcap:
  247. .word OPENSSL_armcap_P-sha512_block_data_order
  248. .skip 32-4
  249. #else
  250. .skip 32
  251. #endif
  252. .global sha512_block_data_order
  253. .type sha512_block_data_order,%function
  254. sha512_block_data_order:
  255. .Lsha512_block_data_order:
  256. #if __ARM_ARCH__<7
  257. sub r3,pc,#8 @ sha512_block_data_order
  258. #else
  259. adr r3,.Lsha512_block_data_order
  260. #endif
  261. #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
  262. ldr r12,.LOPENSSL_armcap
  263. ldr r12,[r3,r12] @ OPENSSL_armcap_P
  264. tst r12,#1
  265. bne .LNEON
  266. #endif
  267. add $len,$inp,$len,lsl#7 @ len to point at the end of inp
  268. stmdb sp!,{r4-r12,lr}
  269. sub $Ktbl,r3,#672 @ K512
  270. sub sp,sp,#9*8
  271. ldr $Elo,[$ctx,#$Eoff+$lo]
  272. ldr $Ehi,[$ctx,#$Eoff+$hi]
  273. ldr $t0, [$ctx,#$Goff+$lo]
  274. ldr $t1, [$ctx,#$Goff+$hi]
  275. ldr $t2, [$ctx,#$Hoff+$lo]
  276. ldr $t3, [$ctx,#$Hoff+$hi]
  277. .Loop:
  278. str $t0, [sp,#$Goff+0]
  279. str $t1, [sp,#$Goff+4]
  280. str $t2, [sp,#$Hoff+0]
  281. str $t3, [sp,#$Hoff+4]
  282. ldr $Alo,[$ctx,#$Aoff+$lo]
  283. ldr $Ahi,[$ctx,#$Aoff+$hi]
  284. ldr $Tlo,[$ctx,#$Boff+$lo]
  285. ldr $Thi,[$ctx,#$Boff+$hi]
  286. ldr $t0, [$ctx,#$Coff+$lo]
  287. ldr $t1, [$ctx,#$Coff+$hi]
  288. ldr $t2, [$ctx,#$Doff+$lo]
  289. ldr $t3, [$ctx,#$Doff+$hi]
  290. str $Tlo,[sp,#$Boff+0]
  291. str $Thi,[sp,#$Boff+4]
  292. str $t0, [sp,#$Coff+0]
  293. str $t1, [sp,#$Coff+4]
  294. str $t2, [sp,#$Doff+0]
  295. str $t3, [sp,#$Doff+4]
  296. ldr $Tlo,[$ctx,#$Foff+$lo]
  297. ldr $Thi,[$ctx,#$Foff+$hi]
  298. str $Tlo,[sp,#$Foff+0]
  299. str $Thi,[sp,#$Foff+4]
  300. .L00_15:
  301. #if __ARM_ARCH__<7
  302. ldrb $Tlo,[$inp,#7]
  303. ldrb $t0, [$inp,#6]
  304. ldrb $t1, [$inp,#5]
  305. ldrb $t2, [$inp,#4]
  306. ldrb $Thi,[$inp,#3]
  307. ldrb $t3, [$inp,#2]
  308. orr $Tlo,$Tlo,$t0,lsl#8
  309. ldrb $t0, [$inp,#1]
  310. orr $Tlo,$Tlo,$t1,lsl#16
  311. ldrb $t1, [$inp],#8
  312. orr $Tlo,$Tlo,$t2,lsl#24
  313. orr $Thi,$Thi,$t3,lsl#8
  314. orr $Thi,$Thi,$t0,lsl#16
  315. orr $Thi,$Thi,$t1,lsl#24
  316. #else
  317. ldr $Tlo,[$inp,#4]
  318. ldr $Thi,[$inp],#8
  319. #ifdef __ARMEL__
  320. rev $Tlo,$Tlo
  321. rev $Thi,$Thi
  322. #endif
  323. #endif
  324. ___
  325. &BODY_00_15(0x94);
  326. $code.=<<___;
  327. tst $Ktbl,#1
  328. beq .L00_15
  329. ldr $t0,[sp,#`$Xoff+8*(16-1)`+0]
  330. ldr $t1,[sp,#`$Xoff+8*(16-1)`+4]
  331. bic $Ktbl,$Ktbl,#1
  332. .L16_79:
  333. @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
  334. @ LO lo>>1^hi<<31 ^ lo>>8^hi<<24 ^ lo>>7^hi<<25
  335. @ HI hi>>1^lo<<31 ^ hi>>8^lo<<24 ^ hi>>7
  336. mov $Tlo,$t0,lsr#1
  337. ldr $t2,[sp,#`$Xoff+8*(16-14)`+0]
  338. mov $Thi,$t1,lsr#1
  339. ldr $t3,[sp,#`$Xoff+8*(16-14)`+4]
  340. eor $Tlo,$Tlo,$t1,lsl#31
  341. eor $Thi,$Thi,$t0,lsl#31
  342. eor $Tlo,$Tlo,$t0,lsr#8
  343. eor $Thi,$Thi,$t1,lsr#8
  344. eor $Tlo,$Tlo,$t1,lsl#24
  345. eor $Thi,$Thi,$t0,lsl#24
  346. eor $Tlo,$Tlo,$t0,lsr#7
  347. eor $Thi,$Thi,$t1,lsr#7
  348. eor $Tlo,$Tlo,$t1,lsl#25
  349. @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
  350. @ LO lo>>19^hi<<13 ^ hi>>29^lo<<3 ^ lo>>6^hi<<26
  351. @ HI hi>>19^lo<<13 ^ lo>>29^hi<<3 ^ hi>>6
  352. mov $t0,$t2,lsr#19
  353. mov $t1,$t3,lsr#19
  354. eor $t0,$t0,$t3,lsl#13
  355. eor $t1,$t1,$t2,lsl#13
  356. eor $t0,$t0,$t3,lsr#29
  357. eor $t1,$t1,$t2,lsr#29
  358. eor $t0,$t0,$t2,lsl#3
  359. eor $t1,$t1,$t3,lsl#3
  360. eor $t0,$t0,$t2,lsr#6
  361. eor $t1,$t1,$t3,lsr#6
  362. ldr $t2,[sp,#`$Xoff+8*(16-9)`+0]
  363. eor $t0,$t0,$t3,lsl#26
  364. ldr $t3,[sp,#`$Xoff+8*(16-9)`+4]
  365. adds $Tlo,$Tlo,$t0
  366. ldr $t0,[sp,#`$Xoff+8*16`+0]
  367. adc $Thi,$Thi,$t1
  368. ldr $t1,[sp,#`$Xoff+8*16`+4]
  369. adds $Tlo,$Tlo,$t2
  370. adc $Thi,$Thi,$t3
  371. adds $Tlo,$Tlo,$t0
  372. adc $Thi,$Thi,$t1
  373. ___
  374. &BODY_00_15(0x17);
  375. $code.=<<___;
  376. #if __ARM_ARCH__>=7
  377. ittt eq @ Thumb2 thing, sanity check in ARM
  378. #endif
  379. ldreq $t0,[sp,#`$Xoff+8*(16-1)`+0]
  380. ldreq $t1,[sp,#`$Xoff+8*(16-1)`+4]
  381. beq .L16_79
  382. bic $Ktbl,$Ktbl,#1
  383. ldr $Tlo,[sp,#$Boff+0]
  384. ldr $Thi,[sp,#$Boff+4]
  385. ldr $t0, [$ctx,#$Aoff+$lo]
  386. ldr $t1, [$ctx,#$Aoff+$hi]
  387. ldr $t2, [$ctx,#$Boff+$lo]
  388. ldr $t3, [$ctx,#$Boff+$hi]
  389. adds $t0,$Alo,$t0
  390. str $t0, [$ctx,#$Aoff+$lo]
  391. adc $t1,$Ahi,$t1
  392. str $t1, [$ctx,#$Aoff+$hi]
  393. adds $t2,$Tlo,$t2
  394. str $t2, [$ctx,#$Boff+$lo]
  395. adc $t3,$Thi,$t3
  396. str $t3, [$ctx,#$Boff+$hi]
  397. ldr $Alo,[sp,#$Coff+0]
  398. ldr $Ahi,[sp,#$Coff+4]
  399. ldr $Tlo,[sp,#$Doff+0]
  400. ldr $Thi,[sp,#$Doff+4]
  401. ldr $t0, [$ctx,#$Coff+$lo]
  402. ldr $t1, [$ctx,#$Coff+$hi]
  403. ldr $t2, [$ctx,#$Doff+$lo]
  404. ldr $t3, [$ctx,#$Doff+$hi]
  405. adds $t0,$Alo,$t0
  406. str $t0, [$ctx,#$Coff+$lo]
  407. adc $t1,$Ahi,$t1
  408. str $t1, [$ctx,#$Coff+$hi]
  409. adds $t2,$Tlo,$t2
  410. str $t2, [$ctx,#$Doff+$lo]
  411. adc $t3,$Thi,$t3
  412. str $t3, [$ctx,#$Doff+$hi]
  413. ldr $Tlo,[sp,#$Foff+0]
  414. ldr $Thi,[sp,#$Foff+4]
  415. ldr $t0, [$ctx,#$Eoff+$lo]
  416. ldr $t1, [$ctx,#$Eoff+$hi]
  417. ldr $t2, [$ctx,#$Foff+$lo]
  418. ldr $t3, [$ctx,#$Foff+$hi]
  419. adds $Elo,$Elo,$t0
  420. str $Elo,[$ctx,#$Eoff+$lo]
  421. adc $Ehi,$Ehi,$t1
  422. str $Ehi,[$ctx,#$Eoff+$hi]
  423. adds $t2,$Tlo,$t2
  424. str $t2, [$ctx,#$Foff+$lo]
  425. adc $t3,$Thi,$t3
  426. str $t3, [$ctx,#$Foff+$hi]
  427. ldr $Alo,[sp,#$Goff+0]
  428. ldr $Ahi,[sp,#$Goff+4]
  429. ldr $Tlo,[sp,#$Hoff+0]
  430. ldr $Thi,[sp,#$Hoff+4]
  431. ldr $t0, [$ctx,#$Goff+$lo]
  432. ldr $t1, [$ctx,#$Goff+$hi]
  433. ldr $t2, [$ctx,#$Hoff+$lo]
  434. ldr $t3, [$ctx,#$Hoff+$hi]
  435. adds $t0,$Alo,$t0
  436. str $t0, [$ctx,#$Goff+$lo]
  437. adc $t1,$Ahi,$t1
  438. str $t1, [$ctx,#$Goff+$hi]
  439. adds $t2,$Tlo,$t2
  440. str $t2, [$ctx,#$Hoff+$lo]
  441. adc $t3,$Thi,$t3
  442. str $t3, [$ctx,#$Hoff+$hi]
  443. add sp,sp,#640
  444. sub $Ktbl,$Ktbl,#640
  445. teq $inp,$len
  446. bne .Loop
  447. add sp,sp,#8*9 @ destroy frame
  448. #if __ARM_ARCH__>=5
  449. ldmia sp!,{r4-r12,pc}
  450. #else
  451. ldmia sp!,{r4-r12,lr}
  452. tst lr,#1
  453. moveq pc,lr @ be binary compatible with V4, yet
  454. bx lr @ interoperable with Thumb ISA:-)
  455. #endif
  456. .size sha512_block_data_order,.-sha512_block_data_order
  457. ___
  458. {
  459. my @Sigma0=(28,34,39);
  460. my @Sigma1=(14,18,41);
  461. my @sigma0=(1, 8, 7);
  462. my @sigma1=(19,61,6);
  463. my $Ktbl="r3";
  464. my $cnt="r12"; # volatile register known as ip, intra-procedure-call scratch
  465. my @X=map("d$_",(0..15));
  466. my @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("d$_",(16..23));
  467. sub NEON_00_15() {
  468. my $i=shift;
  469. my ($a,$b,$c,$d,$e,$f,$g,$h)=@_;
  470. my ($t0,$t1,$t2,$T1,$K,$Ch,$Maj)=map("d$_",(24..31)); # temps
  471. $code.=<<___ if ($i<16 || $i&1);
  472. vshr.u64 $t0,$e,#@Sigma1[0] @ $i
  473. #if $i<16
  474. vld1.64 {@X[$i%16]},[$inp]! @ handles unaligned
  475. #endif
  476. vshr.u64 $t1,$e,#@Sigma1[1]
  477. #if $i>0
  478. vadd.i64 $a,$Maj @ h+=Maj from the past
  479. #endif
  480. vshr.u64 $t2,$e,#@Sigma1[2]
  481. ___
  482. $code.=<<___;
  483. vld1.64 {$K},[$Ktbl,:64]! @ K[i++]
  484. vsli.64 $t0,$e,#`64-@Sigma1[0]`
  485. vsli.64 $t1,$e,#`64-@Sigma1[1]`
  486. vmov $Ch,$e
  487. vsli.64 $t2,$e,#`64-@Sigma1[2]`
  488. #if $i<16 && defined(__ARMEL__)
  489. vrev64.8 @X[$i],@X[$i]
  490. #endif
  491. veor $t1,$t0
  492. vbsl $Ch,$f,$g @ Ch(e,f,g)
  493. vshr.u64 $t0,$a,#@Sigma0[0]
  494. veor $t2,$t1 @ Sigma1(e)
  495. vadd.i64 $T1,$Ch,$h
  496. vshr.u64 $t1,$a,#@Sigma0[1]
  497. vsli.64 $t0,$a,#`64-@Sigma0[0]`
  498. vadd.i64 $T1,$t2
  499. vshr.u64 $t2,$a,#@Sigma0[2]
  500. vadd.i64 $K,@X[$i%16]
  501. vsli.64 $t1,$a,#`64-@Sigma0[1]`
  502. veor $Maj,$a,$b
  503. vsli.64 $t2,$a,#`64-@Sigma0[2]`
  504. veor $h,$t0,$t1
  505. vadd.i64 $T1,$K
  506. vbsl $Maj,$c,$b @ Maj(a,b,c)
  507. veor $h,$t2 @ Sigma0(a)
  508. vadd.i64 $d,$T1
  509. vadd.i64 $Maj,$T1
  510. @ vadd.i64 $h,$Maj
  511. ___
  512. }
  513. sub NEON_16_79() {
  514. my $i=shift;
  515. if ($i&1) { &NEON_00_15($i,@_); return; }
  516. # 2x-vectorized, therefore runs every 2nd round
  517. my @X=map("q$_",(0..7)); # view @X as 128-bit vector
  518. my ($t0,$t1,$s0,$s1) = map("q$_",(12..15)); # temps
  519. my ($d0,$d1,$d2) = map("d$_",(24..26)); # temps from NEON_00_15
  520. my $e=@_[4]; # $e from NEON_00_15
  521. $i /= 2;
  522. $code.=<<___;
  523. vshr.u64 $t0,@X[($i+7)%8],#@sigma1[0]
  524. vshr.u64 $t1,@X[($i+7)%8],#@sigma1[1]
  525. vadd.i64 @_[0],d30 @ h+=Maj from the past
  526. vshr.u64 $s1,@X[($i+7)%8],#@sigma1[2]
  527. vsli.64 $t0,@X[($i+7)%8],#`64-@sigma1[0]`
  528. vext.8 $s0,@X[$i%8],@X[($i+1)%8],#8 @ X[i+1]
  529. vsli.64 $t1,@X[($i+7)%8],#`64-@sigma1[1]`
  530. veor $s1,$t0
  531. vshr.u64 $t0,$s0,#@sigma0[0]
  532. veor $s1,$t1 @ sigma1(X[i+14])
  533. vshr.u64 $t1,$s0,#@sigma0[1]
  534. vadd.i64 @X[$i%8],$s1
  535. vshr.u64 $s1,$s0,#@sigma0[2]
  536. vsli.64 $t0,$s0,#`64-@sigma0[0]`
  537. vsli.64 $t1,$s0,#`64-@sigma0[1]`
  538. vext.8 $s0,@X[($i+4)%8],@X[($i+5)%8],#8 @ X[i+9]
  539. veor $s1,$t0
  540. vshr.u64 $d0,$e,#@Sigma1[0] @ from NEON_00_15
  541. vadd.i64 @X[$i%8],$s0
  542. vshr.u64 $d1,$e,#@Sigma1[1] @ from NEON_00_15
  543. veor $s1,$t1 @ sigma0(X[i+1])
  544. vshr.u64 $d2,$e,#@Sigma1[2] @ from NEON_00_15
  545. vadd.i64 @X[$i%8],$s1
  546. ___
  547. &NEON_00_15(2*$i,@_);
  548. }
  549. $code.=<<___;
  550. #if __ARM_MAX_ARCH__>=7
  551. .arch armv7-a
  552. .fpu neon
  553. .global sha512_block_data_order_neon
  554. .type sha512_block_data_order_neon,%function
  555. .align 4
  556. sha512_block_data_order_neon:
  557. .LNEON:
  558. dmb @ errata #451034 on early Cortex A8
  559. add $len,$inp,$len,lsl#7 @ len to point at the end of inp
  560. VFP_ABI_PUSH
  561. adr $Ktbl,.Lsha512_block_data_order
  562. sub $Ktbl,$Ktbl,.Lsha512_block_data_order-K512
  563. vldmia $ctx,{$A-$H} @ load context
  564. .Loop_neon:
  565. ___
  566. for($i=0;$i<16;$i++) { &NEON_00_15($i,@V); unshift(@V,pop(@V)); }
  567. $code.=<<___;
  568. mov $cnt,#4
  569. .L16_79_neon:
  570. subs $cnt,#1
  571. ___
  572. for(;$i<32;$i++) { &NEON_16_79($i,@V); unshift(@V,pop(@V)); }
  573. $code.=<<___;
  574. bne .L16_79_neon
  575. vadd.i64 $A,d30 @ h+=Maj from the past
  576. vldmia $ctx,{d24-d31} @ load context to temp
  577. vadd.i64 q8,q12 @ vectorized accumulate
  578. vadd.i64 q9,q13
  579. vadd.i64 q10,q14
  580. vadd.i64 q11,q15
  581. vstmia $ctx,{$A-$H} @ save context
  582. teq $inp,$len
  583. sub $Ktbl,#640 @ rewind K512
  584. bne .Loop_neon
  585. VFP_ABI_POP
  586. ret @ bx lr
  587. .size sha512_block_data_order_neon,.-sha512_block_data_order_neon
  588. #endif
  589. ___
  590. }
  591. $code.=<<___;
  592. .asciz "SHA512 block transform for ARMv4/NEON, CRYPTOGAMS by <appro\@openssl.org>"
  593. .align 2
  594. #if __ARM_MAX_ARCH__>=7 && !defined(__KERNEL__)
  595. .comm OPENSSL_armcap_P,4,4
  596. #endif
  597. ___
  598. $code =~ s/\`([^\`]*)\`/eval $1/gem;
  599. $code =~ s/\bbx\s+lr\b/.word\t0xe12fff1e/gm; # make it possible to compile with -march=armv4
  600. $code =~ s/\bret\b/bx lr/gm;
  601. open SELF,$0;
  602. while(<SELF>) {
  603. next if (/^#!/);
  604. last if (!s/^#/@/ and !/^$/);
  605. print;
  606. }
  607. close SELF;
  608. print $code;
  609. close STDOUT; # enforce flush