Kconfig 63 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. config ARM
  3. bool
  4. default y
  5. select ARCH_32BIT_OFF_T
  6. select ARCH_HAS_BINFMT_FLAT
  7. select ARCH_HAS_DEBUG_VIRTUAL if MMU
  8. select ARCH_HAS_DEVMEM_IS_ALLOWED
  9. select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
  10. select ARCH_HAS_ELF_RANDOMIZE
  11. select ARCH_HAS_FORTIFY_SOURCE
  12. select ARCH_HAS_KEEPINITRD
  13. select ARCH_HAS_KCOV
  14. select ARCH_HAS_MEMBARRIER_SYNC_CORE
  15. select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
  16. select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
  17. select ARCH_HAS_PHYS_TO_DMA
  18. select ARCH_HAS_SETUP_DMA_OPS
  19. select ARCH_HAS_SET_MEMORY
  20. select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  21. select ARCH_HAS_STRICT_MODULE_RWX if MMU
  22. select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
  23. select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
  24. select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
  25. select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  26. select ARCH_HAVE_CUSTOM_GPIO_H
  27. select ARCH_HAS_GCOV_PROFILE_ALL
  28. select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC
  29. select ARCH_MIGHT_HAVE_PC_PARPORT
  30. select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
  31. select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  32. select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  33. select ARCH_SUPPORTS_ATOMIC_RMW
  34. select ARCH_USE_BUILTIN_BSWAP
  35. select ARCH_USE_CMPXCHG_LOCKREF
  36. select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
  37. select ARCH_WANT_IPC_PARSE_VERSION
  38. select ARCH_WANT_LD_ORPHAN_WARN
  39. select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
  40. select BUILDTIME_TABLE_SORT if MMU
  41. select CLONE_BACKWARDS
  42. select CPU_PM if SUSPEND || CPU_IDLE
  43. select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  44. select DMA_DECLARE_COHERENT
  45. select DMA_OPS
  46. select DMA_REMAP if MMU
  47. select EDAC_SUPPORT
  48. select EDAC_ATOMIC_SCRUB
  49. select GENERIC_ALLOCATOR
  50. select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  51. select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
  52. select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  53. select GENERIC_IRQ_IPI if SMP
  54. select ARCH_WANTS_IRQ_RAW if GENERIC_IRQ_IPI
  55. select GENERIC_CPU_AUTOPROBE
  56. select GENERIC_EARLY_IOREMAP
  57. select GENERIC_IDLE_POLL_SETUP
  58. select GENERIC_IRQ_PROBE
  59. select GENERIC_IRQ_SHOW
  60. select GENERIC_IRQ_SHOW_LEVEL
  61. select GENERIC_PCI_IOMAP
  62. select GENERIC_SCHED_CLOCK
  63. select GENERIC_SMP_IDLE_THREAD
  64. select GENERIC_STRNCPY_FROM_USER
  65. select GENERIC_STRNLEN_USER
  66. select HANDLE_DOMAIN_IRQ
  67. select HARDIRQS_SW_RESEND
  68. select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
  69. select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  70. select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  71. select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  72. select HAVE_ARCH_MMAP_RND_BITS if MMU
  73. select HAVE_ARCH_SECCOMP
  74. select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
  75. select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  76. select HAVE_ARCH_TRACEHOOK
  77. select HAVE_ARM_SMCCC if CPU_V7
  78. select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  79. select HAVE_CONTEXT_TRACKING
  80. select HAVE_C_RECORDMCOUNT
  81. select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
  82. select HAVE_DMA_CONTIGUOUS if MMU
  83. select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  84. select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  85. select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  86. select HAVE_EXIT_THREAD
  87. select HAVE_FAST_GUP if ARM_LPAE
  88. select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
  89. select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
  90. select HAVE_FUNCTION_TRACER if !XIP_KERNEL
  91. select HAVE_FUTEX_CMPXCHG if FUTEX
  92. select HAVE_GCC_PLUGINS
  93. select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
  94. select HAVE_IDE if PCI || ISA || PCMCIA
  95. select HAVE_IRQ_TIME_ACCOUNTING
  96. select HAVE_KERNEL_GZIP
  97. select HAVE_KERNEL_LZ4
  98. select HAVE_KERNEL_LZMA
  99. select HAVE_KERNEL_LZO
  100. select HAVE_KERNEL_XZ
  101. select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  102. select HAVE_KRETPROBES if HAVE_KPROBES
  103. select HAVE_MOD_ARCH_SPECIFIC
  104. select HAVE_NMI
  105. select HAVE_OPROFILE if HAVE_PERF_EVENTS
  106. select HAVE_OPTPROBES if !THUMB2_KERNEL
  107. select HAVE_PERF_EVENTS
  108. select HAVE_PERF_REGS
  109. select HAVE_PERF_USER_STACK_DUMP
  110. select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
  111. select HAVE_REGS_AND_STACK_ACCESS_API
  112. select HAVE_RSEQ
  113. select HAVE_STACKPROTECTOR
  114. select HAVE_SYSCALL_TRACEPOINTS
  115. select HAVE_UID16
  116. select HAVE_VIRT_CPU_ACCOUNTING_GEN
  117. select IRQ_FORCED_THREADING
  118. select MODULES_USE_ELF_REL
  119. select NEED_DMA_MAP_STATE
  120. select OF_EARLY_FLATTREE if OF
  121. select OLD_SIGACTION
  122. select OLD_SIGSUSPEND3
  123. select PCI_SYSCALL if PCI
  124. select PERF_USE_VMALLOC
  125. select RTC_LIB
  126. select SET_FS
  127. select SYS_SUPPORTS_APM_EMULATION
  128. # Above selects are sorted alphabetically; please add new ones
  129. # according to that. Thanks.
  130. help
  131. The ARM series is a line of low-power-consumption RISC chip designs
  132. licensed by ARM Ltd and targeted at embedded applications and
  133. handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
  134. manufactured, but legacy ARM-based PC hardware remains popular in
  135. Europe. There is an ARM Linux project with a web page at
  136. <http://www.arm.linux.org.uk/>.
  137. config ARM_HAS_SG_CHAIN
  138. bool
  139. config ARM_DMA_USE_IOMMU
  140. bool
  141. select ARM_HAS_SG_CHAIN
  142. select NEED_SG_DMA_LENGTH
  143. if ARM_DMA_USE_IOMMU
  144. config ARM_DMA_IOMMU_ALIGNMENT
  145. int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
  146. range 4 9
  147. default 8
  148. help
  149. DMA mapping framework by default aligns all buffers to the smallest
  150. PAGE_SIZE order which is greater than or equal to the requested buffer
  151. size. This works well for buffers up to a few hundreds kilobytes, but
  152. for larger buffers it just a waste of address space. Drivers which has
  153. relatively small addressing window (like 64Mib) might run out of
  154. virtual space with just a few allocations.
  155. With this parameter you can specify the maximum PAGE_SIZE order for
  156. DMA IOMMU buffers. Larger buffers will be aligned only to this
  157. specified order. The order is expressed as a power of two multiplied
  158. by the PAGE_SIZE.
  159. endif
  160. config SYS_SUPPORTS_APM_EMULATION
  161. bool
  162. config HAVE_TCM
  163. bool
  164. select GENERIC_ALLOCATOR
  165. config HAVE_PROC_CPU
  166. bool
  167. config NO_IOPORT_MAP
  168. bool
  169. config SBUS
  170. bool
  171. config STACKTRACE_SUPPORT
  172. bool
  173. default y
  174. config LOCKDEP_SUPPORT
  175. bool
  176. default y
  177. config TRACE_IRQFLAGS_SUPPORT
  178. bool
  179. default !CPU_V7M
  180. config ARCH_HAS_ILOG2_U32
  181. bool
  182. config ARCH_HAS_ILOG2_U64
  183. bool
  184. config ARCH_HAS_BANDGAP
  185. bool
  186. config FIX_EARLYCON_MEM
  187. def_bool y if MMU
  188. config GENERIC_HWEIGHT
  189. bool
  190. default y
  191. config GENERIC_CALIBRATE_DELAY
  192. bool
  193. default y
  194. config ARCH_MAY_HAVE_PC_FDC
  195. bool
  196. config ZONE_DMA
  197. bool
  198. config ARCH_SUPPORTS_UPROBES
  199. def_bool y
  200. config ARCH_HAS_DMA_SET_COHERENT_MASK
  201. bool
  202. config GENERIC_ISA_DMA
  203. bool
  204. config FIQ
  205. bool
  206. config NEED_RET_TO_USER
  207. bool
  208. config ARCH_MTD_XIP
  209. bool
  210. config ARM_PATCH_PHYS_VIRT
  211. bool "Patch physical to virtual translations at runtime" if EMBEDDED
  212. default y
  213. depends on !XIP_KERNEL && MMU
  214. help
  215. Patch phys-to-virt and virt-to-phys translation functions at
  216. boot and module load time according to the position of the
  217. kernel in system memory.
  218. This can only be used with non-XIP MMU kernels where the base
  219. of physical memory is at a 16MB boundary.
  220. Only disable this option if you know that you do not require
  221. this feature (eg, building a kernel for a single machine) and
  222. you need to shrink the kernel to the minimal size.
  223. config NEED_MACH_IO_H
  224. bool
  225. help
  226. Select this when mach/io.h is required to provide special
  227. definitions for this platform. The need for mach/io.h should
  228. be avoided when possible.
  229. config NEED_MACH_MEMORY_H
  230. bool
  231. help
  232. Select this when mach/memory.h is required to provide special
  233. definitions for this platform. The need for mach/memory.h should
  234. be avoided when possible.
  235. config PHYS_OFFSET
  236. hex "Physical address of main memory" if MMU
  237. depends on !ARM_PATCH_PHYS_VIRT
  238. default DRAM_BASE if !MMU
  239. default 0x00000000 if ARCH_EBSA110 || \
  240. ARCH_FOOTBRIDGE
  241. default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
  242. default 0x20000000 if ARCH_S5PV210
  243. default 0xc0000000 if ARCH_SA1100
  244. help
  245. Please provide the physical address corresponding to the
  246. location of main memory in your system.
  247. config GENERIC_BUG
  248. def_bool y
  249. depends on BUG
  250. config PGTABLE_LEVELS
  251. int
  252. default 3 if ARM_LPAE
  253. default 2
  254. menu "System Type"
  255. config MMU
  256. bool "MMU-based Paged Memory Management Support"
  257. default y
  258. help
  259. Select if you want MMU-based virtualised addressing space
  260. support by paged memory management. If unsure, say 'Y'.
  261. config ARCH_MMAP_RND_BITS_MIN
  262. default 8
  263. config ARCH_MMAP_RND_BITS_MAX
  264. default 14 if PAGE_OFFSET=0x40000000
  265. default 15 if PAGE_OFFSET=0x80000000
  266. default 16
  267. #
  268. # The "ARM system type" choice list is ordered alphabetically by option
  269. # text. Please add new entries in the option alphabetic order.
  270. #
  271. choice
  272. prompt "ARM system type"
  273. default ARM_SINGLE_ARMV7M if !MMU
  274. default ARCH_MULTIPLATFORM if MMU
  275. config ARCH_MULTIPLATFORM
  276. bool "Allow multiple platforms to be selected"
  277. depends on MMU
  278. select ARCH_FLATMEM_ENABLE
  279. select ARCH_SPARSEMEM_ENABLE
  280. select ARCH_SELECT_MEMORY_MODEL
  281. select ARM_HAS_SG_CHAIN
  282. select ARM_PATCH_PHYS_VIRT
  283. select AUTO_ZRELADDR
  284. select TIMER_OF
  285. select COMMON_CLK
  286. select GENERIC_CLOCKEVENTS
  287. select GENERIC_IRQ_MULTI_HANDLER
  288. select HAVE_PCI
  289. select PCI_DOMAINS_GENERIC if PCI
  290. select SPARSE_IRQ
  291. select USE_OF
  292. config ARM_SINGLE_ARMV7M
  293. bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
  294. depends on !MMU
  295. select ARM_NVIC
  296. select AUTO_ZRELADDR
  297. select TIMER_OF
  298. select COMMON_CLK
  299. select CPU_V7M
  300. select GENERIC_CLOCKEVENTS
  301. select NO_IOPORT_MAP
  302. select SPARSE_IRQ
  303. select USE_OF
  304. config ARCH_EBSA110
  305. bool "EBSA-110"
  306. select ARCH_USES_GETTIMEOFFSET
  307. select CPU_SA110
  308. select ISA
  309. select NEED_MACH_IO_H
  310. select NEED_MACH_MEMORY_H
  311. select NO_IOPORT_MAP
  312. help
  313. This is an evaluation board for the StrongARM processor available
  314. from Digital. It has limited hardware on-board, including an
  315. Ethernet interface, two PCMCIA sockets, two serial ports and a
  316. parallel port.
  317. config ARCH_EP93XX
  318. bool "EP93xx-based"
  319. select ARCH_SPARSEMEM_ENABLE
  320. select ARM_AMBA
  321. imply ARM_PATCH_PHYS_VIRT
  322. select ARM_VIC
  323. select AUTO_ZRELADDR
  324. select CLKDEV_LOOKUP
  325. select CLKSRC_MMIO
  326. select CPU_ARM920T
  327. select GENERIC_CLOCKEVENTS
  328. select GPIOLIB
  329. select HAVE_LEGACY_CLK
  330. help
  331. This enables support for the Cirrus EP93xx series of CPUs.
  332. config ARCH_FOOTBRIDGE
  333. bool "FootBridge"
  334. select CPU_SA110
  335. select FOOTBRIDGE
  336. select GENERIC_CLOCKEVENTS
  337. select HAVE_IDE
  338. select NEED_MACH_IO_H if !MMU
  339. select NEED_MACH_MEMORY_H
  340. help
  341. Support for systems based on the DC21285 companion chip
  342. ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
  343. config ARCH_IOP32X
  344. bool "IOP32x-based"
  345. depends on MMU
  346. select CPU_XSCALE
  347. select GPIO_IOP
  348. select GPIOLIB
  349. select NEED_RET_TO_USER
  350. select FORCE_PCI
  351. select PLAT_IOP
  352. help
  353. Support for Intel's 80219 and IOP32X (XScale) family of
  354. processors.
  355. config ARCH_IXP4XX
  356. bool "IXP4xx-based"
  357. depends on MMU
  358. select ARCH_HAS_DMA_SET_COHERENT_MASK
  359. select ARCH_SUPPORTS_BIG_ENDIAN
  360. select CPU_XSCALE
  361. select DMABOUNCE if PCI
  362. select GENERIC_CLOCKEVENTS
  363. select GENERIC_IRQ_MULTI_HANDLER
  364. select GPIO_IXP4XX
  365. select GPIOLIB
  366. select HAVE_PCI
  367. select IXP4XX_IRQ
  368. select IXP4XX_TIMER
  369. select NEED_MACH_IO_H
  370. select USB_EHCI_BIG_ENDIAN_DESC
  371. select USB_EHCI_BIG_ENDIAN_MMIO
  372. help
  373. Support for Intel's IXP4XX (XScale) family of processors.
  374. config ARCH_DOVE
  375. bool "Marvell Dove"
  376. select CPU_PJ4
  377. select GENERIC_CLOCKEVENTS
  378. select GENERIC_IRQ_MULTI_HANDLER
  379. select GPIOLIB
  380. select HAVE_PCI
  381. select MVEBU_MBUS
  382. select PINCTRL
  383. select PINCTRL_DOVE
  384. select PLAT_ORION_LEGACY
  385. select SPARSE_IRQ
  386. select PM_GENERIC_DOMAINS if PM
  387. help
  388. Support for the Marvell Dove SoC 88AP510
  389. config ARCH_PXA
  390. bool "PXA2xx/PXA3xx-based"
  391. depends on MMU
  392. select ARCH_MTD_XIP
  393. select ARM_CPU_SUSPEND if PM
  394. select AUTO_ZRELADDR
  395. select COMMON_CLK
  396. select CLKSRC_PXA
  397. select CLKSRC_MMIO
  398. select TIMER_OF
  399. select CPU_XSCALE if !CPU_XSC3
  400. select GENERIC_CLOCKEVENTS
  401. select GENERIC_IRQ_MULTI_HANDLER
  402. select GPIO_PXA
  403. select GPIOLIB
  404. select HAVE_IDE
  405. select IRQ_DOMAIN
  406. select PLAT_PXA
  407. select SPARSE_IRQ
  408. help
  409. Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
  410. config ARCH_RPC
  411. bool "RiscPC"
  412. depends on MMU
  413. select ARCH_ACORN
  414. select ARCH_MAY_HAVE_PC_FDC
  415. select ARCH_SPARSEMEM_ENABLE
  416. select ARM_HAS_SG_CHAIN
  417. select CPU_SA110
  418. select FIQ
  419. select HAVE_IDE
  420. select HAVE_PATA_PLATFORM
  421. select ISA_DMA_API
  422. select NEED_MACH_IO_H
  423. select NEED_MACH_MEMORY_H
  424. select NO_IOPORT_MAP
  425. help
  426. On the Acorn Risc-PC, Linux can support the internal IDE disk and
  427. CD-ROM interface, serial and parallel port, and the floppy drive.
  428. config ARCH_SA1100
  429. bool "SA1100-based"
  430. select ARCH_MTD_XIP
  431. select ARCH_SPARSEMEM_ENABLE
  432. select CLKSRC_MMIO
  433. select CLKSRC_PXA
  434. select TIMER_OF if OF
  435. select COMMON_CLK
  436. select CPU_FREQ
  437. select CPU_SA1100
  438. select GENERIC_CLOCKEVENTS
  439. select GENERIC_IRQ_MULTI_HANDLER
  440. select GPIOLIB
  441. select HAVE_IDE
  442. select IRQ_DOMAIN
  443. select ISA
  444. select NEED_MACH_MEMORY_H
  445. select SPARSE_IRQ
  446. help
  447. Support for StrongARM 11x0 based boards.
  448. config ARCH_S3C24XX
  449. bool "Samsung S3C24XX SoCs"
  450. select ATAGS
  451. select CLKSRC_SAMSUNG_PWM
  452. select GENERIC_CLOCKEVENTS
  453. select GPIO_SAMSUNG
  454. select GPIOLIB
  455. select GENERIC_IRQ_MULTI_HANDLER
  456. select HAVE_S3C2410_I2C if I2C
  457. select HAVE_S3C_RTC if RTC_CLASS
  458. select NEED_MACH_IO_H
  459. select S3C2410_WATCHDOG
  460. select SAMSUNG_ATAGS
  461. select USE_OF
  462. select WATCHDOG
  463. help
  464. Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
  465. and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
  466. (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
  467. Samsung SMDK2410 development board (and derivatives).
  468. config ARCH_OMAP1
  469. bool "TI OMAP1"
  470. depends on MMU
  471. select ARCH_HAS_HOLES_MEMORYMODEL
  472. select ARCH_OMAP
  473. select CLKDEV_LOOKUP
  474. select CLKSRC_MMIO
  475. select GENERIC_CLOCKEVENTS
  476. select GENERIC_IRQ_CHIP
  477. select GENERIC_IRQ_MULTI_HANDLER
  478. select GPIOLIB
  479. select HAVE_IDE
  480. select HAVE_LEGACY_CLK
  481. select IRQ_DOMAIN
  482. select NEED_MACH_IO_H if PCCARD
  483. select NEED_MACH_MEMORY_H
  484. select SPARSE_IRQ
  485. help
  486. Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
  487. endchoice
  488. menu "Multiple platform selection"
  489. depends on ARCH_MULTIPLATFORM
  490. comment "CPU Core family selection"
  491. config ARCH_MULTI_V4
  492. bool "ARMv4 based platforms (FA526)"
  493. depends on !ARCH_MULTI_V6_V7
  494. select ARCH_MULTI_V4_V5
  495. select CPU_FA526
  496. config ARCH_MULTI_V4T
  497. bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
  498. depends on !ARCH_MULTI_V6_V7
  499. select ARCH_MULTI_V4_V5
  500. select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
  501. CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
  502. CPU_ARM925T || CPU_ARM940T)
  503. config ARCH_MULTI_V5
  504. bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
  505. depends on !ARCH_MULTI_V6_V7
  506. select ARCH_MULTI_V4_V5
  507. select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
  508. CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
  509. CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
  510. config ARCH_MULTI_V4_V5
  511. bool
  512. config ARCH_MULTI_V6
  513. bool "ARMv6 based platforms (ARM11)"
  514. select ARCH_MULTI_V6_V7
  515. select CPU_V6K
  516. config ARCH_MULTI_V7
  517. bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
  518. default y
  519. select ARCH_MULTI_V6_V7
  520. select CPU_V7
  521. select HAVE_SMP
  522. config ARCH_MULTI_V6_V7
  523. bool
  524. select MIGHT_HAVE_CACHE_L2X0
  525. config ARCH_MULTI_CPU_AUTO
  526. def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
  527. select ARCH_MULTI_V5
  528. endmenu
  529. config ARCH_VIRT
  530. bool "Dummy Virtual Machine"
  531. depends on ARCH_MULTI_V7
  532. select ARM_AMBA
  533. select ARM_GIC
  534. select ARM_GIC_V2M if PCI
  535. select ARM_GIC_V3
  536. select ARM_GIC_V3_ITS if PCI
  537. select ARM_PSCI
  538. select HAVE_ARM_ARCH_TIMER
  539. select ARCH_SUPPORTS_BIG_ENDIAN
  540. #
  541. # This is sorted alphabetically by mach-* pathname. However, plat-*
  542. # Kconfigs may be included either alphabetically (according to the
  543. # plat- suffix) or along side the corresponding mach-* source.
  544. #
  545. source "arch/arm/mach-actions/Kconfig"
  546. source "arch/arm/mach-alpine/Kconfig"
  547. source "arch/arm/mach-artpec/Kconfig"
  548. source "arch/arm/mach-asm9260/Kconfig"
  549. source "arch/arm/mach-aspeed/Kconfig"
  550. source "arch/arm/mach-at91/Kconfig"
  551. source "arch/arm/mach-axxia/Kconfig"
  552. source "arch/arm/mach-bcm/Kconfig"
  553. source "arch/arm/mach-berlin/Kconfig"
  554. source "arch/arm/mach-clps711x/Kconfig"
  555. source "arch/arm/mach-cns3xxx/Kconfig"
  556. source "arch/arm/mach-davinci/Kconfig"
  557. source "arch/arm/mach-digicolor/Kconfig"
  558. source "arch/arm/mach-dove/Kconfig"
  559. source "arch/arm/mach-ep93xx/Kconfig"
  560. source "arch/arm/mach-exynos/Kconfig"
  561. source "arch/arm/mach-footbridge/Kconfig"
  562. source "arch/arm/mach-gemini/Kconfig"
  563. source "arch/arm/mach-highbank/Kconfig"
  564. source "arch/arm/mach-hisi/Kconfig"
  565. source "arch/arm/mach-imx/Kconfig"
  566. source "arch/arm/mach-integrator/Kconfig"
  567. source "arch/arm/mach-iop32x/Kconfig"
  568. source "arch/arm/mach-ixp4xx/Kconfig"
  569. source "arch/arm/mach-keystone/Kconfig"
  570. source "arch/arm/mach-lpc32xx/Kconfig"
  571. source "arch/arm/mach-mediatek/Kconfig"
  572. source "arch/arm/mach-meson/Kconfig"
  573. source "arch/arm/mach-milbeaut/Kconfig"
  574. source "arch/arm/mach-mmp/Kconfig"
  575. source "arch/arm/mach-moxart/Kconfig"
  576. source "arch/arm/mach-mstar/Kconfig"
  577. source "arch/arm/mach-mv78xx0/Kconfig"
  578. source "arch/arm/mach-mvebu/Kconfig"
  579. source "arch/arm/mach-mxs/Kconfig"
  580. source "arch/arm/mach-nomadik/Kconfig"
  581. source "arch/arm/mach-npcm/Kconfig"
  582. source "arch/arm/mach-nspire/Kconfig"
  583. source "arch/arm/plat-omap/Kconfig"
  584. source "arch/arm/mach-omap1/Kconfig"
  585. source "arch/arm/mach-omap2/Kconfig"
  586. source "arch/arm/mach-orion5x/Kconfig"
  587. source "arch/arm/mach-oxnas/Kconfig"
  588. source "arch/arm/mach-picoxcell/Kconfig"
  589. source "arch/arm/mach-prima2/Kconfig"
  590. source "arch/arm/mach-pxa/Kconfig"
  591. source "arch/arm/plat-pxa/Kconfig"
  592. source "arch/arm/mach-qcom/Kconfig"
  593. source "arch/arm/mach-rda/Kconfig"
  594. source "arch/arm/mach-realtek/Kconfig"
  595. source "arch/arm/mach-realview/Kconfig"
  596. source "arch/arm/mach-rockchip/Kconfig"
  597. source "arch/arm/mach-s3c/Kconfig"
  598. source "arch/arm/mach-s5pv210/Kconfig"
  599. source "arch/arm/mach-sa1100/Kconfig"
  600. source "arch/arm/mach-shmobile/Kconfig"
  601. source "arch/arm/mach-socfpga/Kconfig"
  602. source "arch/arm/mach-spear/Kconfig"
  603. source "arch/arm/mach-sti/Kconfig"
  604. source "arch/arm/mach-stm32/Kconfig"
  605. source "arch/arm/mach-sunxi/Kconfig"
  606. source "arch/arm/mach-tango/Kconfig"
  607. source "arch/arm/mach-tegra/Kconfig"
  608. source "arch/arm/mach-u300/Kconfig"
  609. source "arch/arm/mach-uniphier/Kconfig"
  610. source "arch/arm/mach-ux500/Kconfig"
  611. source "arch/arm/mach-versatile/Kconfig"
  612. source "arch/arm/mach-vexpress/Kconfig"
  613. source "arch/arm/mach-vt8500/Kconfig"
  614. source "arch/arm/mach-zx/Kconfig"
  615. source "arch/arm/mach-zynq/Kconfig"
  616. # ARMv7-M architecture
  617. config ARCH_EFM32
  618. bool "Energy Micro efm32"
  619. depends on ARM_SINGLE_ARMV7M
  620. select GPIOLIB
  621. help
  622. Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
  623. processors.
  624. config ARCH_LPC18XX
  625. bool "NXP LPC18xx/LPC43xx"
  626. depends on ARM_SINGLE_ARMV7M
  627. select ARCH_HAS_RESET_CONTROLLER
  628. select ARM_AMBA
  629. select CLKSRC_LPC32XX
  630. select PINCTRL
  631. help
  632. Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
  633. high performance microcontrollers.
  634. config ARCH_MPS2
  635. bool "ARM MPS2 platform"
  636. depends on ARM_SINGLE_ARMV7M
  637. select ARM_AMBA
  638. select CLKSRC_MPS2
  639. help
  640. Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
  641. with a range of available cores like Cortex-M3/M4/M7.
  642. Please, note that depends which Application Note is used memory map
  643. for the platform may vary, so adjustment of RAM base might be needed.
  644. # Definitions to make life easier
  645. config ARCH_ACORN
  646. bool
  647. config PLAT_IOP
  648. bool
  649. select GENERIC_CLOCKEVENTS
  650. config PLAT_ORION
  651. bool
  652. select CLKSRC_MMIO
  653. select COMMON_CLK
  654. select GENERIC_IRQ_CHIP
  655. select IRQ_DOMAIN
  656. config PLAT_ORION_LEGACY
  657. bool
  658. select PLAT_ORION
  659. config PLAT_PXA
  660. bool
  661. config PLAT_VERSATILE
  662. bool
  663. source "arch/arm/mm/Kconfig"
  664. config IWMMXT
  665. bool "Enable iWMMXt support"
  666. depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
  667. default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
  668. help
  669. Enable support for iWMMXt context switching at run time if
  670. running on a CPU that supports it.
  671. if !MMU
  672. source "arch/arm/Kconfig-nommu"
  673. endif
  674. config PJ4B_ERRATA_4742
  675. bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
  676. depends on CPU_PJ4B && MACH_ARMADA_370
  677. default y
  678. help
  679. When coming out of either a Wait for Interrupt (WFI) or a Wait for
  680. Event (WFE) IDLE states, a specific timing sensitivity exists between
  681. the retiring WFI/WFE instructions and the newly issued subsequent
  682. instructions. This sensitivity can result in a CPU hang scenario.
  683. Workaround:
  684. The software must insert either a Data Synchronization Barrier (DSB)
  685. or Data Memory Barrier (DMB) command immediately after the WFI/WFE
  686. instruction
  687. config ARM_ERRATA_326103
  688. bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
  689. depends on CPU_V6
  690. help
  691. Executing a SWP instruction to read-only memory does not set bit 11
  692. of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
  693. treat the access as a read, preventing a COW from occurring and
  694. causing the faulting task to livelock.
  695. config ARM_ERRATA_411920
  696. bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
  697. depends on CPU_V6 || CPU_V6K
  698. help
  699. Invalidation of the Instruction Cache operation can
  700. fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
  701. It does not affect the MPCore. This option enables the ARM Ltd.
  702. recommended workaround.
  703. config ARM_ERRATA_430973
  704. bool "ARM errata: Stale prediction on replaced interworking branch"
  705. depends on CPU_V7
  706. help
  707. This option enables the workaround for the 430973 Cortex-A8
  708. r1p* erratum. If a code sequence containing an ARM/Thumb
  709. interworking branch is replaced with another code sequence at the
  710. same virtual address, whether due to self-modifying code or virtual
  711. to physical address re-mapping, Cortex-A8 does not recover from the
  712. stale interworking branch prediction. This results in Cortex-A8
  713. executing the new code sequence in the incorrect ARM or Thumb state.
  714. The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
  715. and also flushes the branch target cache at every context switch.
  716. Note that setting specific bits in the ACTLR register may not be
  717. available in non-secure mode.
  718. config ARM_ERRATA_458693
  719. bool "ARM errata: Processor deadlock when a false hazard is created"
  720. depends on CPU_V7
  721. depends on !ARCH_MULTIPLATFORM
  722. help
  723. This option enables the workaround for the 458693 Cortex-A8 (r2p0)
  724. erratum. For very specific sequences of memory operations, it is
  725. possible for a hazard condition intended for a cache line to instead
  726. be incorrectly associated with a different cache line. This false
  727. hazard might then cause a processor deadlock. The workaround enables
  728. the L1 caching of the NEON accesses and disables the PLD instruction
  729. in the ACTLR register. Note that setting specific bits in the ACTLR
  730. register may not be available in non-secure mode.
  731. config ARM_ERRATA_460075
  732. bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
  733. depends on CPU_V7
  734. depends on !ARCH_MULTIPLATFORM
  735. help
  736. This option enables the workaround for the 460075 Cortex-A8 (r2p0)
  737. erratum. Any asynchronous access to the L2 cache may encounter a
  738. situation in which recent store transactions to the L2 cache are lost
  739. and overwritten with stale memory contents from external memory. The
  740. workaround disables the write-allocate mode for the L2 cache via the
  741. ACTLR register. Note that setting specific bits in the ACTLR register
  742. may not be available in non-secure mode.
  743. config ARM_ERRATA_742230
  744. bool "ARM errata: DMB operation may be faulty"
  745. depends on CPU_V7 && SMP
  746. depends on !ARCH_MULTIPLATFORM
  747. help
  748. This option enables the workaround for the 742230 Cortex-A9
  749. (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
  750. between two write operations may not ensure the correct visibility
  751. ordering of the two writes. This workaround sets a specific bit in
  752. the diagnostic register of the Cortex-A9 which causes the DMB
  753. instruction to behave as a DSB, ensuring the correct behaviour of
  754. the two writes.
  755. config ARM_ERRATA_742231
  756. bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
  757. depends on CPU_V7 && SMP
  758. depends on !ARCH_MULTIPLATFORM
  759. help
  760. This option enables the workaround for the 742231 Cortex-A9
  761. (r2p0..r2p2) erratum. Under certain conditions, specific to the
  762. Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
  763. accessing some data located in the same cache line, may get corrupted
  764. data due to bad handling of the address hazard when the line gets
  765. replaced from one of the CPUs at the same time as another CPU is
  766. accessing it. This workaround sets specific bits in the diagnostic
  767. register of the Cortex-A9 which reduces the linefill issuing
  768. capabilities of the processor.
  769. config ARM_ERRATA_643719
  770. bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
  771. depends on CPU_V7 && SMP
  772. default y
  773. help
  774. This option enables the workaround for the 643719 Cortex-A9 (prior to
  775. r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
  776. register returns zero when it should return one. The workaround
  777. corrects this value, ensuring cache maintenance operations which use
  778. it behave as intended and avoiding data corruption.
  779. config ARM_ERRATA_720789
  780. bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
  781. depends on CPU_V7
  782. help
  783. This option enables the workaround for the 720789 Cortex-A9 (prior to
  784. r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
  785. broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
  786. As a consequence of this erratum, some TLB entries which should be
  787. invalidated are not, resulting in an incoherency in the system page
  788. tables. The workaround changes the TLB flushing routines to invalidate
  789. entries regardless of the ASID.
  790. config ARM_ERRATA_743622
  791. bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
  792. depends on CPU_V7
  793. depends on !ARCH_MULTIPLATFORM
  794. help
  795. This option enables the workaround for the 743622 Cortex-A9
  796. (r2p*) erratum. Under very rare conditions, a faulty
  797. optimisation in the Cortex-A9 Store Buffer may lead to data
  798. corruption. This workaround sets a specific bit in the diagnostic
  799. register of the Cortex-A9 which disables the Store Buffer
  800. optimisation, preventing the defect from occurring. This has no
  801. visible impact on the overall performance or power consumption of the
  802. processor.
  803. config ARM_ERRATA_751472
  804. bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
  805. depends on CPU_V7
  806. depends on !ARCH_MULTIPLATFORM
  807. help
  808. This option enables the workaround for the 751472 Cortex-A9 (prior
  809. to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
  810. completion of a following broadcasted operation if the second
  811. operation is received by a CPU before the ICIALLUIS has completed,
  812. potentially leading to corrupted entries in the cache or TLB.
  813. config ARM_ERRATA_754322
  814. bool "ARM errata: possible faulty MMU translations following an ASID switch"
  815. depends on CPU_V7
  816. help
  817. This option enables the workaround for the 754322 Cortex-A9 (r2p*,
  818. r3p*) erratum. A speculative memory access may cause a page table walk
  819. which starts prior to an ASID switch but completes afterwards. This
  820. can populate the micro-TLB with a stale entry which may be hit with
  821. the new ASID. This workaround places two dsb instructions in the mm
  822. switching code so that no page table walks can cross the ASID switch.
  823. config ARM_ERRATA_754327
  824. bool "ARM errata: no automatic Store Buffer drain"
  825. depends on CPU_V7 && SMP
  826. help
  827. This option enables the workaround for the 754327 Cortex-A9 (prior to
  828. r2p0) erratum. The Store Buffer does not have any automatic draining
  829. mechanism and therefore a livelock may occur if an external agent
  830. continuously polls a memory location waiting to observe an update.
  831. This workaround defines cpu_relax() as smp_mb(), preventing correctly
  832. written polling loops from denying visibility of updates to memory.
  833. config ARM_ERRATA_364296
  834. bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
  835. depends on CPU_V6
  836. help
  837. This options enables the workaround for the 364296 ARM1136
  838. r0p2 erratum (possible cache data corruption with
  839. hit-under-miss enabled). It sets the undocumented bit 31 in
  840. the auxiliary control register and the FI bit in the control
  841. register, thus disabling hit-under-miss without putting the
  842. processor into full low interrupt latency mode. ARM11MPCore
  843. is not affected.
  844. config ARM_ERRATA_764369
  845. bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
  846. depends on CPU_V7 && SMP
  847. help
  848. This option enables the workaround for erratum 764369
  849. affecting Cortex-A9 MPCore with two or more processors (all
  850. current revisions). Under certain timing circumstances, a data
  851. cache line maintenance operation by MVA targeting an Inner
  852. Shareable memory region may fail to proceed up to either the
  853. Point of Coherency or to the Point of Unification of the
  854. system. This workaround adds a DSB instruction before the
  855. relevant cache maintenance functions and sets a specific bit
  856. in the diagnostic control register of the SCU.
  857. config ARM_ERRATA_775420
  858. bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
  859. depends on CPU_V7
  860. help
  861. This option enables the workaround for the 775420 Cortex-A9 (r2p2,
  862. r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
  863. operation aborts with MMU exception, it might cause the processor
  864. to deadlock. This workaround puts DSB before executing ISB if
  865. an abort may occur on cache maintenance.
  866. config ARM_ERRATA_798181
  867. bool "ARM errata: TLBI/DSB failure on Cortex-A15"
  868. depends on CPU_V7 && SMP
  869. help
  870. On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
  871. adequately shooting down all use of the old entries. This
  872. option enables the Linux kernel workaround for this erratum
  873. which sends an IPI to the CPUs that are running the same ASID
  874. as the one being invalidated.
  875. config ARM_ERRATA_773022
  876. bool "ARM errata: incorrect instructions may be executed from loop buffer"
  877. depends on CPU_V7
  878. help
  879. This option enables the workaround for the 773022 Cortex-A15
  880. (up to r0p4) erratum. In certain rare sequences of code, the
  881. loop buffer may deliver incorrect instructions. This
  882. workaround disables the loop buffer to avoid the erratum.
  883. config ARM_ERRATA_818325_852422
  884. bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
  885. depends on CPU_V7
  886. help
  887. This option enables the workaround for:
  888. - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
  889. instruction might deadlock. Fixed in r0p1.
  890. - Cortex-A12 852422: Execution of a sequence of instructions might
  891. lead to either a data corruption or a CPU deadlock. Not fixed in
  892. any Cortex-A12 cores yet.
  893. This workaround for all both errata involves setting bit[12] of the
  894. Feature Register. This bit disables an optimisation applied to a
  895. sequence of 2 instructions that use opposing condition codes.
  896. config ARM_ERRATA_821420
  897. bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
  898. depends on CPU_V7
  899. help
  900. This option enables the workaround for the 821420 Cortex-A12
  901. (all revs) erratum. In very rare timing conditions, a sequence
  902. of VMOV to Core registers instructions, for which the second
  903. one is in the shadow of a branch or abort, can lead to a
  904. deadlock when the VMOV instructions are issued out-of-order.
  905. config ARM_ERRATA_825619
  906. bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
  907. depends on CPU_V7
  908. help
  909. This option enables the workaround for the 825619 Cortex-A12
  910. (all revs) erratum. Within rare timing constraints, executing a
  911. DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
  912. and Device/Strongly-Ordered loads and stores might cause deadlock
  913. config ARM_ERRATA_857271
  914. bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
  915. depends on CPU_V7
  916. help
  917. This option enables the workaround for the 857271 Cortex-A12
  918. (all revs) erratum. Under very rare timing conditions, the CPU might
  919. hang. The workaround is expected to have a < 1% performance impact.
  920. config ARM_ERRATA_852421
  921. bool "ARM errata: A17: DMB ST might fail to create order between stores"
  922. depends on CPU_V7
  923. help
  924. This option enables the workaround for the 852421 Cortex-A17
  925. (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
  926. execution of a DMB ST instruction might fail to properly order
  927. stores from GroupA and stores from GroupB.
  928. config ARM_ERRATA_852423
  929. bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
  930. depends on CPU_V7
  931. help
  932. This option enables the workaround for:
  933. - Cortex-A17 852423: Execution of a sequence of instructions might
  934. lead to either a data corruption or a CPU deadlock. Not fixed in
  935. any Cortex-A17 cores yet.
  936. This is identical to Cortex-A12 erratum 852422. It is a separate
  937. config option from the A12 erratum due to the way errata are checked
  938. for and handled.
  939. config ARM_ERRATA_857272
  940. bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
  941. depends on CPU_V7
  942. help
  943. This option enables the workaround for the 857272 Cortex-A17 erratum.
  944. This erratum is not known to be fixed in any A17 revision.
  945. This is identical to Cortex-A12 erratum 857271. It is a separate
  946. config option from the A12 erratum due to the way errata are checked
  947. for and handled.
  948. endmenu
  949. source "arch/arm/common/Kconfig"
  950. menu "Bus support"
  951. config ISA
  952. bool
  953. help
  954. Find out whether you have ISA slots on your motherboard. ISA is the
  955. name of a bus system, i.e. the way the CPU talks to the other stuff
  956. inside your box. Other bus systems are PCI, EISA, MicroChannel
  957. (MCA) or VESA. ISA is an older system, now being displaced by PCI;
  958. newer boards don't support it. If you have ISA, say Y, otherwise N.
  959. # Select ISA DMA controller support
  960. config ISA_DMA
  961. bool
  962. select ISA_DMA_API
  963. # Select ISA DMA interface
  964. config ISA_DMA_API
  965. bool
  966. config PCI_NANOENGINE
  967. bool "BSE nanoEngine PCI support"
  968. depends on SA1100_NANOENGINE
  969. help
  970. Enable PCI on the BSE nanoEngine board.
  971. config ARM_ERRATA_814220
  972. bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
  973. depends on CPU_V7
  974. help
  975. The v7 ARM states that all cache and branch predictor maintenance
  976. operations that do not specify an address execute, relative to
  977. each other, in program order.
  978. However, because of this erratum, an L2 set/way cache maintenance
  979. operation can overtake an L1 set/way cache maintenance operation.
  980. This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
  981. r0p4, r0p5.
  982. endmenu
  983. menu "Kernel Features"
  984. config HAVE_SMP
  985. bool
  986. help
  987. This option should be selected by machines which have an SMP-
  988. capable CPU.
  989. The only effect of this option is to make the SMP-related
  990. options available to the user for configuration.
  991. config SMP
  992. bool "Symmetric Multi-Processing"
  993. depends on CPU_V6K || CPU_V7
  994. depends on GENERIC_CLOCKEVENTS
  995. depends on HAVE_SMP
  996. depends on MMU || ARM_MPU
  997. select IRQ_WORK
  998. help
  999. This enables support for systems with more than one CPU. If you have
  1000. a system with only one CPU, say N. If you have a system with more
  1001. than one CPU, say Y.
  1002. If you say N here, the kernel will run on uni- and multiprocessor
  1003. machines, but will use only one CPU of a multiprocessor machine. If
  1004. you say Y here, the kernel will run on many, but not all,
  1005. uniprocessor machines. On a uniprocessor machine, the kernel
  1006. will run faster if you say N here.
  1007. See also <file:Documentation/x86/i386/IO-APIC.rst>,
  1008. <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
  1009. <http://tldp.org/HOWTO/SMP-HOWTO.html>.
  1010. If you don't know what to do here, say N.
  1011. config SMP_ON_UP
  1012. bool "Allow booting SMP kernel on uniprocessor systems"
  1013. depends on SMP && !XIP_KERNEL && MMU
  1014. default y
  1015. help
  1016. SMP kernels contain instructions which fail on non-SMP processors.
  1017. Enabling this option allows the kernel to modify itself to make
  1018. these instructions safe. Disabling it allows about 1K of space
  1019. savings.
  1020. If you don't know what to do here, say Y.
  1021. config ARM_CPU_TOPOLOGY
  1022. bool "Support cpu topology definition"
  1023. depends on SMP && CPU_V7
  1024. default y
  1025. help
  1026. Support ARM cpu topology definition. The MPIDR register defines
  1027. affinity between processors which is then used to describe the cpu
  1028. topology of an ARM System.
  1029. config SCHED_MC
  1030. bool "Multi-core scheduler support"
  1031. depends on ARM_CPU_TOPOLOGY
  1032. help
  1033. Multi-core scheduler support improves the CPU scheduler's decision
  1034. making when dealing with multi-core CPU chips at a cost of slightly
  1035. increased overhead in some places. If unsure say N here.
  1036. config SCHED_SMT
  1037. bool "SMT scheduler support"
  1038. depends on ARM_CPU_TOPOLOGY
  1039. help
  1040. Improves the CPU scheduler's decision making when dealing with
  1041. MultiThreading at a cost of slightly increased overhead in some
  1042. places. If unsure say N here.
  1043. config HAVE_ARM_SCU
  1044. bool
  1045. help
  1046. This option enables support for the ARM snoop control unit
  1047. config HAVE_ARM_ARCH_TIMER
  1048. bool "Architected timer support"
  1049. depends on CPU_V7
  1050. select ARM_ARCH_TIMER
  1051. help
  1052. This option enables support for the ARM architected timer
  1053. config HAVE_ARM_TWD
  1054. bool
  1055. help
  1056. This options enables support for the ARM timer and watchdog unit
  1057. config MCPM
  1058. bool "Multi-Cluster Power Management"
  1059. depends on CPU_V7 && SMP
  1060. help
  1061. This option provides the common power management infrastructure
  1062. for (multi-)cluster based systems, such as big.LITTLE based
  1063. systems.
  1064. config MCPM_QUAD_CLUSTER
  1065. bool
  1066. depends on MCPM
  1067. help
  1068. To avoid wasting resources unnecessarily, MCPM only supports up
  1069. to 2 clusters by default.
  1070. Platforms with 3 or 4 clusters that use MCPM must select this
  1071. option to allow the additional clusters to be managed.
  1072. config BIG_LITTLE
  1073. bool "big.LITTLE support (Experimental)"
  1074. depends on CPU_V7 && SMP
  1075. select MCPM
  1076. help
  1077. This option enables support selections for the big.LITTLE
  1078. system architecture.
  1079. config BL_SWITCHER
  1080. bool "big.LITTLE switcher support"
  1081. depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
  1082. select CPU_PM
  1083. help
  1084. The big.LITTLE "switcher" provides the core functionality to
  1085. transparently handle transition between a cluster of A15's
  1086. and a cluster of A7's in a big.LITTLE system.
  1087. config BL_SWITCHER_DUMMY_IF
  1088. tristate "Simple big.LITTLE switcher user interface"
  1089. depends on BL_SWITCHER && DEBUG_KERNEL
  1090. help
  1091. This is a simple and dummy char dev interface to control
  1092. the big.LITTLE switcher core code. It is meant for
  1093. debugging purposes only.
  1094. choice
  1095. prompt "Memory split"
  1096. depends on MMU
  1097. default VMSPLIT_3G
  1098. help
  1099. Select the desired split between kernel and user memory.
  1100. If you are not absolutely sure what you are doing, leave this
  1101. option alone!
  1102. config VMSPLIT_3G
  1103. bool "3G/1G user/kernel split"
  1104. config VMSPLIT_3G_OPT
  1105. depends on !ARM_LPAE
  1106. bool "3G/1G user/kernel split (for full 1G low memory)"
  1107. config VMSPLIT_2G
  1108. bool "2G/2G user/kernel split"
  1109. config VMSPLIT_1G
  1110. bool "1G/3G user/kernel split"
  1111. endchoice
  1112. config PAGE_OFFSET
  1113. hex
  1114. default PHYS_OFFSET if !MMU
  1115. default 0x40000000 if VMSPLIT_1G
  1116. default 0x80000000 if VMSPLIT_2G
  1117. default 0xB0000000 if VMSPLIT_3G_OPT
  1118. default 0xC0000000
  1119. config NR_CPUS
  1120. int "Maximum number of CPUs (2-32)"
  1121. range 2 32
  1122. depends on SMP
  1123. default "4"
  1124. config HOTPLUG_CPU
  1125. bool "Support for hot-pluggable CPUs"
  1126. depends on SMP
  1127. select GENERIC_IRQ_MIGRATION
  1128. help
  1129. Say Y here to experiment with turning CPUs off and on. CPUs
  1130. can be controlled through /sys/devices/system/cpu.
  1131. config ARM_PSCI
  1132. bool "Support for the ARM Power State Coordination Interface (PSCI)"
  1133. depends on HAVE_ARM_SMCCC
  1134. select ARM_PSCI_FW
  1135. help
  1136. Say Y here if you want Linux to communicate with system firmware
  1137. implementing the PSCI specification for CPU-centric power
  1138. management operations described in ARM document number ARM DEN
  1139. 0022A ("Power State Coordination Interface System Software on
  1140. ARM processors").
  1141. # The GPIO number here must be sorted by descending number. In case of
  1142. # a multiplatform kernel, we just want the highest value required by the
  1143. # selected platforms.
  1144. config ARCH_NR_GPIO
  1145. int
  1146. default 2048 if ARCH_SOCFPGA
  1147. default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
  1148. ARCH_ZYNQ || ARCH_ASPEED
  1149. default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
  1150. SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
  1151. default 416 if ARCH_SUNXI
  1152. default 392 if ARCH_U8500
  1153. default 352 if ARCH_VT8500
  1154. default 288 if ARCH_ROCKCHIP
  1155. default 264 if MACH_H4700
  1156. default 0
  1157. help
  1158. Maximum number of GPIOs in the system.
  1159. If unsure, leave the default value.
  1160. config HZ_FIXED
  1161. int
  1162. default 200 if ARCH_EBSA110
  1163. default 128 if SOC_AT91RM9200
  1164. default 0
  1165. choice
  1166. depends on HZ_FIXED = 0
  1167. prompt "Timer frequency"
  1168. config HZ_100
  1169. bool "100 Hz"
  1170. config HZ_200
  1171. bool "200 Hz"
  1172. config HZ_250
  1173. bool "250 Hz"
  1174. config HZ_300
  1175. bool "300 Hz"
  1176. config HZ_500
  1177. bool "500 Hz"
  1178. config HZ_1000
  1179. bool "1000 Hz"
  1180. endchoice
  1181. config HZ
  1182. int
  1183. default HZ_FIXED if HZ_FIXED != 0
  1184. default 100 if HZ_100
  1185. default 200 if HZ_200
  1186. default 250 if HZ_250
  1187. default 300 if HZ_300
  1188. default 500 if HZ_500
  1189. default 1000
  1190. config SCHED_HRTICK
  1191. def_bool HIGH_RES_TIMERS
  1192. config THUMB2_KERNEL
  1193. bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
  1194. depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
  1195. default y if CPU_THUMBONLY
  1196. select ARM_UNWIND
  1197. help
  1198. By enabling this option, the kernel will be compiled in
  1199. Thumb-2 mode.
  1200. If unsure, say N.
  1201. config ARM_PATCH_IDIV
  1202. bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
  1203. depends on CPU_32v7 && !XIP_KERNEL
  1204. default y
  1205. help
  1206. The ARM compiler inserts calls to __aeabi_idiv() and
  1207. __aeabi_uidiv() when it needs to perform division on signed
  1208. and unsigned integers. Some v7 CPUs have support for the sdiv
  1209. and udiv instructions that can be used to implement those
  1210. functions.
  1211. Enabling this option allows the kernel to modify itself to
  1212. replace the first two instructions of these library functions
  1213. with the sdiv or udiv plus "bx lr" instructions when the CPU
  1214. it is running on supports them. Typically this will be faster
  1215. and less power intensive than running the original library
  1216. code to do integer division.
  1217. config AEABI
  1218. bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
  1219. !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
  1220. default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
  1221. help
  1222. This option allows for the kernel to be compiled using the latest
  1223. ARM ABI (aka EABI). This is only useful if you are using a user
  1224. space environment that is also compiled with EABI.
  1225. Since there are major incompatibilities between the legacy ABI and
  1226. EABI, especially with regard to structure member alignment, this
  1227. option also changes the kernel syscall calling convention to
  1228. disambiguate both ABIs and allow for backward compatibility support
  1229. (selected with CONFIG_OABI_COMPAT).
  1230. To use this you need GCC version 4.0.0 or later.
  1231. config OABI_COMPAT
  1232. bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
  1233. depends on AEABI && !THUMB2_KERNEL
  1234. help
  1235. This option preserves the old syscall interface along with the
  1236. new (ARM EABI) one. It also provides a compatibility layer to
  1237. intercept syscalls that have structure arguments which layout
  1238. in memory differs between the legacy ABI and the new ARM EABI
  1239. (only for non "thumb" binaries). This option adds a tiny
  1240. overhead to all syscalls and produces a slightly larger kernel.
  1241. The seccomp filter system will not be available when this is
  1242. selected, since there is no way yet to sensibly distinguish
  1243. between calling conventions during filtering.
  1244. If you know you'll be using only pure EABI user space then you
  1245. can say N here. If this option is not selected and you attempt
  1246. to execute a legacy ABI binary then the result will be
  1247. UNPREDICTABLE (in fact it can be predicted that it won't work
  1248. at all). If in doubt say N.
  1249. config ARCH_HAS_HOLES_MEMORYMODEL
  1250. bool
  1251. config ARCH_SELECT_MEMORY_MODEL
  1252. bool
  1253. config ARCH_FLATMEM_ENABLE
  1254. bool
  1255. config ARCH_SPARSEMEM_ENABLE
  1256. bool
  1257. select SPARSEMEM_STATIC if SPARSEMEM
  1258. config HAVE_ARCH_PFN_VALID
  1259. def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
  1260. config HIGHMEM
  1261. bool "High Memory Support"
  1262. depends on MMU
  1263. help
  1264. The address space of ARM processors is only 4 Gigabytes large
  1265. and it has to accommodate user address space, kernel address
  1266. space as well as some memory mapped IO. That means that, if you
  1267. have a large amount of physical memory and/or IO, not all of the
  1268. memory can be "permanently mapped" by the kernel. The physical
  1269. memory that is not permanently mapped is called "high memory".
  1270. Depending on the selected kernel/user memory split, minimum
  1271. vmalloc space and actual amount of RAM, you may not need this
  1272. option which should result in a slightly faster kernel.
  1273. If unsure, say n.
  1274. config HIGHPTE
  1275. bool "Allocate 2nd-level pagetables from highmem" if EXPERT
  1276. depends on HIGHMEM
  1277. default y
  1278. help
  1279. The VM uses one page of physical memory for each page table.
  1280. For systems with a lot of processes, this can use a lot of
  1281. precious low memory, eventually leading to low memory being
  1282. consumed by page tables. Setting this option will allow
  1283. user-space 2nd level page tables to reside in high memory.
  1284. config CPU_SW_DOMAIN_PAN
  1285. bool "Enable use of CPU domains to implement privileged no-access"
  1286. depends on MMU && !ARM_LPAE
  1287. default y
  1288. help
  1289. Increase kernel security by ensuring that normal kernel accesses
  1290. are unable to access userspace addresses. This can help prevent
  1291. use-after-free bugs becoming an exploitable privilege escalation
  1292. by ensuring that magic values (such as LIST_POISON) will always
  1293. fault when dereferenced.
  1294. CPUs with low-vector mappings use a best-efforts implementation.
  1295. Their lower 1MB needs to remain accessible for the vectors, but
  1296. the remainder of userspace will become appropriately inaccessible.
  1297. config HW_PERF_EVENTS
  1298. def_bool y
  1299. depends on ARM_PMU
  1300. config SYS_SUPPORTS_HUGETLBFS
  1301. def_bool y
  1302. depends on ARM_LPAE
  1303. config HAVE_ARCH_TRANSPARENT_HUGEPAGE
  1304. def_bool y
  1305. depends on ARM_LPAE
  1306. config ARCH_WANT_GENERAL_HUGETLB
  1307. def_bool y
  1308. config ARM_MODULE_PLTS
  1309. bool "Use PLTs to allow module memory to spill over into vmalloc area"
  1310. depends on MODULES
  1311. default y
  1312. help
  1313. Allocate PLTs when loading modules so that jumps and calls whose
  1314. targets are too far away for their relative offsets to be encoded
  1315. in the instructions themselves can be bounced via veneers in the
  1316. module's PLT. This allows modules to be allocated in the generic
  1317. vmalloc area after the dedicated module memory area has been
  1318. exhausted. The modules will use slightly more memory, but after
  1319. rounding up to page size, the actual memory footprint is usually
  1320. the same.
  1321. Disabling this is usually safe for small single-platform
  1322. configurations. If unsure, say y.
  1323. config FORCE_MAX_ZONEORDER
  1324. int "Maximum zone order"
  1325. default "12" if SOC_AM33XX
  1326. default "9" if SA1111 || ARCH_EFM32
  1327. default "11"
  1328. help
  1329. The kernel memory allocator divides physically contiguous memory
  1330. blocks into "zones", where each zone is a power of two number of
  1331. pages. This option selects the largest power of two that the kernel
  1332. keeps in the memory allocator. If you need to allocate very large
  1333. blocks of physically contiguous memory, then you may need to
  1334. increase this value.
  1335. This config option is actually maximum order plus one. For example,
  1336. a value of 11 means that the largest free memory block is 2^10 pages.
  1337. config ALIGNMENT_TRAP
  1338. bool
  1339. depends on CPU_CP15_MMU
  1340. default y if !ARCH_EBSA110
  1341. select HAVE_PROC_CPU if PROC_FS
  1342. help
  1343. ARM processors cannot fetch/store information which is not
  1344. naturally aligned on the bus, i.e., a 4 byte fetch must start at an
  1345. address divisible by 4. On 32-bit ARM processors, these non-aligned
  1346. fetch/store instructions will be emulated in software if you say
  1347. here, which has a severe performance impact. This is necessary for
  1348. correct operation of some network protocols. With an IP-only
  1349. configuration it is safe to say N, otherwise say Y.
  1350. config UACCESS_WITH_MEMCPY
  1351. bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
  1352. depends on MMU
  1353. default y if CPU_FEROCEON
  1354. help
  1355. Implement faster copy_to_user and clear_user methods for CPU
  1356. cores where a 8-word STM instruction give significantly higher
  1357. memory write throughput than a sequence of individual 32bit stores.
  1358. A possible side effect is a slight increase in scheduling latency
  1359. between threads sharing the same address space if they invoke
  1360. such copy operations with large buffers.
  1361. However, if the CPU data cache is using a write-allocate mode,
  1362. this option is unlikely to provide any performance gain.
  1363. config PARAVIRT
  1364. bool "Enable paravirtualization code"
  1365. help
  1366. This changes the kernel so it can modify itself when it is run
  1367. under a hypervisor, potentially improving performance significantly
  1368. over full virtualization.
  1369. config PARAVIRT_TIME_ACCOUNTING
  1370. bool "Paravirtual steal time accounting"
  1371. select PARAVIRT
  1372. help
  1373. Select this option to enable fine granularity task steal time
  1374. accounting. Time spent executing other tasks in parallel with
  1375. the current vCPU is discounted from the vCPU power. To account for
  1376. that, there can be a small performance impact.
  1377. If in doubt, say N here.
  1378. config XEN_DOM0
  1379. def_bool y
  1380. depends on XEN
  1381. config XEN
  1382. bool "Xen guest support on ARM"
  1383. depends on ARM && AEABI && OF
  1384. depends on CPU_V7 && !CPU_V6
  1385. depends on !GENERIC_ATOMIC64
  1386. depends on MMU
  1387. select ARCH_DMA_ADDR_T_64BIT
  1388. select ARM_PSCI
  1389. select SWIOTLB
  1390. select SWIOTLB_XEN
  1391. select PARAVIRT
  1392. help
  1393. Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
  1394. config STACKPROTECTOR_PER_TASK
  1395. bool "Use a unique stack canary value for each task"
  1396. depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
  1397. select GCC_PLUGIN_ARM_SSP_PER_TASK
  1398. default y
  1399. help
  1400. Due to the fact that GCC uses an ordinary symbol reference from
  1401. which to load the value of the stack canary, this value can only
  1402. change at reboot time on SMP systems, and all tasks running in the
  1403. kernel's address space are forced to use the same canary value for
  1404. the entire duration that the system is up.
  1405. Enable this option to switch to a different method that uses a
  1406. different canary value for each task.
  1407. endmenu
  1408. menu "Boot options"
  1409. config USE_OF
  1410. bool "Flattened Device Tree support"
  1411. select IRQ_DOMAIN
  1412. select OF
  1413. help
  1414. Include support for flattened device tree machine descriptions.
  1415. config ATAGS
  1416. bool "Support for the traditional ATAGS boot data passing" if USE_OF
  1417. default y
  1418. help
  1419. This is the traditional way of passing data to the kernel at boot
  1420. time. If you are solely relying on the flattened device tree (or
  1421. the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
  1422. to remove ATAGS support from your kernel binary. If unsure,
  1423. leave this to y.
  1424. config DEPRECATED_PARAM_STRUCT
  1425. bool "Provide old way to pass kernel parameters"
  1426. depends on ATAGS
  1427. help
  1428. This was deprecated in 2001 and announced to live on for 5 years.
  1429. Some old boot loaders still use this way.
  1430. # Compressed boot loader in ROM. Yes, we really want to ask about
  1431. # TEXT and BSS so we preserve their values in the config files.
  1432. config ZBOOT_ROM_TEXT
  1433. hex "Compressed ROM boot loader base address"
  1434. default 0x0
  1435. help
  1436. The physical address at which the ROM-able zImage is to be
  1437. placed in the target. Platforms which normally make use of
  1438. ROM-able zImage formats normally set this to a suitable
  1439. value in their defconfig file.
  1440. If ZBOOT_ROM is not enabled, this has no effect.
  1441. config ZBOOT_ROM_BSS
  1442. hex "Compressed ROM boot loader BSS address"
  1443. default 0x0
  1444. help
  1445. The base address of an area of read/write memory in the target
  1446. for the ROM-able zImage which must be available while the
  1447. decompressor is running. It must be large enough to hold the
  1448. entire decompressed kernel plus an additional 128 KiB.
  1449. Platforms which normally make use of ROM-able zImage formats
  1450. normally set this to a suitable value in their defconfig file.
  1451. If ZBOOT_ROM is not enabled, this has no effect.
  1452. config ZBOOT_ROM
  1453. bool "Compressed boot loader in ROM/flash"
  1454. depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
  1455. depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
  1456. help
  1457. Say Y here if you intend to execute your compressed kernel image
  1458. (zImage) directly from ROM or flash. If unsure, say N.
  1459. config ARM_APPENDED_DTB
  1460. bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
  1461. depends on OF
  1462. help
  1463. With this option, the boot code will look for a device tree binary
  1464. (DTB) appended to zImage
  1465. (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
  1466. This is meant as a backward compatibility convenience for those
  1467. systems with a bootloader that can't be upgraded to accommodate
  1468. the documented boot protocol using a device tree.
  1469. Beware that there is very little in terms of protection against
  1470. this option being confused by leftover garbage in memory that might
  1471. look like a DTB header after a reboot if no actual DTB is appended
  1472. to zImage. Do not leave this option active in a production kernel
  1473. if you don't intend to always append a DTB. Proper passing of the
  1474. location into r2 of a bootloader provided DTB is always preferable
  1475. to this option.
  1476. config ARM_ATAG_DTB_COMPAT
  1477. bool "Supplement the appended DTB with traditional ATAG information"
  1478. depends on ARM_APPENDED_DTB
  1479. help
  1480. Some old bootloaders can't be updated to a DTB capable one, yet
  1481. they provide ATAGs with memory configuration, the ramdisk address,
  1482. the kernel cmdline string, etc. Such information is dynamically
  1483. provided by the bootloader and can't always be stored in a static
  1484. DTB. To allow a device tree enabled kernel to be used with such
  1485. bootloaders, this option allows zImage to extract the information
  1486. from the ATAG list and store it at run time into the appended DTB.
  1487. choice
  1488. prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
  1489. default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
  1490. config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
  1491. bool "Use bootloader kernel arguments if available"
  1492. help
  1493. Uses the command-line options passed by the boot loader instead of
  1494. the device tree bootargs property. If the boot loader doesn't provide
  1495. any, the device tree bootargs property will be used.
  1496. config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
  1497. bool "Extend with bootloader kernel arguments"
  1498. help
  1499. The command-line arguments provided by the boot loader will be
  1500. appended to the the device tree bootargs property.
  1501. endchoice
  1502. config CMDLINE
  1503. string "Default kernel command string"
  1504. default ""
  1505. help
  1506. On some architectures (EBSA110 and CATS), there is currently no way
  1507. for the boot loader to pass arguments to the kernel. For these
  1508. architectures, you should supply some command-line options at build
  1509. time by entering them here. As a minimum, you should specify the
  1510. memory size and the root device (e.g., mem=64M root=/dev/nfs).
  1511. choice
  1512. prompt "Kernel command line type" if CMDLINE != ""
  1513. default CMDLINE_FROM_BOOTLOADER
  1514. depends on ATAGS
  1515. config CMDLINE_FROM_BOOTLOADER
  1516. bool "Use bootloader kernel arguments if available"
  1517. help
  1518. Uses the command-line options passed by the boot loader. If
  1519. the boot loader doesn't provide any, the default kernel command
  1520. string provided in CMDLINE will be used.
  1521. config CMDLINE_EXTEND
  1522. bool "Extend bootloader kernel arguments"
  1523. help
  1524. The command-line arguments provided by the boot loader will be
  1525. appended to the default kernel command string.
  1526. config CMDLINE_FORCE
  1527. bool "Always use the default kernel command string"
  1528. help
  1529. Always use the default kernel command string, even if the boot
  1530. loader passes other arguments to the kernel.
  1531. This is useful if you cannot or don't want to change the
  1532. command-line options your boot loader passes to the kernel.
  1533. endchoice
  1534. config XIP_KERNEL
  1535. bool "Kernel Execute-In-Place from ROM"
  1536. depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
  1537. help
  1538. Execute-In-Place allows the kernel to run from non-volatile storage
  1539. directly addressable by the CPU, such as NOR flash. This saves RAM
  1540. space since the text section of the kernel is not loaded from flash
  1541. to RAM. Read-write sections, such as the data section and stack,
  1542. are still copied to RAM. The XIP kernel is not compressed since
  1543. it has to run directly from flash, so it will take more space to
  1544. store it. The flash address used to link the kernel object files,
  1545. and for storing it, is configuration dependent. Therefore, if you
  1546. say Y here, you must know the proper physical address where to
  1547. store the kernel image depending on your own flash memory usage.
  1548. Also note that the make target becomes "make xipImage" rather than
  1549. "make zImage" or "make Image". The final kernel binary to put in
  1550. ROM memory will be arch/arm/boot/xipImage.
  1551. If unsure, say N.
  1552. config XIP_PHYS_ADDR
  1553. hex "XIP Kernel Physical Location"
  1554. depends on XIP_KERNEL
  1555. default "0x00080000"
  1556. help
  1557. This is the physical address in your flash memory the kernel will
  1558. be linked for and stored to. This address is dependent on your
  1559. own flash usage.
  1560. config XIP_DEFLATED_DATA
  1561. bool "Store kernel .data section compressed in ROM"
  1562. depends on XIP_KERNEL
  1563. select ZLIB_INFLATE
  1564. help
  1565. Before the kernel is actually executed, its .data section has to be
  1566. copied to RAM from ROM. This option allows for storing that data
  1567. in compressed form and decompressed to RAM rather than merely being
  1568. copied, saving some precious ROM space. A possible drawback is a
  1569. slightly longer boot delay.
  1570. config KEXEC
  1571. bool "Kexec system call (EXPERIMENTAL)"
  1572. depends on (!SMP || PM_SLEEP_SMP)
  1573. depends on MMU
  1574. select KEXEC_CORE
  1575. help
  1576. kexec is a system call that implements the ability to shutdown your
  1577. current kernel, and to start another kernel. It is like a reboot
  1578. but it is independent of the system firmware. And like a reboot
  1579. you can start any kernel with it, not just Linux.
  1580. It is an ongoing process to be certain the hardware in a machine
  1581. is properly shutdown, so do not be surprised if this code does not
  1582. initially work for you.
  1583. config ATAGS_PROC
  1584. bool "Export atags in procfs"
  1585. depends on ATAGS && KEXEC
  1586. default y
  1587. help
  1588. Should the atags used to boot the kernel be exported in an "atags"
  1589. file in procfs. Useful with kexec.
  1590. config CRASH_DUMP
  1591. bool "Build kdump crash kernel (EXPERIMENTAL)"
  1592. help
  1593. Generate crash dump after being started by kexec. This should
  1594. be normally only set in special crash dump kernels which are
  1595. loaded in the main kernel with kexec-tools into a specially
  1596. reserved region and then later executed after a crash by
  1597. kdump/kexec. The crash dump kernel must be compiled to a
  1598. memory address not used by the main kernel
  1599. For more details see Documentation/admin-guide/kdump/kdump.rst
  1600. config AUTO_ZRELADDR
  1601. bool "Auto calculation of the decompressed kernel image address"
  1602. help
  1603. ZRELADDR is the physical address where the decompressed kernel
  1604. image will be placed. If AUTO_ZRELADDR is selected, the address
  1605. will be determined at run-time by masking the current IP with
  1606. 0xf8000000. This assumes the zImage being placed in the first 128MB
  1607. from start of memory.
  1608. config EFI_STUB
  1609. bool
  1610. config EFI
  1611. bool "UEFI runtime support"
  1612. depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
  1613. select UCS2_STRING
  1614. select EFI_PARAMS_FROM_FDT
  1615. select EFI_STUB
  1616. select EFI_GENERIC_STUB
  1617. select EFI_RUNTIME_WRAPPERS
  1618. help
  1619. This option provides support for runtime services provided
  1620. by UEFI firmware (such as non-volatile variables, realtime
  1621. clock, and platform reset). A UEFI stub is also provided to
  1622. allow the kernel to be booted as an EFI application. This
  1623. is only useful for kernels that may run on systems that have
  1624. UEFI firmware.
  1625. config DMI
  1626. bool "Enable support for SMBIOS (DMI) tables"
  1627. depends on EFI
  1628. default y
  1629. help
  1630. This enables SMBIOS/DMI feature for systems.
  1631. This option is only useful on systems that have UEFI firmware.
  1632. However, even with this option, the resultant kernel should
  1633. continue to boot on existing non-UEFI platforms.
  1634. NOTE: This does *NOT* enable or encourage the use of DMI quirks,
  1635. i.e., the the practice of identifying the platform via DMI to
  1636. decide whether certain workarounds for buggy hardware and/or
  1637. firmware need to be enabled. This would require the DMI subsystem
  1638. to be enabled much earlier than we do on ARM, which is non-trivial.
  1639. endmenu
  1640. menu "CPU Power Management"
  1641. source "drivers/cpufreq/Kconfig"
  1642. source "drivers/cpuidle/Kconfig"
  1643. endmenu
  1644. menu "Floating point emulation"
  1645. comment "At least one emulation must be selected"
  1646. config FPE_NWFPE
  1647. bool "NWFPE math emulation"
  1648. depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
  1649. help
  1650. Say Y to include the NWFPE floating point emulator in the kernel.
  1651. This is necessary to run most binaries. Linux does not currently
  1652. support floating point hardware so you need to say Y here even if
  1653. your machine has an FPA or floating point co-processor podule.
  1654. You may say N here if you are going to load the Acorn FPEmulator
  1655. early in the bootup.
  1656. config FPE_NWFPE_XP
  1657. bool "Support extended precision"
  1658. depends on FPE_NWFPE
  1659. help
  1660. Say Y to include 80-bit support in the kernel floating-point
  1661. emulator. Otherwise, only 32 and 64-bit support is compiled in.
  1662. Note that gcc does not generate 80-bit operations by default,
  1663. so in most cases this option only enlarges the size of the
  1664. floating point emulator without any good reason.
  1665. You almost surely want to say N here.
  1666. config FPE_FASTFPE
  1667. bool "FastFPE math emulation (EXPERIMENTAL)"
  1668. depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
  1669. help
  1670. Say Y here to include the FAST floating point emulator in the kernel.
  1671. This is an experimental much faster emulator which now also has full
  1672. precision for the mantissa. It does not support any exceptions.
  1673. It is very simple, and approximately 3-6 times faster than NWFPE.
  1674. It should be sufficient for most programs. It may be not suitable
  1675. for scientific calculations, but you have to check this for yourself.
  1676. If you do not feel you need a faster FP emulation you should better
  1677. choose NWFPE.
  1678. config VFP
  1679. bool "VFP-format floating point maths"
  1680. depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
  1681. help
  1682. Say Y to include VFP support code in the kernel. This is needed
  1683. if your hardware includes a VFP unit.
  1684. Please see <file:Documentation/arm/vfp/release-notes.rst> for
  1685. release notes and additional status information.
  1686. Say N if your target does not have VFP hardware.
  1687. config VFPv3
  1688. bool
  1689. depends on VFP
  1690. default y if CPU_V7
  1691. config NEON
  1692. bool "Advanced SIMD (NEON) Extension support"
  1693. depends on VFPv3 && CPU_V7
  1694. help
  1695. Say Y to include support code for NEON, the ARMv7 Advanced SIMD
  1696. Extension.
  1697. config KERNEL_MODE_NEON
  1698. bool "Support for NEON in kernel mode"
  1699. depends on NEON && AEABI
  1700. help
  1701. Say Y to include support for NEON in kernel mode.
  1702. endmenu
  1703. menu "Power management options"
  1704. source "kernel/power/Kconfig"
  1705. config ARCH_SUSPEND_POSSIBLE
  1706. depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
  1707. CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
  1708. def_bool y
  1709. config ARM_CPU_SUSPEND
  1710. def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
  1711. depends on ARCH_SUSPEND_POSSIBLE
  1712. config ARCH_HIBERNATION_POSSIBLE
  1713. bool
  1714. depends on MMU
  1715. default y if ARCH_SUSPEND_POSSIBLE
  1716. endmenu
  1717. source "drivers/firmware/Kconfig"
  1718. if CRYPTO
  1719. source "arch/arm/crypto/Kconfig"
  1720. endif
  1721. source "arch/arm/Kconfig.assembler"