mcip.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ARC ARConnect (MultiCore IP) support (formerly known as MCIP)
  4. *
  5. * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
  6. */
  7. #include <linux/smp.h>
  8. #include <linux/irq.h>
  9. #include <linux/irqchip/chained_irq.h>
  10. #include <linux/spinlock.h>
  11. #include <soc/arc/mcip.h>
  12. #include <asm/irqflags-arcv2.h>
  13. #include <asm/setup.h>
  14. static DEFINE_RAW_SPINLOCK(mcip_lock);
  15. #ifdef CONFIG_SMP
  16. static char smp_cpuinfo_buf[128];
  17. /*
  18. * Set mask to halt GFRC if any online core in SMP cluster is halted.
  19. * Only works for ARC HS v3.0+, on earlier versions has no effect.
  20. */
  21. static void mcip_update_gfrc_halt_mask(int cpu)
  22. {
  23. struct bcr_generic gfrc;
  24. unsigned long flags;
  25. u32 gfrc_halt_mask;
  26. READ_BCR(ARC_REG_GFRC_BUILD, gfrc);
  27. /*
  28. * CMD_GFRC_SET_CORE and CMD_GFRC_READ_CORE commands were added in
  29. * GFRC 0x3 version.
  30. */
  31. if (gfrc.ver < 0x3)
  32. return;
  33. raw_spin_lock_irqsave(&mcip_lock, flags);
  34. __mcip_cmd(CMD_GFRC_READ_CORE, 0);
  35. gfrc_halt_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
  36. gfrc_halt_mask |= BIT(cpu);
  37. __mcip_cmd_data(CMD_GFRC_SET_CORE, 0, gfrc_halt_mask);
  38. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  39. }
  40. static void mcip_update_debug_halt_mask(int cpu)
  41. {
  42. u32 mcip_mask = 0;
  43. unsigned long flags;
  44. raw_spin_lock_irqsave(&mcip_lock, flags);
  45. /*
  46. * mcip_mask is same for CMD_DEBUG_SET_SELECT and CMD_DEBUG_SET_MASK
  47. * commands. So read it once instead of reading both CMD_DEBUG_READ_MASK
  48. * and CMD_DEBUG_READ_SELECT.
  49. */
  50. __mcip_cmd(CMD_DEBUG_READ_SELECT, 0);
  51. mcip_mask = read_aux_reg(ARC_REG_MCIP_READBACK);
  52. mcip_mask |= BIT(cpu);
  53. __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, mcip_mask);
  54. /*
  55. * Parameter specified halt cause:
  56. * STATUS32[H]/actionpoint/breakpoint/self-halt
  57. * We choose all of them (0xF).
  58. */
  59. __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xF, mcip_mask);
  60. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  61. }
  62. static void mcip_setup_per_cpu(int cpu)
  63. {
  64. struct mcip_bcr mp;
  65. READ_BCR(ARC_REG_MCIP_BCR, mp);
  66. smp_ipi_irq_setup(cpu, IPI_IRQ);
  67. smp_ipi_irq_setup(cpu, SOFTIRQ_IRQ);
  68. /* Update GFRC halt mask as new CPU came online */
  69. if (mp.gfrc)
  70. mcip_update_gfrc_halt_mask(cpu);
  71. /* Update MCIP debug mask as new CPU came online */
  72. if (mp.dbg)
  73. mcip_update_debug_halt_mask(cpu);
  74. }
  75. static void mcip_ipi_send(int cpu)
  76. {
  77. unsigned long flags;
  78. int ipi_was_pending;
  79. /* ARConnect can only send IPI to others */
  80. if (unlikely(cpu == raw_smp_processor_id())) {
  81. arc_softirq_trigger(SOFTIRQ_IRQ);
  82. return;
  83. }
  84. raw_spin_lock_irqsave(&mcip_lock, flags);
  85. /*
  86. * If receiver already has a pending interrupt, elide sending this one.
  87. * Linux cross core calling works well with concurrent IPIs
  88. * coalesced into one
  89. * see arch/arc/kernel/smp.c: ipi_send_msg_one()
  90. */
  91. __mcip_cmd(CMD_INTRPT_READ_STATUS, cpu);
  92. ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK);
  93. if (!ipi_was_pending)
  94. __mcip_cmd(CMD_INTRPT_GENERATE_IRQ, cpu);
  95. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  96. }
  97. static void mcip_ipi_clear(int irq)
  98. {
  99. unsigned int cpu, c;
  100. unsigned long flags;
  101. if (unlikely(irq == SOFTIRQ_IRQ)) {
  102. arc_softirq_clear(irq);
  103. return;
  104. }
  105. raw_spin_lock_irqsave(&mcip_lock, flags);
  106. /* Who sent the IPI */
  107. __mcip_cmd(CMD_INTRPT_CHECK_SOURCE, 0);
  108. cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */
  109. /*
  110. * In rare case, multiple concurrent IPIs sent to same target can
  111. * possibly be coalesced by MCIP into 1 asserted IRQ, so @cpus can be
  112. * "vectored" (multiple bits sets) as opposed to typical single bit
  113. */
  114. do {
  115. c = __ffs(cpu); /* 0,1,2,3 */
  116. __mcip_cmd(CMD_INTRPT_GENERATE_ACK, c);
  117. cpu &= ~(1U << c);
  118. } while (cpu);
  119. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  120. }
  121. static void mcip_probe_n_setup(void)
  122. {
  123. struct mcip_bcr mp;
  124. READ_BCR(ARC_REG_MCIP_BCR, mp);
  125. sprintf(smp_cpuinfo_buf,
  126. "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n",
  127. mp.ver, mp.num_cores,
  128. IS_AVAIL1(mp.ipi, "IPI "),
  129. IS_AVAIL1(mp.idu, "IDU "),
  130. IS_AVAIL1(mp.dbg, "DEBUG "),
  131. IS_AVAIL1(mp.gfrc, "GFRC"));
  132. cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
  133. }
  134. struct plat_smp_ops plat_smp_ops = {
  135. .info = smp_cpuinfo_buf,
  136. .init_early_smp = mcip_probe_n_setup,
  137. .init_per_cpu = mcip_setup_per_cpu,
  138. .ipi_send = mcip_ipi_send,
  139. .ipi_clear = mcip_ipi_clear,
  140. };
  141. #endif
  142. /***************************************************************************
  143. * ARCv2 Interrupt Distribution Unit (IDU)
  144. *
  145. * Connects external "COMMON" IRQs to core intc, providing:
  146. * -dynamic routing (IRQ affinity)
  147. * -load balancing (Round Robin interrupt distribution)
  148. * -1:N distribution
  149. *
  150. * It physically resides in the MCIP hw block
  151. */
  152. #include <linux/irqchip.h>
  153. #include <linux/of.h>
  154. #include <linux/of_irq.h>
  155. /*
  156. * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core)
  157. */
  158. static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
  159. {
  160. __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
  161. }
  162. static void idu_set_mode(unsigned int cmn_irq, bool set_lvl, unsigned int lvl,
  163. bool set_distr, unsigned int distr)
  164. {
  165. union {
  166. unsigned int word;
  167. struct {
  168. unsigned int distr:2, pad:2, lvl:1, pad2:27;
  169. };
  170. } data;
  171. data.word = __mcip_cmd_read(CMD_IDU_READ_MODE, cmn_irq);
  172. if (set_distr)
  173. data.distr = distr;
  174. if (set_lvl)
  175. data.lvl = lvl;
  176. __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
  177. }
  178. static void idu_irq_mask_raw(irq_hw_number_t hwirq)
  179. {
  180. unsigned long flags;
  181. raw_spin_lock_irqsave(&mcip_lock, flags);
  182. __mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1);
  183. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  184. }
  185. static void idu_irq_mask(struct irq_data *data)
  186. {
  187. idu_irq_mask_raw(data->hwirq);
  188. }
  189. static void idu_irq_unmask(struct irq_data *data)
  190. {
  191. unsigned long flags;
  192. raw_spin_lock_irqsave(&mcip_lock, flags);
  193. __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0);
  194. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  195. }
  196. static void idu_irq_ack(struct irq_data *data)
  197. {
  198. unsigned long flags;
  199. raw_spin_lock_irqsave(&mcip_lock, flags);
  200. __mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
  201. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  202. }
  203. static void idu_irq_mask_ack(struct irq_data *data)
  204. {
  205. unsigned long flags;
  206. raw_spin_lock_irqsave(&mcip_lock, flags);
  207. __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
  208. __mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
  209. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  210. }
  211. static int
  212. idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
  213. bool force)
  214. {
  215. unsigned long flags;
  216. cpumask_t online;
  217. unsigned int destination_bits;
  218. unsigned int distribution_mode;
  219. /* errout if no online cpu per @cpumask */
  220. if (!cpumask_and(&online, cpumask, cpu_online_mask))
  221. return -EINVAL;
  222. raw_spin_lock_irqsave(&mcip_lock, flags);
  223. destination_bits = cpumask_bits(&online)[0];
  224. idu_set_dest(data->hwirq, destination_bits);
  225. if (ffs(destination_bits) == fls(destination_bits))
  226. distribution_mode = IDU_M_DISTRI_DEST;
  227. else
  228. distribution_mode = IDU_M_DISTRI_RR;
  229. idu_set_mode(data->hwirq, false, 0, true, distribution_mode);
  230. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  231. return IRQ_SET_MASK_OK;
  232. }
  233. static int idu_irq_set_type(struct irq_data *data, u32 type)
  234. {
  235. unsigned long flags;
  236. /*
  237. * ARCv2 IDU HW does not support inverse polarity, so these are the
  238. * only interrupt types supported.
  239. */
  240. if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
  241. return -EINVAL;
  242. raw_spin_lock_irqsave(&mcip_lock, flags);
  243. idu_set_mode(data->hwirq, true,
  244. type & IRQ_TYPE_EDGE_RISING ? IDU_M_TRIG_EDGE :
  245. IDU_M_TRIG_LEVEL,
  246. false, 0);
  247. raw_spin_unlock_irqrestore(&mcip_lock, flags);
  248. return 0;
  249. }
  250. static void idu_irq_enable(struct irq_data *data)
  251. {
  252. /*
  253. * By default send all common interrupts to all available online CPUs.
  254. * The affinity of common interrupts in IDU must be set manually since
  255. * in some cases the kernel will not call irq_set_affinity() by itself:
  256. * 1. When the kernel is not configured with support of SMP.
  257. * 2. When the kernel is configured with support of SMP but upper
  258. * interrupt controllers does not support setting of the affinity
  259. * and cannot propagate it to IDU.
  260. */
  261. idu_irq_set_affinity(data, cpu_online_mask, false);
  262. idu_irq_unmask(data);
  263. }
  264. static struct irq_chip idu_irq_chip = {
  265. .name = "MCIP IDU Intc",
  266. .irq_mask = idu_irq_mask,
  267. .irq_unmask = idu_irq_unmask,
  268. .irq_ack = idu_irq_ack,
  269. .irq_mask_ack = idu_irq_mask_ack,
  270. .irq_enable = idu_irq_enable,
  271. .irq_set_type = idu_irq_set_type,
  272. #ifdef CONFIG_SMP
  273. .irq_set_affinity = idu_irq_set_affinity,
  274. #endif
  275. };
  276. static void idu_cascade_isr(struct irq_desc *desc)
  277. {
  278. struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
  279. struct irq_chip *core_chip = irq_desc_get_chip(desc);
  280. irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
  281. irq_hw_number_t idu_hwirq = core_hwirq - FIRST_EXT_IRQ;
  282. chained_irq_enter(core_chip, desc);
  283. generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
  284. chained_irq_exit(core_chip, desc);
  285. }
  286. static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
  287. {
  288. irq_set_chip_and_handler(virq, &idu_irq_chip, handle_level_irq);
  289. irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
  290. return 0;
  291. }
  292. static const struct irq_domain_ops idu_irq_ops = {
  293. .xlate = irq_domain_xlate_onetwocell,
  294. .map = idu_irq_map,
  295. };
  296. /*
  297. * [16, 23]: Statically assigned always private-per-core (Timers, WDT, IPI)
  298. * [24, 23+C]: If C > 0 then "C" common IRQs
  299. * [24+C, N]: Not statically assigned, private-per-core
  300. */
  301. static int __init
  302. idu_of_init(struct device_node *intc, struct device_node *parent)
  303. {
  304. struct irq_domain *domain;
  305. int nr_irqs;
  306. int i, virq;
  307. struct mcip_bcr mp;
  308. struct mcip_idu_bcr idu_bcr;
  309. READ_BCR(ARC_REG_MCIP_BCR, mp);
  310. if (!mp.idu)
  311. panic("IDU not detected, but DeviceTree using it");
  312. READ_BCR(ARC_REG_MCIP_IDU_BCR, idu_bcr);
  313. nr_irqs = mcip_idu_bcr_to_nr_irqs(idu_bcr);
  314. pr_info("MCIP: IDU supports %u common irqs\n", nr_irqs);
  315. domain = irq_domain_add_linear(intc, nr_irqs, &idu_irq_ops, NULL);
  316. /* Parent interrupts (core-intc) are already mapped */
  317. for (i = 0; i < nr_irqs; i++) {
  318. /* Mask all common interrupts by default */
  319. idu_irq_mask_raw(i);
  320. /*
  321. * Return parent uplink IRQs (towards core intc) 24,25,.....
  322. * this step has been done before already
  323. * however we need it to get the parent virq and set IDU handler
  324. * as first level isr
  325. */
  326. virq = irq_create_mapping(NULL, i + FIRST_EXT_IRQ);
  327. BUG_ON(!virq);
  328. irq_set_chained_handler_and_data(virq, idu_cascade_isr, domain);
  329. }
  330. __mcip_cmd(CMD_IDU_ENABLE, 0);
  331. return 0;
  332. }
  333. IRQCHIP_DECLARE(arcv2_idu_intc, "snps,archs-idu-intc", idu_of_init);