head.S 4.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ARC CPU startup Code
  4. *
  5. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  6. *
  7. * Vineetg: Dec 2007
  8. * -Check if we are running on Simulator or on real hardware
  9. * to skip certain things during boot on simulator
  10. */
  11. #include <linux/linkage.h>
  12. #include <asm/asm-offsets.h>
  13. #include <asm/entry.h>
  14. #include <asm/arcregs.h>
  15. #include <asm/cache.h>
  16. #include <asm/dsp-impl.h>
  17. #include <asm/irqflags.h>
  18. .macro CPU_EARLY_SETUP
  19. ; Setting up Vectror Table (in case exception happens in early boot
  20. sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
  21. ; Disable I-cache/D-cache if kernel so configured
  22. lr r5, [ARC_REG_IC_BCR]
  23. breq r5, 0, 1f ; I$ doesn't exist
  24. lr r5, [ARC_REG_IC_CTRL]
  25. #ifdef CONFIG_ARC_HAS_ICACHE
  26. bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
  27. #else
  28. bset r5, r5, 0 ; I$ exists, but is not used
  29. #endif
  30. sr r5, [ARC_REG_IC_CTRL]
  31. 1:
  32. lr r5, [ARC_REG_DC_BCR]
  33. breq r5, 0, 1f ; D$ doesn't exist
  34. lr r5, [ARC_REG_DC_CTRL]
  35. bclr r5, r5, 6 ; Invalidate (discard w/o wback)
  36. #ifdef CONFIG_ARC_HAS_DCACHE
  37. bclr r5, r5, 0 ; Enable (+Inv)
  38. #else
  39. bset r5, r5, 0 ; Disable (+Inv)
  40. #endif
  41. sr r5, [ARC_REG_DC_CTRL]
  42. 1:
  43. #ifdef CONFIG_ISA_ARCV2
  44. ; Unaligned access is disabled at reset, so re-enable early as
  45. ; gcc 7.3.1 (ARC GNU 2018.03) onwards generates unaligned access
  46. ; by default
  47. lr r5, [status32]
  48. #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
  49. bset r5, r5, STATUS_AD_BIT
  50. #else
  51. ; Although disabled at reset, bootloader might have enabled it
  52. bclr r5, r5, STATUS_AD_BIT
  53. #endif
  54. kflag r5
  55. #ifdef CONFIG_ARC_LPB_DISABLE
  56. lr r5, [ARC_REG_LPB_BUILD]
  57. breq r5, 0, 1f ; LPB doesn't exist
  58. mov r5, 1
  59. sr r5, [ARC_REG_LPB_CTRL]
  60. 1:
  61. #endif /* CONFIG_ARC_LPB_DISABLE */
  62. /* On HSDK, CCMs need to remapped super early */
  63. #ifdef CONFIG_ARC_SOC_HSDK
  64. mov r6, 0x60000000
  65. lr r5, [ARC_REG_ICCM_BUILD]
  66. breq r5, 0, 1f
  67. sr r6, [ARC_REG_AUX_ICCM]
  68. 1:
  69. lr r5, [ARC_REG_DCCM_BUILD]
  70. breq r5, 0, 2f
  71. sr r6, [ARC_REG_AUX_DCCM]
  72. 2:
  73. #endif /* CONFIG_ARC_SOC_HSDK */
  74. #endif /* CONFIG_ISA_ARCV2 */
  75. ; Config DSP_CTRL properly, so kernel may use integer multiply,
  76. ; multiply-accumulate, and divide operations
  77. DSP_EARLY_INIT
  78. .endm
  79. .section .init.text, "ax",@progbits
  80. ;----------------------------------------------------------------
  81. ; Default Reset Handler (jumped into from Reset vector)
  82. ; - Don't clobber r0,r1,r2 as they might have u-boot provided args
  83. ; - Platforms can override this weak version if needed
  84. ;----------------------------------------------------------------
  85. WEAK(res_service)
  86. j stext
  87. END(res_service)
  88. ;----------------------------------------------------------------
  89. ; Kernel Entry point
  90. ;----------------------------------------------------------------
  91. ENTRY(stext)
  92. CPU_EARLY_SETUP
  93. #ifdef CONFIG_SMP
  94. GET_CPU_ID r5
  95. cmp r5, 0
  96. mov.nz r0, r5
  97. bz .Lmaster_proceed
  98. ; Non-Masters wait for Master to boot enough and bring them up
  99. ; when they resume, tail-call to entry point
  100. mov blink, @first_lines_of_secondary
  101. j arc_platform_smp_wait_to_boot
  102. .Lmaster_proceed:
  103. #endif
  104. ; Clear BSS before updating any globals
  105. ; XXX: use ZOL here
  106. mov r5, __bss_start
  107. sub r6, __bss_stop, r5
  108. lsr.f lp_count, r6, 2
  109. lpnz 1f
  110. st.ab 0, [r5, 4]
  111. 1:
  112. ; Uboot - kernel ABI
  113. ; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2
  114. ; r1 = magic number (always zero as of now)
  115. ; r2 = pointer to uboot provided cmdline or external DTB in mem
  116. ; These are handled later in handle_uboot_args()
  117. st r0, [@uboot_tag]
  118. st r1, [@uboot_magic]
  119. st r2, [@uboot_arg]
  120. ; setup "current" tsk and optionally cache it in dedicated r25
  121. mov r9, @init_task
  122. SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch
  123. ; setup stack (fp, sp)
  124. mov fp, 0
  125. ; tsk->thread_info is really a PAGE, whose bottom hoists stack
  126. GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output)
  127. j start_kernel ; "C" entry point
  128. END(stext)
  129. #ifdef CONFIG_SMP
  130. ;----------------------------------------------------------------
  131. ; First lines of code run by secondary before jumping to 'C'
  132. ;----------------------------------------------------------------
  133. .section .text, "ax",@progbits
  134. ENTRY(first_lines_of_secondary)
  135. ; setup per-cpu idle task as "current" on this CPU
  136. ld r0, [@secondary_idle_tsk]
  137. SET_CURR_TASK_ON_CPU r0, r1
  138. ; setup stack (fp, sp)
  139. mov fp, 0
  140. ; set it's stack base to tsk->thread_info bottom
  141. GET_TSK_STACK_BASE r0, sp
  142. j start_kernel_secondary
  143. END(first_lines_of_secondary)
  144. #endif