entry-arcv2.S 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
  4. *
  5. * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
  6. */
  7. #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
  8. #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
  9. #include <asm/errno.h>
  10. #include <asm/arcregs.h>
  11. #include <asm/irqflags.h>
  12. ; A maximum number of supported interrupts in the core interrupt controller.
  13. ; This number is not equal to the maximum interrupt number (256) because
  14. ; first 16 lines are reserved for exceptions and are not configurable.
  15. #define NR_CPU_IRQS 240
  16. .cpu HS
  17. #define VECTOR .word
  18. ;############################ Vector Table #################################
  19. .section .vector,"a",@progbits
  20. .align 4
  21. # Initial 16 slots are Exception Vectors
  22. VECTOR res_service ; Reset Vector
  23. VECTOR mem_service ; Mem exception
  24. VECTOR instr_service ; Instrn Error
  25. VECTOR EV_MachineCheck ; Fatal Machine check
  26. VECTOR EV_TLBMissI ; Intruction TLB miss
  27. VECTOR EV_TLBMissD ; Data TLB miss
  28. VECTOR EV_TLBProtV ; Protection Violation
  29. VECTOR EV_PrivilegeV ; Privilege Violation
  30. VECTOR EV_SWI ; Software Breakpoint
  31. VECTOR EV_Trap ; Trap exception
  32. VECTOR EV_Extension ; Extn Instruction Exception
  33. VECTOR EV_DivZero ; Divide by Zero
  34. VECTOR EV_DCError ; Data Cache Error
  35. VECTOR EV_Misaligned ; Misaligned Data Access
  36. VECTOR reserved ; Reserved slots
  37. VECTOR reserved ; Reserved slots
  38. # Begin Interrupt Vectors
  39. VECTOR handle_interrupt ; (16) Timer0
  40. VECTOR handle_interrupt ; unused (Timer1)
  41. VECTOR handle_interrupt ; unused (WDT)
  42. VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
  43. VECTOR handle_interrupt ; (20) perf Interrupt
  44. VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
  45. VECTOR handle_interrupt ; unused
  46. VECTOR handle_interrupt ; (23) unused
  47. # End of fixed IRQs
  48. .rept NR_CPU_IRQS - 8
  49. VECTOR handle_interrupt
  50. .endr
  51. .section .text, "ax",@progbits
  52. reserved:
  53. flag 1 ; Unexpected event, halt
  54. ;##################### Interrupt Handling ##############################
  55. ENTRY(handle_interrupt)
  56. INTERRUPT_PROLOGUE
  57. # irq control APIs local_irq_save/restore/disable/enable fiddle with
  58. # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
  59. # However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
  60. # query in hard ISR path would return false (since .IE is set) which would
  61. # trips genirq interrupt handling asserts.
  62. #
  63. # So do a "soft" disable of interrutps here.
  64. #
  65. # Note this disable is only for consistent book-keeping as further interrupts
  66. # will be disabled anyways even w/o this. Hardware tracks active interrupts
  67. # seperately in AUX_IRQ_ACT.active and will not take new interrupts
  68. # unless this one returns (or higher prio becomes pending in 2-prio scheme)
  69. IRQ_DISABLE
  70. ; icause is banked: one per priority level
  71. ; so a higher prio interrupt taken here won't clobber prev prio icause
  72. lr r0, [ICAUSE]
  73. mov blink, ret_from_exception
  74. b.d arch_do_IRQ
  75. mov r1, sp
  76. END(handle_interrupt)
  77. ;################### Non TLB Exception Handling #############################
  78. ENTRY(EV_SWI)
  79. ; TODO: implement this
  80. EXCEPTION_PROLOGUE
  81. b ret_from_exception
  82. END(EV_SWI)
  83. ENTRY(EV_DivZero)
  84. ; TODO: implement this
  85. EXCEPTION_PROLOGUE
  86. b ret_from_exception
  87. END(EV_DivZero)
  88. ENTRY(EV_DCError)
  89. ; TODO: implement this
  90. EXCEPTION_PROLOGUE
  91. b ret_from_exception
  92. END(EV_DCError)
  93. ; ---------------------------------------------
  94. ; Memory Error Exception Handler
  95. ; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
  96. ; Instruction fetch or Data access, under a single Exception Vector
  97. ; ---------------------------------------------
  98. ENTRY(mem_service)
  99. EXCEPTION_PROLOGUE
  100. lr r0, [efa]
  101. mov r1, sp
  102. FAKE_RET_FROM_EXCPN
  103. bl do_memory_error
  104. b ret_from_exception
  105. END(mem_service)
  106. ENTRY(EV_Misaligned)
  107. EXCEPTION_PROLOGUE
  108. lr r0, [efa] ; Faulting Data address
  109. mov r1, sp
  110. FAKE_RET_FROM_EXCPN
  111. SAVE_CALLEE_SAVED_USER
  112. mov r2, sp ; callee_regs
  113. bl do_misaligned_access
  114. ; TBD: optimize - do this only if a callee reg was involved
  115. ; either a dst of emulated LD/ST or src with address-writeback
  116. RESTORE_CALLEE_SAVED_USER
  117. b ret_from_exception
  118. END(EV_Misaligned)
  119. ; ---------------------------------------------
  120. ; Protection Violation Exception Handler
  121. ; ---------------------------------------------
  122. ENTRY(EV_TLBProtV)
  123. EXCEPTION_PROLOGUE
  124. lr r0, [efa] ; Faulting Data address
  125. mov r1, sp ; pt_regs
  126. FAKE_RET_FROM_EXCPN
  127. mov blink, ret_from_exception
  128. b do_page_fault
  129. END(EV_TLBProtV)
  130. ; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
  131. ; need to call do_page_fault().
  132. ; ECR in pt_regs provides whether access was R/W/X
  133. .global call_do_page_fault
  134. .set call_do_page_fault, EV_TLBProtV
  135. ;############# Common Handlers for ARCompact and ARCv2 ##############
  136. #include "entry.S"
  137. ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
  138. ;
  139. ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
  140. ; IRQ shd definitely not happen between now and rtie
  141. ; All 2 entry points to here already disable interrupts
  142. .Lrestore_regs:
  143. restore_regs:
  144. # Interrpts are actually disabled from this point on, but will get
  145. # reenabled after we return from interrupt/exception.
  146. # But irq tracer needs to be told now...
  147. TRACE_ASM_IRQ_ENABLE
  148. ld r0, [sp, PT_status32] ; U/K mode at time of entry
  149. lr r10, [AUX_IRQ_ACT]
  150. bmsk r11, r10, 15 ; extract AUX_IRQ_ACT.active
  151. breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception
  152. ;####### Return from Intr #######
  153. .Lisr_ret:
  154. debug_marker_l1:
  155. ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
  156. btst r0, STATUS_DE_BIT ; Z flag set if bit clear
  157. bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set
  158. ; Handle special case #1: (Entry via Exception, Return via IRQ)
  159. ;
  160. ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
  161. ; task now returning to U mode (riding the Intr)
  162. ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
  163. ; won't be switched to correct U mode value (from AUX_SP)
  164. ; So force AUX_IRQ_ACT.U for such a case
  165. btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
  166. bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U
  167. sr r11, [AUX_IRQ_ACT]
  168. INTERRUPT_EPILOGUE
  169. rtie
  170. ;####### Return from Exception / pure kernel mode #######
  171. .Lexcept_ret: ; Expects r0 has PT_status32
  172. debug_marker_syscall:
  173. EXCEPTION_EPILOGUE
  174. rtie
  175. ;####### Return from Intr to insn in delay slot #######
  176. ; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
  177. ;
  178. ; Intr returning to a Delay Slot (DS) insn
  179. ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
  180. ; entry was via Exception in DS which got preempted in kernel).
  181. ;
  182. ; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
  183. ;
  184. ; Solution is to drop out of interrupt context into pure kernel mode
  185. ; and return from pure kernel mode which does right things for delay slot
  186. .Lintr_ret_to_delay_slot:
  187. debug_marker_ds:
  188. ld r2, [@intr_to_DE_cnt]
  189. add r2, r2, 1
  190. st r2, [@intr_to_DE_cnt]
  191. ; drop out of interrupt context (clear AUX_IRQ_ACT.active)
  192. bmskn r11, r10, 15
  193. sr r11, [AUX_IRQ_ACT]
  194. b .Lexcept_ret
  195. END(ret_from_exception)