mmu.rst 8.6 KB

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  1. =============================
  2. MMUv3 initialization sequence
  3. =============================
  4. The code in the initialize_mmu macro sets up MMUv3 memory mapping
  5. identically to MMUv2 fixed memory mapping. Depending on
  6. CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
  7. located in addresses it was linked for (symbol undefined), or not
  8. (symbol defined), so it needs to be position-independent.
  9. The code has the following assumptions:
  10. - This code fragment is run only on an MMU v3.
  11. - TLBs are in their reset state.
  12. - ITLBCFG and DTLBCFG are zero (reset state).
  13. - RASID is 0x04030201 (reset state).
  14. - PS.RING is zero (reset state).
  15. - LITBASE is zero (reset state, PC-relative literals); required to be PIC.
  16. TLB setup proceeds along the following steps.
  17. Legend:
  18. - VA = virtual address (two upper nibbles of it);
  19. - PA = physical address (two upper nibbles of it);
  20. - pc = physical range that contains this code;
  21. After step 2, we jump to virtual address in the range 0x40000000..0x5fffffff
  22. or 0x00000000..0x1fffffff, depending on whether the kernel was loaded below
  23. 0x40000000 or above. That address corresponds to next instruction to execute
  24. in this code. After step 4, we jump to intended (linked) address of this code.
  25. The scheme below assumes that the kernel is loaded below 0x40000000.
  26. ====== ===== ===== ===== ===== ====== ===== =====
  27. - Step0 Step1 Step2 Step3 Step4 Step5
  28. VA PA PA PA PA VA PA PA
  29. ====== ===== ===== ===== ===== ====== ===== =====
  30. E0..FF -> E0 -> E0 -> E0 F0..FF -> F0 -> F0
  31. C0..DF -> C0 -> C0 -> C0 E0..EF -> F0 -> F0
  32. A0..BF -> A0 -> A0 -> A0 D8..DF -> 00 -> 00
  33. 80..9F -> 80 -> 80 -> 80 D0..D7 -> 00 -> 00
  34. 60..7F -> 60 -> 60 -> 60
  35. 40..5F -> 40 -> pc -> pc 40..5F -> pc
  36. 20..3F -> 20 -> 20 -> 20
  37. 00..1F -> 00 -> 00 -> 00
  38. ====== ===== ===== ===== ===== ====== ===== =====
  39. The default location of IO peripherals is above 0xf0000000. This may be changed
  40. using a "ranges" property in a device tree simple-bus node. See the Devicetree
  41. Specification, section 4.5 for details on the syntax and semantics of
  42. simple-bus nodes. The following limitations apply:
  43. 1. Only top level simple-bus nodes are considered
  44. 2. Only one (first) simple-bus node is considered
  45. 3. Empty "ranges" properties are not supported
  46. 4. Only the first triplet in the "ranges" property is considered
  47. 5. The parent-bus-address value is rounded down to the nearest 256MB boundary
  48. 6. The IO area covers the entire 256MB segment of parent-bus-address; the
  49. "ranges" triplet length field is ignored
  50. MMUv3 address space layouts.
  51. ============================
  52. Default MMUv2-compatible layout::
  53. Symbol VADDR Size
  54. +------------------+
  55. | Userspace | 0x00000000 TASK_SIZE
  56. +------------------+ 0x40000000
  57. +------------------+
  58. | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
  59. +------------------+
  60. | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
  61. +------------------+ 0x8e400000
  62. +------------------+
  63. | VMALLOC area | VMALLOC_START 0xc0000000 128MB - 64KB
  64. +------------------+ VMALLOC_END
  65. +------------------+
  66. | Cache aliasing | TLBTEMP_BASE_1 0xc8000000 DCACHE_WAY_SIZE
  67. | remap area 1 |
  68. +------------------+
  69. | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
  70. | remap area 2 |
  71. +------------------+
  72. +------------------+
  73. | KMAP area | PKMAP_BASE PTRS_PER_PTE *
  74. | | DCACHE_N_COLORS *
  75. | | PAGE_SIZE
  76. | | (4MB * DCACHE_N_COLORS)
  77. +------------------+
  78. | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
  79. | | NR_CPUS *
  80. | | DCACHE_N_COLORS *
  81. | | PAGE_SIZE
  82. +------------------+ FIXADDR_TOP 0xcffff000
  83. +------------------+
  84. | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xd0000000 128MB
  85. +------------------+
  86. | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xd8000000 128MB
  87. +------------------+
  88. | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
  89. +------------------+
  90. | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
  91. +------------------+
  92. 256MB cached + 256MB uncached layout::
  93. Symbol VADDR Size
  94. +------------------+
  95. | Userspace | 0x00000000 TASK_SIZE
  96. +------------------+ 0x40000000
  97. +------------------+
  98. | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
  99. +------------------+
  100. | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
  101. +------------------+ 0x8e400000
  102. +------------------+
  103. | VMALLOC area | VMALLOC_START 0xa0000000 128MB - 64KB
  104. +------------------+ VMALLOC_END
  105. +------------------+
  106. | Cache aliasing | TLBTEMP_BASE_1 0xa8000000 DCACHE_WAY_SIZE
  107. | remap area 1 |
  108. +------------------+
  109. | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
  110. | remap area 2 |
  111. +------------------+
  112. +------------------+
  113. | KMAP area | PKMAP_BASE PTRS_PER_PTE *
  114. | | DCACHE_N_COLORS *
  115. | | PAGE_SIZE
  116. | | (4MB * DCACHE_N_COLORS)
  117. +------------------+
  118. | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
  119. | | NR_CPUS *
  120. | | DCACHE_N_COLORS *
  121. | | PAGE_SIZE
  122. +------------------+ FIXADDR_TOP 0xaffff000
  123. +------------------+
  124. | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xb0000000 256MB
  125. +------------------+
  126. | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 256MB
  127. +------------------+
  128. +------------------+
  129. | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
  130. +------------------+
  131. | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
  132. +------------------+
  133. 512MB cached + 512MB uncached layout::
  134. Symbol VADDR Size
  135. +------------------+
  136. | Userspace | 0x00000000 TASK_SIZE
  137. +------------------+ 0x40000000
  138. +------------------+
  139. | Page table | XCHAL_PAGE_TABLE_VADDR 0x80000000 XCHAL_PAGE_TABLE_SIZE
  140. +------------------+
  141. | KASAN shadow map | KASAN_SHADOW_START 0x80400000 KASAN_SHADOW_SIZE
  142. +------------------+ 0x8e400000
  143. +------------------+
  144. | VMALLOC area | VMALLOC_START 0x90000000 128MB - 64KB
  145. +------------------+ VMALLOC_END
  146. +------------------+
  147. | Cache aliasing | TLBTEMP_BASE_1 0x98000000 DCACHE_WAY_SIZE
  148. | remap area 1 |
  149. +------------------+
  150. | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
  151. | remap area 2 |
  152. +------------------+
  153. +------------------+
  154. | KMAP area | PKMAP_BASE PTRS_PER_PTE *
  155. | | DCACHE_N_COLORS *
  156. | | PAGE_SIZE
  157. | | (4MB * DCACHE_N_COLORS)
  158. +------------------+
  159. | Atomic KMAP area | FIXADDR_START KM_TYPE_NR *
  160. | | NR_CPUS *
  161. | | DCACHE_N_COLORS *
  162. | | PAGE_SIZE
  163. +------------------+ FIXADDR_TOP 0x9ffff000
  164. +------------------+
  165. | Cached KSEG | XCHAL_KSEG_CACHED_VADDR 0xa0000000 512MB
  166. +------------------+
  167. | Uncached KSEG | XCHAL_KSEG_BYPASS_VADDR 0xc0000000 512MB
  168. +------------------+
  169. | Cached KIO | XCHAL_KIO_CACHED_VADDR 0xe0000000 256MB
  170. +------------------+
  171. | Uncached KIO | XCHAL_KIO_BYPASS_VADDR 0xf0000000 256MB
  172. +------------------+