atomctl.rst 2.2 KB

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  1. ===========================================
  2. Atomic Operation Control (ATOMCTL) Register
  3. ===========================================
  4. We Have Atomic Operation Control (ATOMCTL) Register.
  5. This register determines the effect of using a S32C1I instruction
  6. with various combinations of:
  7. 1. With and without an Coherent Cache Controller which
  8. can do Atomic Transactions to the memory internally.
  9. 2. With and without An Intelligent Memory Controller which
  10. can do Atomic Transactions itself.
  11. The Core comes up with a default value of for the three types of cache ops::
  12. 0x28: (WB: Internal, WT: Internal, BY:Exception)
  13. On the FPGA Cards we typically simulate an Intelligent Memory controller
  14. which can implement RCW transactions. For FPGA cards with an External
  15. Memory controller we let it to the atomic operations internally while
  16. doing a Cached (WB) transaction and use the Memory RCW for un-cached
  17. operations.
  18. For systems without an coherent cache controller, non-MX, we always
  19. use the memory controllers RCW, thought non-MX controlers likely
  20. support the Internal Operation.
  21. CUSTOMER-WARNING:
  22. Virtually all customers buy their memory controllers from vendors that
  23. don't support atomic RCW memory transactions and will likely want to
  24. configure this register to not use RCW.
  25. Developers might find using RCW in Bypass mode convenient when testing
  26. with the cache being bypassed; for example studying cache alias problems.
  27. See Section 4.3.12.4 of ISA; Bits::
  28. WB WT BY
  29. 5 4 | 3 2 | 1 0
  30. ========= ================== ================== ===============
  31. 2 Bit
  32. Field
  33. Values WB - Write Back WT - Write Thru BY - Bypass
  34. ========= ================== ================== ===============
  35. 0 Exception Exception Exception
  36. 1 RCW Transaction RCW Transaction RCW Transaction
  37. 2 Internal Operation Internal Operation Reserved
  38. 3 Reserved Reserved Reserved
  39. ========= ================== ================== ===============