pti.rst 8.9 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. ==========================
  3. Page Table Isolation (PTI)
  4. ==========================
  5. Overview
  6. ========
  7. Page Table Isolation (pti, previously known as KAISER [1]_) is a
  8. countermeasure against attacks on the shared user/kernel address
  9. space such as the "Meltdown" approach [2]_.
  10. To mitigate this class of attacks, we create an independent set of
  11. page tables for use only when running userspace applications. When
  12. the kernel is entered via syscalls, interrupts or exceptions, the
  13. page tables are switched to the full "kernel" copy. When the system
  14. switches back to user mode, the user copy is used again.
  15. The userspace page tables contain only a minimal amount of kernel
  16. data: only what is needed to enter/exit the kernel such as the
  17. entry/exit functions themselves and the interrupt descriptor table
  18. (IDT). There are a few strictly unnecessary things that get mapped
  19. such as the first C function when entering an interrupt (see
  20. comments in pti.c).
  21. This approach helps to ensure that side-channel attacks leveraging
  22. the paging structures do not function when PTI is enabled. It can be
  23. enabled by setting CONFIG_PAGE_TABLE_ISOLATION=y at compile time.
  24. Once enabled at compile-time, it can be disabled at boot with the
  25. 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
  26. Page Table Management
  27. =====================
  28. When PTI is enabled, the kernel manages two sets of page tables.
  29. The first set is very similar to the single set which is present in
  30. kernels without PTI. This includes a complete mapping of userspace
  31. that the kernel can use for things like copy_to_user().
  32. Although _complete_, the user portion of the kernel page tables is
  33. crippled by setting the NX bit in the top level. This ensures
  34. that any missed kernel->user CR3 switch will immediately crash
  35. userspace upon executing its first instruction.
  36. The userspace page tables map only the kernel data needed to enter
  37. and exit the kernel. This data is entirely contained in the 'struct
  38. cpu_entry_area' structure which is placed in the fixmap which gives
  39. each CPU's copy of the area a compile-time-fixed virtual address.
  40. For new userspace mappings, the kernel makes the entries in its
  41. page tables like normal. The only difference is when the kernel
  42. makes entries in the top (PGD) level. In addition to setting the
  43. entry in the main kernel PGD, a copy of the entry is made in the
  44. userspace page tables' PGD.
  45. This sharing at the PGD level also inherently shares all the lower
  46. layers of the page tables. This leaves a single, shared set of
  47. userspace page tables to manage. One PTE to lock, one set of
  48. accessed bits, dirty bits, etc...
  49. Overhead
  50. ========
  51. Protection against side-channel attacks is important. But,
  52. this protection comes at a cost:
  53. 1. Increased Memory Use
  54. a. Each process now needs an order-1 PGD instead of order-0.
  55. (Consumes an additional 4k per process).
  56. b. The 'cpu_entry_area' structure must be 2MB in size and 2MB
  57. aligned so that it can be mapped by setting a single PMD
  58. entry. This consumes nearly 2MB of RAM once the kernel
  59. is decompressed, but no space in the kernel image itself.
  60. 2. Runtime Cost
  61. a. CR3 manipulation to switch between the page table copies
  62. must be done at interrupt, syscall, and exception entry
  63. and exit (it can be skipped when the kernel is interrupted,
  64. though.) Moves to CR3 are on the order of a hundred
  65. cycles, and are required at every entry and exit.
  66. b. A "trampoline" must be used for SYSCALL entry. This
  67. trampoline depends on a smaller set of resources than the
  68. non-PTI SYSCALL entry code, so requires mapping fewer
  69. things into the userspace page tables. The downside is
  70. that stacks must be switched at entry time.
  71. c. Global pages are disabled for all kernel structures not
  72. mapped into both kernel and userspace page tables. This
  73. feature of the MMU allows different processes to share TLB
  74. entries mapping the kernel. Losing the feature means more
  75. TLB misses after a context switch. The actual loss of
  76. performance is very small, however, never exceeding 1%.
  77. d. Process Context IDentifiers (PCID) is a CPU feature that
  78. allows us to skip flushing the entire TLB when switching page
  79. tables by setting a special bit in CR3 when the page tables
  80. are changed. This makes switching the page tables (at context
  81. switch, or kernel entry/exit) cheaper. But, on systems with
  82. PCID support, the context switch code must flush both the user
  83. and kernel entries out of the TLB. The user PCID TLB flush is
  84. deferred until the exit to userspace, minimizing the cost.
  85. See intel.com/sdm for the gory PCID/INVPCID details.
  86. e. The userspace page tables must be populated for each new
  87. process. Even without PTI, the shared kernel mappings
  88. are created by copying top-level (PGD) entries into each
  89. new process. But, with PTI, there are now *two* kernel
  90. mappings: one in the kernel page tables that maps everything
  91. and one for the entry/exit structures. At fork(), we need to
  92. copy both.
  93. f. In addition to the fork()-time copying, there must also
  94. be an update to the userspace PGD any time a set_pgd() is done
  95. on a PGD used to map userspace. This ensures that the kernel
  96. and userspace copies always map the same userspace
  97. memory.
  98. g. On systems without PCID support, each CR3 write flushes
  99. the entire TLB. That means that each syscall, interrupt
  100. or exception flushes the TLB.
  101. h. INVPCID is a TLB-flushing instruction which allows flushing
  102. of TLB entries for non-current PCIDs. Some systems support
  103. PCIDs, but do not support INVPCID. On these systems, addresses
  104. can only be flushed from the TLB for the current PCID. When
  105. flushing a kernel address, we need to flush all PCIDs, so a
  106. single kernel address flush will require a TLB-flushing CR3
  107. write upon the next use of every PCID.
  108. Possible Future Work
  109. ====================
  110. 1. We can be more careful about not actually writing to CR3
  111. unless its value is actually changed.
  112. 2. Allow PTI to be enabled/disabled at runtime in addition to the
  113. boot-time switching.
  114. Testing
  115. ========
  116. To test stability of PTI, the following test procedure is recommended,
  117. ideally doing all of these in parallel:
  118. 1. Set CONFIG_DEBUG_ENTRY=y
  119. 2. Run several copies of all of the tools/testing/selftests/x86/ tests
  120. (excluding MPX and protection_keys) in a loop on multiple CPUs for
  121. several minutes. These tests frequently uncover corner cases in the
  122. kernel entry code. In general, old kernels might cause these tests
  123. themselves to crash, but they should never crash the kernel.
  124. 3. Run the 'perf' tool in a mode (top or record) that generates many
  125. frequent performance monitoring non-maskable interrupts (see "NMI"
  126. in /proc/interrupts). This exercises the NMI entry/exit code which
  127. is known to trigger bugs in code paths that did not expect to be
  128. interrupted, including nested NMIs. Using "-c" boosts the rate of
  129. NMIs, and using two -c with separate counters encourages nested NMIs
  130. and less deterministic behavior.
  131. ::
  132. while true; do perf record -c 10000 -e instructions,cycles -a sleep 10; done
  133. 4. Launch a KVM virtual machine.
  134. 5. Run 32-bit binaries on systems supporting the SYSCALL instruction.
  135. This has been a lightly-tested code path and needs extra scrutiny.
  136. Debugging
  137. =========
  138. Bugs in PTI cause a few different signatures of crashes
  139. that are worth noting here.
  140. * Failures of the selftests/x86 code. Usually a bug in one of the
  141. more obscure corners of entry_64.S
  142. * Crashes in early boot, especially around CPU bringup. Bugs
  143. in the trampoline code or mappings cause these.
  144. * Crashes at the first interrupt. Caused by bugs in entry_64.S,
  145. like screwing up a page table switch. Also caused by
  146. incorrectly mapping the IRQ handler entry code.
  147. * Crashes at the first NMI. The NMI code is separate from main
  148. interrupt handlers and can have bugs that do not affect
  149. normal interrupts. Also caused by incorrectly mapping NMI
  150. code. NMIs that interrupt the entry code must be very
  151. careful and can be the cause of crashes that show up when
  152. running perf.
  153. * Kernel crashes at the first exit to userspace. entry_64.S
  154. bugs, or failing to map some of the exit code.
  155. * Crashes at first interrupt that interrupts userspace. The paths
  156. in entry_64.S that return to userspace are sometimes separate
  157. from the ones that return to the kernel.
  158. * Double faults: overflowing the kernel stack because of page
  159. faults upon page faults. Caused by touching non-pti-mapped
  160. data in the entry code, or forgetting to switch to kernel
  161. CR3 before calling into C functions which are not pti-mapped.
  162. * Userspace segfaults early in boot, sometimes manifesting
  163. as mount(8) failing to mount the rootfs. These have
  164. tended to be TLB invalidation issues. Usually invalidating
  165. the wrong PCID, or otherwise missing an invalidation.
  166. .. [1] https://gruss.cc/files/kaiser.pdf
  167. .. [2] https://meltdownattack.com/meltdown.pdf