intel_th.rst 6.0 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. =======================
  3. Intel(R) Trace Hub (TH)
  4. =======================
  5. Overview
  6. --------
  7. Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
  8. switch and output trace data from multiple hardware and software
  9. sources over several types of trace output ports encoded in System
  10. Trace Protocol (MIPI STPv2) and is intended to perform full system
  11. debugging. For more information on the hardware, see Intel(R) Trace
  12. Hub developer's manual [1].
  13. It consists of trace sources, trace destinations (outputs) and a
  14. switch (Global Trace Hub, GTH). These devices are placed on a bus of
  15. their own ("intel_th"), where they can be discovered and configured
  16. via sysfs attributes.
  17. Currently, the following Intel TH subdevices (blocks) are supported:
  18. - Software Trace Hub (STH), trace source, which is a System Trace
  19. Module (STM) device,
  20. - Memory Storage Unit (MSU), trace output, which allows storing
  21. trace hub output in system memory,
  22. - Parallel Trace Interface output (PTI), trace output to an external
  23. debug host via a PTI port,
  24. - Global Trace Hub (GTH), which is a switch and a central component
  25. of Intel(R) Trace Hub architecture.
  26. Common attributes for output devices are described in
  27. Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
  28. notable of them is "active", which enables or disables trace output
  29. into that particular output device.
  30. GTH allows directing different STP masters into different output ports
  31. via its "masters" attribute group. More detailed GTH interface
  32. description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
  33. STH registers an stm class device, through which it provides interface
  34. to userspace and kernelspace software trace sources. See
  35. Documentation/trace/stm.rst for more information on that.
  36. MSU can be configured to collect trace data into a system memory
  37. buffer, which can later on be read from its device nodes via read() or
  38. mmap() interface and directed to a "software sink" driver that will
  39. consume the data and/or relay it further.
  40. On the whole, Intel(R) Trace Hub does not require any special
  41. userspace software to function; everything can be configured, started
  42. and collected via sysfs attributes, and device nodes.
  43. [1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
  44. Bus and Subdevices
  45. ------------------
  46. For each Intel TH device in the system a bus of its own is
  47. created and assigned an id number that reflects the order in which TH
  48. devices were enumerated. All TH subdevices (devices on intel_th bus)
  49. begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
  50. followed by device's name and an optional index.
  51. Output devices also get a device node in /dev/intel_thN, where N is
  52. the Intel TH device id. For example, MSU's memory buffers, when
  53. allocated, are accessible via /dev/intel_th0/msc{0,1}.
  54. Quick example
  55. -------------
  56. # figure out which GTH port is the first memory controller::
  57. $ cat /sys/bus/intel_th/devices/0-msc0/port
  58. 0
  59. # looks like it's port 0, configure master 33 to send data to port 0::
  60. $ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
  61. # allocate a 2-windowed multiblock buffer on the first memory
  62. # controller, each with 64 pages::
  63. $ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
  64. $ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages
  65. # enable wrapping for this controller, too::
  66. $ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap
  67. # and enable tracing into this port::
  68. $ echo 1 > /sys/bus/intel_th/devices/0-msc0/active
  69. # .. send data to master 33, see stm.txt for more details ..
  70. # .. wait for traces to pile up ..
  71. # .. and stop the trace::
  72. $ echo 0 > /sys/bus/intel_th/devices/0-msc0/active
  73. # and now you can collect the trace from the device node::
  74. $ cat /dev/intel_th0/msc0 > my_stp_trace
  75. Host Debugger Mode
  76. ------------------
  77. It is possible to configure the Trace Hub and control its trace
  78. capture from a remote debug host, which should be connected via one of
  79. the hardware debugging interfaces, which will then be used to both
  80. control Intel Trace Hub and transfer its trace data to the debug host.
  81. The driver needs to be told that such an arrangement is taking place
  82. so that it does not touch any capture/port configuration and avoids
  83. conflicting with the debug host's configuration accesses. The only
  84. activity that the driver will perform in this mode is collecting
  85. software traces to the Software Trace Hub (an stm class device). The
  86. user is still responsible for setting up adequate master/channel
  87. mappings that the decoder on the receiving end would recognize.
  88. In order to enable the host mode, set the 'host_mode' parameter of the
  89. 'intel_th' kernel module to 'y'. None of the virtual output devices
  90. will show up on the intel_th bus. Also, trace configuration and
  91. capture controlling attribute groups of the 'gth' device will not be
  92. exposed. The 'sth' device will operate as usual.
  93. Software Sinks
  94. --------------
  95. The Memory Storage Unit (MSU) driver provides an in-kernel API for
  96. drivers to register themselves as software sinks for the trace data.
  97. Such drivers can further export the data via other devices, such as
  98. USB device controllers or network cards.
  99. The API has two main parts::
  100. - notifying the software sink that a particular window is full, and
  101. "locking" that window, that is, making it unavailable for the trace
  102. collection; when this happens, the MSU driver will automatically
  103. switch to the next window in the buffer if it is unlocked, or stop
  104. the trace capture if it's not;
  105. - tracking the "locked" state of windows and providing a way for the
  106. software sink driver to notify the MSU driver when a window is
  107. unlocked and can be used again to collect trace data.
  108. An example sink driver, msu-sink illustrates the implementation of a
  109. software sink. Functionally, it simply unlocks windows as soon as they
  110. are full, keeping the MSU running in a circular buffer mode. Unlike the
  111. "multi" mode, it will fill out all the windows in the buffer as opposed
  112. to just the first one. It can be enabled by writing "sink" to the "mode"
  113. file (assuming msu-sink.ko is loaded).