spi-summary.rst 26 KB

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  1. ====================================
  2. Overview of Linux kernel SPI support
  3. ====================================
  4. 02-Feb-2012
  5. What is SPI?
  6. ------------
  7. The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
  8. link used to connect microcontrollers to sensors, memory, and peripherals.
  9. It's a simple "de facto" standard, not complicated enough to acquire a
  10. standardization body. SPI uses a master/slave configuration.
  11. The three signal wires hold a clock (SCK, often on the order of 10 MHz),
  12. and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
  13. Slave Out" (MISO) signals. (Other names are also used.) There are four
  14. clocking modes through which data is exchanged; mode-0 and mode-3 are most
  15. commonly used. Each clock cycle shifts data out and data in; the clock
  16. doesn't cycle except when there is a data bit to shift. Not all data bits
  17. are used though; not every protocol uses those full duplex capabilities.
  18. SPI masters use a fourth "chip select" line to activate a given SPI slave
  19. device, so those three signal wires may be connected to several chips
  20. in parallel. All SPI slaves support chipselects; they are usually active
  21. low signals, labeled nCSx for slave 'x' (e.g. nCS0). Some devices have
  22. other signals, often including an interrupt to the master.
  23. Unlike serial busses like USB or SMBus, even low level protocols for
  24. SPI slave functions are usually not interoperable between vendors
  25. (except for commodities like SPI memory chips).
  26. - SPI may be used for request/response style device protocols, as with
  27. touchscreen sensors and memory chips.
  28. - It may also be used to stream data in either direction (half duplex),
  29. or both of them at the same time (full duplex).
  30. - Some devices may use eight bit words. Others may use different word
  31. lengths, such as streams of 12-bit or 20-bit digital samples.
  32. - Words are usually sent with their most significant bit (MSB) first,
  33. but sometimes the least significant bit (LSB) goes first instead.
  34. - Sometimes SPI is used to daisy-chain devices, like shift registers.
  35. In the same way, SPI slaves will only rarely support any kind of automatic
  36. discovery/enumeration protocol. The tree of slave devices accessible from
  37. a given SPI master will normally be set up manually, with configuration
  38. tables.
  39. SPI is only one of the names used by such four-wire protocols, and
  40. most controllers have no problem handling "MicroWire" (think of it as
  41. half-duplex SPI, for request/response protocols), SSP ("Synchronous
  42. Serial Protocol"), PSP ("Programmable Serial Protocol"), and other
  43. related protocols.
  44. Some chips eliminate a signal line by combining MOSI and MISO, and
  45. limiting themselves to half-duplex at the hardware level. In fact
  46. some SPI chips have this signal mode as a strapping option. These
  47. can be accessed using the same programming interface as SPI, but of
  48. course they won't handle full duplex transfers. You may find such
  49. chips described as using "three wire" signaling: SCK, data, nCSx.
  50. (That data line is sometimes called MOMI or SISO.)
  51. Microcontrollers often support both master and slave sides of the SPI
  52. protocol. This document (and Linux) supports both the master and slave
  53. sides of SPI interactions.
  54. Who uses it? On what kinds of systems?
  55. ---------------------------------------
  56. Linux developers using SPI are probably writing device drivers for embedded
  57. systems boards. SPI is used to control external chips, and it is also a
  58. protocol supported by every MMC or SD memory card. (The older "DataFlash"
  59. cards, predating MMC cards but using the same connectors and card shape,
  60. support only SPI.) Some PC hardware uses SPI flash for BIOS code.
  61. SPI slave chips range from digital/analog converters used for analog
  62. sensors and codecs, to memory, to peripherals like USB controllers
  63. or Ethernet adapters; and more.
  64. Most systems using SPI will integrate a few devices on a mainboard.
  65. Some provide SPI links on expansion connectors; in cases where no
  66. dedicated SPI controller exists, GPIO pins can be used to create a
  67. low speed "bitbanging" adapter. Very few systems will "hotplug" an SPI
  68. controller; the reasons to use SPI focus on low cost and simple operation,
  69. and if dynamic reconfiguration is important, USB will often be a more
  70. appropriate low-pincount peripheral bus.
  71. Many microcontrollers that can run Linux integrate one or more I/O
  72. interfaces with SPI modes. Given SPI support, they could use MMC or SD
  73. cards without needing a special purpose MMC/SD/SDIO controller.
  74. I'm confused. What are these four SPI "clock modes"?
  75. -----------------------------------------------------
  76. It's easy to be confused here, and the vendor documentation you'll
  77. find isn't necessarily helpful. The four modes combine two mode bits:
  78. - CPOL indicates the initial clock polarity. CPOL=0 means the
  79. clock starts low, so the first (leading) edge is rising, and
  80. the second (trailing) edge is falling. CPOL=1 means the clock
  81. starts high, so the first (leading) edge is falling.
  82. - CPHA indicates the clock phase used to sample data; CPHA=0 says
  83. sample on the leading edge, CPHA=1 means the trailing edge.
  84. Since the signal needs to stablize before it's sampled, CPHA=0
  85. implies that its data is written half a clock before the first
  86. clock edge. The chipselect may have made it become available.
  87. Chip specs won't always say "uses SPI mode X" in as many words,
  88. but their timing diagrams will make the CPOL and CPHA modes clear.
  89. In the SPI mode number, CPOL is the high order bit and CPHA is the
  90. low order bit. So when a chip's timing diagram shows the clock
  91. starting low (CPOL=0) and data stabilized for sampling during the
  92. trailing clock edge (CPHA=1), that's SPI mode 1.
  93. Note that the clock mode is relevant as soon as the chipselect goes
  94. active. So the master must set the clock to inactive before selecting
  95. a slave, and the slave can tell the chosen polarity by sampling the
  96. clock level when its select line goes active. That's why many devices
  97. support for example both modes 0 and 3: they don't care about polarity,
  98. and always clock data in/out on rising clock edges.
  99. How do these driver programming interfaces work?
  100. ------------------------------------------------
  101. The <linux/spi/spi.h> header file includes kerneldoc, as does the
  102. main source code, and you should certainly read that chapter of the
  103. kernel API document. This is just an overview, so you get the big
  104. picture before those details.
  105. SPI requests always go into I/O queues. Requests for a given SPI device
  106. are always executed in FIFO order, and complete asynchronously through
  107. completion callbacks. There are also some simple synchronous wrappers
  108. for those calls, including ones for common transaction types like writing
  109. a command and then reading its response.
  110. There are two types of SPI driver, here called:
  111. Controller drivers ...
  112. controllers may be built into System-On-Chip
  113. processors, and often support both Master and Slave roles.
  114. These drivers touch hardware registers and may use DMA.
  115. Or they can be PIO bitbangers, needing just GPIO pins.
  116. Protocol drivers ...
  117. these pass messages through the controller
  118. driver to communicate with a Slave or Master device on the
  119. other side of an SPI link.
  120. So for example one protocol driver might talk to the MTD layer to export
  121. data to filesystems stored on SPI flash like DataFlash; and others might
  122. control audio interfaces, present touchscreen sensors as input interfaces,
  123. or monitor temperature and voltage levels during industrial processing.
  124. And those might all be sharing the same controller driver.
  125. A "struct spi_device" encapsulates the controller-side interface between
  126. those two types of drivers.
  127. There is a minimal core of SPI programming interfaces, focussing on
  128. using the driver model to connect controller and protocol drivers using
  129. device tables provided by board specific initialization code. SPI
  130. shows up in sysfs in several locations::
  131. /sys/devices/.../CTLR ... physical node for a given SPI controller
  132. /sys/devices/.../CTLR/spiB.C ... spi_device on bus "B",
  133. chipselect C, accessed through CTLR.
  134. /sys/bus/spi/devices/spiB.C ... symlink to that physical
  135. .../CTLR/spiB.C device
  136. /sys/devices/.../CTLR/spiB.C/modalias ... identifies the driver
  137. that should be used with this device (for hotplug/coldplug)
  138. /sys/bus/spi/drivers/D ... driver for one or more spi*.* devices
  139. /sys/class/spi_master/spiB ... symlink (or actual device node) to
  140. a logical node which could hold class related state for the SPI
  141. master controller managing bus "B". All spiB.* devices share one
  142. physical SPI bus segment, with SCLK, MOSI, and MISO.
  143. /sys/devices/.../CTLR/slave ... virtual file for (un)registering the
  144. slave device for an SPI slave controller.
  145. Writing the driver name of an SPI slave handler to this file
  146. registers the slave device; writing "(null)" unregisters the slave
  147. device.
  148. Reading from this file shows the name of the slave device ("(null)"
  149. if not registered).
  150. /sys/class/spi_slave/spiB ... symlink (or actual device node) to
  151. a logical node which could hold class related state for the SPI
  152. slave controller on bus "B". When registered, a single spiB.*
  153. device is present here, possible sharing the physical SPI bus
  154. segment with other SPI slave devices.
  155. Note that the actual location of the controller's class state depends
  156. on whether you enabled CONFIG_SYSFS_DEPRECATED or not. At this time,
  157. the only class-specific state is the bus number ("B" in "spiB"), so
  158. those /sys/class entries are only useful to quickly identify busses.
  159. How does board-specific init code declare SPI devices?
  160. ------------------------------------------------------
  161. Linux needs several kinds of information to properly configure SPI devices.
  162. That information is normally provided by board-specific code, even for
  163. chips that do support some of automated discovery/enumeration.
  164. Declare Controllers
  165. ^^^^^^^^^^^^^^^^^^^
  166. The first kind of information is a list of what SPI controllers exist.
  167. For System-on-Chip (SOC) based boards, these will usually be platform
  168. devices, and the controller may need some platform_data in order to
  169. operate properly. The "struct platform_device" will include resources
  170. like the physical address of the controller's first register and its IRQ.
  171. Platforms will often abstract the "register SPI controller" operation,
  172. maybe coupling it with code to initialize pin configurations, so that
  173. the arch/.../mach-*/board-*.c files for several boards can all share the
  174. same basic controller setup code. This is because most SOCs have several
  175. SPI-capable controllers, and only the ones actually usable on a given
  176. board should normally be set up and registered.
  177. So for example arch/.../mach-*/board-*.c files might have code like::
  178. #include <mach/spi.h> /* for mysoc_spi_data */
  179. /* if your mach-* infrastructure doesn't support kernels that can
  180. * run on multiple boards, pdata wouldn't benefit from "__init".
  181. */
  182. static struct mysoc_spi_data pdata __initdata = { ... };
  183. static __init board_init(void)
  184. {
  185. ...
  186. /* this board only uses SPI controller #2 */
  187. mysoc_register_spi(2, &pdata);
  188. ...
  189. }
  190. And SOC-specific utility code might look something like::
  191. #include <mach/spi.h>
  192. static struct platform_device spi2 = { ... };
  193. void mysoc_register_spi(unsigned n, struct mysoc_spi_data *pdata)
  194. {
  195. struct mysoc_spi_data *pdata2;
  196. pdata2 = kmalloc(sizeof *pdata2, GFP_KERNEL);
  197. *pdata2 = pdata;
  198. ...
  199. if (n == 2) {
  200. spi2->dev.platform_data = pdata2;
  201. register_platform_device(&spi2);
  202. /* also: set up pin modes so the spi2 signals are
  203. * visible on the relevant pins ... bootloaders on
  204. * production boards may already have done this, but
  205. * developer boards will often need Linux to do it.
  206. */
  207. }
  208. ...
  209. }
  210. Notice how the platform_data for boards may be different, even if the
  211. same SOC controller is used. For example, on one board SPI might use
  212. an external clock, where another derives the SPI clock from current
  213. settings of some master clock.
  214. Declare Slave Devices
  215. ^^^^^^^^^^^^^^^^^^^^^
  216. The second kind of information is a list of what SPI slave devices exist
  217. on the target board, often with some board-specific data needed for the
  218. driver to work correctly.
  219. Normally your arch/.../mach-*/board-*.c files would provide a small table
  220. listing the SPI devices on each board. (This would typically be only a
  221. small handful.) That might look like::
  222. static struct ads7846_platform_data ads_info = {
  223. .vref_delay_usecs = 100,
  224. .x_plate_ohms = 580,
  225. .y_plate_ohms = 410,
  226. };
  227. static struct spi_board_info spi_board_info[] __initdata = {
  228. {
  229. .modalias = "ads7846",
  230. .platform_data = &ads_info,
  231. .mode = SPI_MODE_0,
  232. .irq = GPIO_IRQ(31),
  233. .max_speed_hz = 120000 /* max sample rate at 3V */ * 16,
  234. .bus_num = 1,
  235. .chip_select = 0,
  236. },
  237. };
  238. Again, notice how board-specific information is provided; each chip may need
  239. several types. This example shows generic constraints like the fastest SPI
  240. clock to allow (a function of board voltage in this case) or how an IRQ pin
  241. is wired, plus chip-specific constraints like an important delay that's
  242. changed by the capacitance at one pin.
  243. (There's also "controller_data", information that may be useful to the
  244. controller driver. An example would be peripheral-specific DMA tuning
  245. data or chipselect callbacks. This is stored in spi_device later.)
  246. The board_info should provide enough information to let the system work
  247. without the chip's driver being loaded. The most troublesome aspect of
  248. that is likely the SPI_CS_HIGH bit in the spi_device.mode field, since
  249. sharing a bus with a device that interprets chipselect "backwards" is
  250. not possible until the infrastructure knows how to deselect it.
  251. Then your board initialization code would register that table with the SPI
  252. infrastructure, so that it's available later when the SPI master controller
  253. driver is registered::
  254. spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
  255. Like with other static board-specific setup, you won't unregister those.
  256. The widely used "card" style computers bundle memory, cpu, and little else
  257. onto a card that's maybe just thirty square centimeters. On such systems,
  258. your ``arch/.../mach-.../board-*.c`` file would primarily provide information
  259. about the devices on the mainboard into which such a card is plugged. That
  260. certainly includes SPI devices hooked up through the card connectors!
  261. Non-static Configurations
  262. ^^^^^^^^^^^^^^^^^^^^^^^^^
  263. Developer boards often play by different rules than product boards, and one
  264. example is the potential need to hotplug SPI devices and/or controllers.
  265. For those cases you might need to use spi_busnum_to_master() to look
  266. up the spi bus master, and will likely need spi_new_device() to provide the
  267. board info based on the board that was hotplugged. Of course, you'd later
  268. call at least spi_unregister_device() when that board is removed.
  269. When Linux includes support for MMC/SD/SDIO/DataFlash cards through SPI, those
  270. configurations will also be dynamic. Fortunately, such devices all support
  271. basic device identification probes, so they should hotplug normally.
  272. How do I write an "SPI Protocol Driver"?
  273. ----------------------------------------
  274. Most SPI drivers are currently kernel drivers, but there's also support
  275. for userspace drivers. Here we talk only about kernel drivers.
  276. SPI protocol drivers somewhat resemble platform device drivers::
  277. static struct spi_driver CHIP_driver = {
  278. .driver = {
  279. .name = "CHIP",
  280. .owner = THIS_MODULE,
  281. .pm = &CHIP_pm_ops,
  282. },
  283. .probe = CHIP_probe,
  284. .remove = CHIP_remove,
  285. };
  286. The driver core will automatically attempt to bind this driver to any SPI
  287. device whose board_info gave a modalias of "CHIP". Your probe() code
  288. might look like this unless you're creating a device which is managing
  289. a bus (appearing under /sys/class/spi_master).
  290. ::
  291. static int CHIP_probe(struct spi_device *spi)
  292. {
  293. struct CHIP *chip;
  294. struct CHIP_platform_data *pdata;
  295. /* assuming the driver requires board-specific data: */
  296. pdata = &spi->dev.platform_data;
  297. if (!pdata)
  298. return -ENODEV;
  299. /* get memory for driver's per-chip state */
  300. chip = kzalloc(sizeof *chip, GFP_KERNEL);
  301. if (!chip)
  302. return -ENOMEM;
  303. spi_set_drvdata(spi, chip);
  304. ... etc
  305. return 0;
  306. }
  307. As soon as it enters probe(), the driver may issue I/O requests to
  308. the SPI device using "struct spi_message". When remove() returns,
  309. or after probe() fails, the driver guarantees that it won't submit
  310. any more such messages.
  311. - An spi_message is a sequence of protocol operations, executed
  312. as one atomic sequence. SPI driver controls include:
  313. + when bidirectional reads and writes start ... by how its
  314. sequence of spi_transfer requests is arranged;
  315. + which I/O buffers are used ... each spi_transfer wraps a
  316. buffer for each transfer direction, supporting full duplex
  317. (two pointers, maybe the same one in both cases) and half
  318. duplex (one pointer is NULL) transfers;
  319. + optionally defining short delays after transfers ... using
  320. the spi_transfer.delay_usecs setting (this delay can be the
  321. only protocol effect, if the buffer length is zero);
  322. + whether the chipselect becomes inactive after a transfer and
  323. any delay ... by using the spi_transfer.cs_change flag;
  324. + hinting whether the next message is likely to go to this same
  325. device ... using the spi_transfer.cs_change flag on the last
  326. transfer in that atomic group, and potentially saving costs
  327. for chip deselect and select operations.
  328. - Follow standard kernel rules, and provide DMA-safe buffers in
  329. your messages. That way controller drivers using DMA aren't forced
  330. to make extra copies unless the hardware requires it (e.g. working
  331. around hardware errata that force the use of bounce buffering).
  332. If standard dma_map_single() handling of these buffers is inappropriate,
  333. you can use spi_message.is_dma_mapped to tell the controller driver
  334. that you've already provided the relevant DMA addresses.
  335. - The basic I/O primitive is spi_async(). Async requests may be
  336. issued in any context (irq handler, task, etc) and completion
  337. is reported using a callback provided with the message.
  338. After any detected error, the chip is deselected and processing
  339. of that spi_message is aborted.
  340. - There are also synchronous wrappers like spi_sync(), and wrappers
  341. like spi_read(), spi_write(), and spi_write_then_read(). These
  342. may be issued only in contexts that may sleep, and they're all
  343. clean (and small, and "optional") layers over spi_async().
  344. - The spi_write_then_read() call, and convenience wrappers around
  345. it, should only be used with small amounts of data where the
  346. cost of an extra copy may be ignored. It's designed to support
  347. common RPC-style requests, such as writing an eight bit command
  348. and reading a sixteen bit response -- spi_w8r16() being one its
  349. wrappers, doing exactly that.
  350. Some drivers may need to modify spi_device characteristics like the
  351. transfer mode, wordsize, or clock rate. This is done with spi_setup(),
  352. which would normally be called from probe() before the first I/O is
  353. done to the device. However, that can also be called at any time
  354. that no message is pending for that device.
  355. While "spi_device" would be the bottom boundary of the driver, the
  356. upper boundaries might include sysfs (especially for sensor readings),
  357. the input layer, ALSA, networking, MTD, the character device framework,
  358. or other Linux subsystems.
  359. Note that there are two types of memory your driver must manage as part
  360. of interacting with SPI devices.
  361. - I/O buffers use the usual Linux rules, and must be DMA-safe.
  362. You'd normally allocate them from the heap or free page pool.
  363. Don't use the stack, or anything that's declared "static".
  364. - The spi_message and spi_transfer metadata used to glue those
  365. I/O buffers into a group of protocol transactions. These can
  366. be allocated anywhere it's convenient, including as part of
  367. other allocate-once driver data structures. Zero-init these.
  368. If you like, spi_message_alloc() and spi_message_free() convenience
  369. routines are available to allocate and zero-initialize an spi_message
  370. with several transfers.
  371. How do I write an "SPI Master Controller Driver"?
  372. -------------------------------------------------
  373. An SPI controller will probably be registered on the platform_bus; write
  374. a driver to bind to the device, whichever bus is involved.
  375. The main task of this type of driver is to provide an "spi_master".
  376. Use spi_alloc_master() to allocate the master, and spi_master_get_devdata()
  377. to get the driver-private data allocated for that device.
  378. ::
  379. struct spi_master *master;
  380. struct CONTROLLER *c;
  381. master = spi_alloc_master(dev, sizeof *c);
  382. if (!master)
  383. return -ENODEV;
  384. c = spi_master_get_devdata(master);
  385. The driver will initialize the fields of that spi_master, including the
  386. bus number (maybe the same as the platform device ID) and three methods
  387. used to interact with the SPI core and SPI protocol drivers. It will
  388. also initialize its own internal state. (See below about bus numbering
  389. and those methods.)
  390. After you initialize the spi_master, then use spi_register_master() to
  391. publish it to the rest of the system. At that time, device nodes for the
  392. controller and any predeclared spi devices will be made available, and
  393. the driver model core will take care of binding them to drivers.
  394. If you need to remove your SPI controller driver, spi_unregister_master()
  395. will reverse the effect of spi_register_master().
  396. Bus Numbering
  397. ^^^^^^^^^^^^^
  398. Bus numbering is important, since that's how Linux identifies a given
  399. SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
  400. SOC systems, the bus numbers should match the numbers defined by the chip
  401. manufacturer. For example, hardware controller SPI2 would be bus number 2,
  402. and spi_board_info for devices connected to it would use that number.
  403. If you don't have such hardware-assigned bus number, and for some reason
  404. you can't just assign them, then provide a negative bus number. That will
  405. then be replaced by a dynamically assigned number. You'd then need to treat
  406. this as a non-static configuration (see above).
  407. SPI Master Methods
  408. ^^^^^^^^^^^^^^^^^^
  409. ``master->setup(struct spi_device *spi)``
  410. This sets up the device clock rate, SPI mode, and word sizes.
  411. Drivers may change the defaults provided by board_info, and then
  412. call spi_setup(spi) to invoke this routine. It may sleep.
  413. Unless each SPI slave has its own configuration registers, don't
  414. change them right away ... otherwise drivers could corrupt I/O
  415. that's in progress for other SPI devices.
  416. .. note::
  417. BUG ALERT: for some reason the first version of
  418. many spi_master drivers seems to get this wrong.
  419. When you code setup(), ASSUME that the controller
  420. is actively processing transfers for another device.
  421. ``master->cleanup(struct spi_device *spi)``
  422. Your controller driver may use spi_device.controller_state to hold
  423. state it dynamically associates with that device. If you do that,
  424. be sure to provide the cleanup() method to free that state.
  425. ``master->prepare_transfer_hardware(struct spi_master *master)``
  426. This will be called by the queue mechanism to signal to the driver
  427. that a message is coming in soon, so the subsystem requests the
  428. driver to prepare the transfer hardware by issuing this call.
  429. This may sleep.
  430. ``master->unprepare_transfer_hardware(struct spi_master *master)``
  431. This will be called by the queue mechanism to signal to the driver
  432. that there are no more messages pending in the queue and it may
  433. relax the hardware (e.g. by power management calls). This may sleep.
  434. ``master->transfer_one_message(struct spi_master *master, struct spi_message *mesg)``
  435. The subsystem calls the driver to transfer a single message while
  436. queuing transfers that arrive in the meantime. When the driver is
  437. finished with this message, it must call
  438. spi_finalize_current_message() so the subsystem can issue the next
  439. message. This may sleep.
  440. ``master->transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer)``
  441. The subsystem calls the driver to transfer a single transfer while
  442. queuing transfers that arrive in the meantime. When the driver is
  443. finished with this transfer, it must call
  444. spi_finalize_current_transfer() so the subsystem can issue the next
  445. transfer. This may sleep. Note: transfer_one and transfer_one_message
  446. are mutually exclusive; when both are set, the generic subsystem does
  447. not call your transfer_one callback.
  448. Return values:
  449. * negative errno: error
  450. * 0: transfer is finished
  451. * 1: transfer is still in progress
  452. ``master->set_cs_timing(struct spi_device *spi, u8 setup_clk_cycles, u8 hold_clk_cycles, u8 inactive_clk_cycles)``
  453. This method allows SPI client drivers to request SPI master controller
  454. for configuring device specific CS setup, hold and inactive timing
  455. requirements.
  456. Deprecated Methods
  457. ^^^^^^^^^^^^^^^^^^
  458. ``master->transfer(struct spi_device *spi, struct spi_message *message)``
  459. This must not sleep. Its responsibility is to arrange that the
  460. transfer happens and its complete() callback is issued. The two
  461. will normally happen later, after other transfers complete, and
  462. if the controller is idle it will need to be kickstarted. This
  463. method is not used on queued controllers and must be NULL if
  464. transfer_one_message() and (un)prepare_transfer_hardware() are
  465. implemented.
  466. SPI Message Queue
  467. ^^^^^^^^^^^^^^^^^
  468. If you are happy with the standard queueing mechanism provided by the
  469. SPI subsystem, just implement the queued methods specified above. Using
  470. the message queue has the upside of centralizing a lot of code and
  471. providing pure process-context execution of methods. The message queue
  472. can also be elevated to realtime priority on high-priority SPI traffic.
  473. Unless the queueing mechanism in the SPI subsystem is selected, the bulk
  474. of the driver will be managing the I/O queue fed by the now deprecated
  475. function transfer().
  476. That queue could be purely conceptual. For example, a driver used only
  477. for low-frequency sensor access might be fine using synchronous PIO.
  478. But the queue will probably be very real, using message->queue, PIO,
  479. often DMA (especially if the root filesystem is in SPI flash), and
  480. execution contexts like IRQ handlers, tasklets, or workqueues (such
  481. as keventd). Your driver can be as fancy, or as simple, as you need.
  482. Such a transfer() method would normally just add the message to a
  483. queue, and then start some asynchronous transfer engine (unless it's
  484. already running).
  485. THANKS TO
  486. ---------
  487. Contributors to Linux-SPI discussions include (in alphabetical order,
  488. by last name):
  489. - Mark Brown
  490. - David Brownell
  491. - Russell King
  492. - Grant Likely
  493. - Dmitry Pervushin
  494. - Stephen Street
  495. - Mark Underwood
  496. - Andrew Victor
  497. - Linus Walleij
  498. - Vitaly Wool