pxa2xx.rst 8.4 KB

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  1. ==============================
  2. PXA2xx SPI on SSP driver HOWTO
  3. ==============================
  4. This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
  5. synchronous serial port into a SPI master controller
  6. (see Documentation/spi/spi-summary.rst). The driver has the following features
  7. - Support for any PXA2xx SSP
  8. - SSP PIO and SSP DMA data transfers.
  9. - External and Internal (SSPFRM) chip selects.
  10. - Per slave device (chip) configuration.
  11. - Full suspend, freeze, resume support.
  12. The driver is built around a "spi_message" fifo serviced by workqueue and a
  13. tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
  14. (pump_transfer) is responsible for queuing SPI transactions and setting up and
  15. launching the dma/interrupt driven transfers.
  16. Declaring PXA2xx Master Controllers
  17. -----------------------------------
  18. Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
  19. "platform device". The master configuration is passed to the driver via a table
  20. found in include/linux/spi/pxa2xx_spi.h::
  21. struct pxa2xx_spi_controller {
  22. u16 num_chipselect;
  23. u8 enable_dma;
  24. };
  25. The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
  26. slave device (chips) attached to this SPI master.
  27. The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
  28. be used. This caused the driver to acquire two DMA channels: rx_channel and
  29. tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
  30. See the "PXA2xx Developer Manual" section "DMA Controller".
  31. NSSP MASTER SAMPLE
  32. ------------------
  33. Below is a sample configuration using the PXA255 NSSP::
  34. static struct resource pxa_spi_nssp_resources[] = {
  35. [0] = {
  36. .start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
  37. .end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
  38. .flags = IORESOURCE_MEM,
  39. },
  40. [1] = {
  41. .start = IRQ_NSSP, /* NSSP IRQ */
  42. .end = IRQ_NSSP,
  43. .flags = IORESOURCE_IRQ,
  44. },
  45. };
  46. static struct pxa2xx_spi_controller pxa_nssp_master_info = {
  47. .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
  48. .enable_dma = 1, /* Enables NSSP DMA */
  49. };
  50. static struct platform_device pxa_spi_nssp = {
  51. .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
  52. .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
  53. .resource = pxa_spi_nssp_resources,
  54. .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
  55. .dev = {
  56. .platform_data = &pxa_nssp_master_info, /* Passed to driver */
  57. },
  58. };
  59. static struct platform_device *devices[] __initdata = {
  60. &pxa_spi_nssp,
  61. };
  62. static void __init board_init(void)
  63. {
  64. (void)platform_add_device(devices, ARRAY_SIZE(devices));
  65. }
  66. Declaring Slave Devices
  67. -----------------------
  68. Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
  69. using the "spi_board_info" structure found in "linux/spi/spi.h". See
  70. "Documentation/spi/spi-summary.rst" for additional information.
  71. Each slave device attached to the PXA must provide slave specific configuration
  72. information via the structure "pxa2xx_spi_chip" found in
  73. "include/linux/spi/pxa2xx_spi.h". The pxa2xx_spi master controller driver
  74. will uses the configuration whenever the driver communicates with the slave
  75. device. All fields are optional.
  76. ::
  77. struct pxa2xx_spi_chip {
  78. u8 tx_threshold;
  79. u8 rx_threshold;
  80. u8 dma_burst_size;
  81. u32 timeout;
  82. u8 enable_loopback;
  83. void (*cs_control)(u32 command);
  84. };
  85. The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
  86. used to configure the SSP hardware fifo. These fields are critical to the
  87. performance of pxa2xx_spi driver and misconfiguration will result in rx
  88. fifo overruns (especially in PIO mode transfers). Good default values are::
  89. .tx_threshold = 8,
  90. .rx_threshold = 8,
  91. The range is 1 to 16 where zero indicates "use default".
  92. The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
  93. engine and is related the "spi_device.bits_per_word" field. Read and understand
  94. the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
  95. to determine the correct value. An SSP configured for byte-wide transfers would
  96. use a value of 8. The driver will determine a reasonable default if
  97. dma_burst_size == 0.
  98. The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
  99. trailing bytes in the SSP receiver fifo. The correct value for this field is
  100. dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
  101. slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
  102. timeouts and must busy-wait any trailing bytes.
  103. The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
  104. into internal loopback mode. In this mode the SSP controller internally
  105. connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
  106. testing.
  107. The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
  108. function for asserting/deasserting a slave device chip select. If the field is
  109. NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
  110. configured to use SSPFRM instead.
  111. NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
  112. chipselect is dropped after each spi_transfer. Most devices need chip select
  113. asserted around the complete message. Use SSPFRM as a GPIO (through cs_control)
  114. to accommodate these chips.
  115. NSSP SLAVE SAMPLE
  116. -----------------
  117. The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
  118. "spi_board_info.controller_data" field. Below is a sample configuration using
  119. the PXA255 NSSP.
  120. ::
  121. /* Chip Select control for the CS8415A SPI slave device */
  122. static void cs8415a_cs_control(u32 command)
  123. {
  124. if (command & PXA2XX_CS_ASSERT)
  125. GPCR(2) = GPIO_bit(2);
  126. else
  127. GPSR(2) = GPIO_bit(2);
  128. }
  129. /* Chip Select control for the CS8405A SPI slave device */
  130. static void cs8405a_cs_control(u32 command)
  131. {
  132. if (command & PXA2XX_CS_ASSERT)
  133. GPCR(3) = GPIO_bit(3);
  134. else
  135. GPSR(3) = GPIO_bit(3);
  136. }
  137. static struct pxa2xx_spi_chip cs8415a_chip_info = {
  138. .tx_threshold = 8, /* SSP hardward FIFO threshold */
  139. .rx_threshold = 8, /* SSP hardward FIFO threshold */
  140. .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
  141. .timeout = 235, /* See Intel documentation */
  142. .cs_control = cs8415a_cs_control, /* Use external chip select */
  143. };
  144. static struct pxa2xx_spi_chip cs8405a_chip_info = {
  145. .tx_threshold = 8, /* SSP hardward FIFO threshold */
  146. .rx_threshold = 8, /* SSP hardward FIFO threshold */
  147. .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
  148. .timeout = 235, /* See Intel documentation */
  149. .cs_control = cs8405a_cs_control, /* Use external chip select */
  150. };
  151. static struct spi_board_info streetracer_spi_board_info[] __initdata = {
  152. {
  153. .modalias = "cs8415a", /* Name of spi_driver for this device */
  154. .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
  155. .bus_num = 2, /* Framework bus number */
  156. .chip_select = 0, /* Framework chip select */
  157. .platform_data = NULL; /* No spi_driver specific config */
  158. .controller_data = &cs8415a_chip_info, /* Master chip config */
  159. .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
  160. },
  161. {
  162. .modalias = "cs8405a", /* Name of spi_driver for this device */
  163. .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
  164. .bus_num = 2, /* Framework bus number */
  165. .chip_select = 1, /* Framework chip select */
  166. .controller_data = &cs8405a_chip_info, /* Master chip config */
  167. .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
  168. },
  169. };
  170. static void __init streetracer_init(void)
  171. {
  172. spi_register_board_info(streetracer_spi_board_info,
  173. ARRAY_SIZE(streetracer_spi_board_info));
  174. }
  175. DMA and PIO I/O Support
  176. -----------------------
  177. The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
  178. transfers. The driver defaults to PIO mode and DMA transfers must be enabled
  179. by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA
  180. mode supports both coherent and stream based DMA mappings.
  181. The following logic is used to determine the type of I/O to be used on
  182. a per "spi_transfer" basis::
  183. if !enable_dma then
  184. always use PIO transfers
  185. if spi_message.len > 8191 then
  186. print "rate limited" warning
  187. use PIO transfers
  188. if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
  189. use coherent DMA mode
  190. if rx_buf and tx_buf are aligned on 8 byte boundary then
  191. use streaming DMA mode
  192. otherwise
  193. use PIO transfer
  194. THANKS TO
  195. ---------
  196. David Brownell and others for mentoring the development of this driver.