hptiop.rst 8.5 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. .. include:: <isonum.txt>
  3. ======================================================
  4. Highpoint RocketRAID 3xxx/4xxx Adapter Driver (hptiop)
  5. ======================================================
  6. Controller Register Map
  7. -----------------------
  8. For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2
  9. ============== ==================================
  10. BAR0 offset Register
  11. ============== ==================================
  12. 0x11C5C Link Interface IRQ Set
  13. 0x11C60 Link Interface IRQ Clear
  14. ============== ==================================
  15. ============== ==================================
  16. BAR2 offset Register
  17. ============== ==================================
  18. 0x10 Inbound Message Register 0
  19. 0x14 Inbound Message Register 1
  20. 0x18 Outbound Message Register 0
  21. 0x1C Outbound Message Register 1
  22. 0x20 Inbound Doorbell Register
  23. 0x24 Inbound Interrupt Status Register
  24. 0x28 Inbound Interrupt Mask Register
  25. 0x30 Outbound Interrupt Status Register
  26. 0x34 Outbound Interrupt Mask Register
  27. 0x40 Inbound Queue Port
  28. 0x44 Outbound Queue Port
  29. ============== ==================================
  30. For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:
  31. ============== ==================================
  32. BAR0 offset Register
  33. ============== ==================================
  34. 0x10 Inbound Message Register 0
  35. 0x14 Inbound Message Register 1
  36. 0x18 Outbound Message Register 0
  37. 0x1C Outbound Message Register 1
  38. 0x20 Inbound Doorbell Register
  39. 0x24 Inbound Interrupt Status Register
  40. 0x28 Inbound Interrupt Mask Register
  41. 0x30 Outbound Interrupt Status Register
  42. 0x34 Outbound Interrupt Mask Register
  43. 0x40 Inbound Queue Port
  44. 0x44 Outbound Queue Port
  45. ============== ==================================
  46. For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
  47. ============== ==================================
  48. BAR0 offset Register
  49. ============== ==================================
  50. 0x20400 Inbound Doorbell Register
  51. 0x20404 Inbound Interrupt Mask Register
  52. 0x20408 Outbound Doorbell Register
  53. 0x2040C Outbound Interrupt Mask Register
  54. ============== ==================================
  55. ============== ==================================
  56. BAR1 offset Register
  57. ============== ==================================
  58. 0x0 Inbound Queue Head Pointer
  59. 0x4 Inbound Queue Tail Pointer
  60. 0x8 Outbound Queue Head Pointer
  61. 0xC Outbound Queue Tail Pointer
  62. 0x10 Inbound Message Register
  63. 0x14 Outbound Message Register
  64. 0x40-0x1040 Inbound Queue
  65. 0x1040-0x2040 Outbound Queue
  66. ============== ==================================
  67. For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:
  68. ============== ==================================
  69. BAR0 offset Register
  70. ============== ==================================
  71. 0x0 IOP configuration information.
  72. ============== ==================================
  73. ============== ===================================================
  74. BAR1 offset Register
  75. ============== ===================================================
  76. 0x4000 Inbound List Base Address Low
  77. 0x4004 Inbound List Base Address High
  78. 0x4018 Inbound List Write Pointer
  79. 0x402C Inbound List Configuration and Control
  80. 0x4050 Outbound List Base Address Low
  81. 0x4054 Outbound List Base Address High
  82. 0x4058 Outbound List Copy Pointer Shadow Base Address Low
  83. 0x405C Outbound List Copy Pointer Shadow Base Address High
  84. 0x4088 Outbound List Interrupt Cause
  85. 0x408C Outbound List Interrupt Enable
  86. 0x1020C PCIe Function 0 Interrupt Enable
  87. 0x10400 PCIe Function 0 to CPU Message A
  88. 0x10420 CPU to PCIe Function 0 Message A
  89. 0x10480 CPU to PCIe Function 0 Doorbell
  90. 0x10484 CPU to PCIe Function 0 Doorbell Enable
  91. ============== ===================================================
  92. I/O Request Workflow of Not Marvell Frey
  93. ----------------------------------------
  94. All queued requests are handled via inbound/outbound queue port.
  95. A request packet can be allocated in either IOP or host memory.
  96. To send a request to the controller:
  97. - Get a free request packet by reading the inbound queue port or
  98. allocate a free request in host DMA coherent memory.
  99. The value returned from the inbound queue port is an offset
  100. relative to the IOP BAR0.
  101. Requests allocated in host memory must be aligned on 32-bytes boundary.
  102. - Fill the packet.
  103. - Post the packet to IOP by writing it to inbound queue. For requests
  104. allocated in IOP memory, write the offset to inbound queue port. For
  105. requests allocated in host memory, write (0x80000000|(bus_addr>>5))
  106. to the inbound queue port.
  107. - The IOP process the request. When the request is completed, it
  108. will be put into outbound queue. An outbound interrupt will be
  109. generated.
  110. For requests allocated in IOP memory, the request offset is posted to
  111. outbound queue.
  112. For requests allocated in host memory, (0x80000000|(bus_addr>>5))
  113. is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXT
  114. flag is set in the request, the low 32-bit context value will be
  115. posted instead.
  116. - The host read the outbound queue and complete the request.
  117. For requests allocated in IOP memory, the host driver free the request
  118. by writing it to the outbound queue.
  119. Non-queued requests (reset/flush etc) can be sent via inbound message
  120. register 0. An outbound message with the same value indicates the completion
  121. of an inbound message.
  122. I/O Request Workflow of Marvell Frey
  123. ------------------------------------
  124. All queued requests are handled via inbound/outbound list.
  125. To send a request to the controller:
  126. - Allocate a free request in host DMA coherent memory.
  127. Requests allocated in host memory must be aligned on 32-bytes boundary.
  128. - Fill the request with index of the request in the flag.
  129. Fill a free inbound list unit with the physical address and the size of
  130. the request.
  131. Set up the inbound list write pointer with the index of previous unit,
  132. round to 0 if the index reaches the supported count of requests.
  133. - Post the inbound list writer pointer to IOP.
  134. - The IOP process the request. When the request is completed, the flag of
  135. the request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into a
  136. free outbound list unit and the index of the outbound list unit will be
  137. put into the copy pointer shadow register. An outbound interrupt will be
  138. generated.
  139. - The host read the outbound list copy pointer shadow register and compare
  140. with previous saved read pointer N. If they are different, the host will
  141. read the (N+1)th outbound list unit.
  142. The host get the index of the request from the (N+1)th outbound list
  143. unit and complete the request.
  144. Non-queued requests (reset communication/reset/flush etc) can be sent via PCIe
  145. Function 0 to CPU Message A register. The CPU to PCIe Function 0 Message register
  146. with the same value indicates the completion of message.
  147. User-level Interface
  148. ---------------------
  149. The driver exposes following sysfs attributes:
  150. ================== === ========================
  151. NAME R/W Description
  152. ================== === ========================
  153. driver-version R driver version string
  154. firmware-version R firmware version string
  155. ================== === ========================
  156. -----------------------------------------------------------------------------
  157. Copyright |copy| 2006-2012 HighPoint Technologies, Inc. All Rights Reserved.
  158. This file is distributed in the hope that it will be useful,
  159. but WITHOUT ANY WARRANTY; without even the implied warranty of
  160. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  161. GNU General Public License for more details.
  162. linux@highpoint-tech.com
  163. http://www.highpoint-tech.com