phy.rst 22 KB

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  1. =====================
  2. PHY Abstraction Layer
  3. =====================
  4. Purpose
  5. =======
  6. Most network devices consist of set of registers which provide an interface
  7. to a MAC layer, which communicates with the physical connection through a
  8. PHY. The PHY concerns itself with negotiating link parameters with the link
  9. partner on the other side of the network connection (typically, an ethernet
  10. cable), and provides a register interface to allow drivers to determine what
  11. settings were chosen, and to configure what settings are allowed.
  12. While these devices are distinct from the network devices, and conform to a
  13. standard layout for the registers, it has been common practice to integrate
  14. the PHY management code with the network driver. This has resulted in large
  15. amounts of redundant code. Also, on embedded systems with multiple (and
  16. sometimes quite different) ethernet controllers connected to the same
  17. management bus, it is difficult to ensure safe use of the bus.
  18. Since the PHYs are devices, and the management busses through which they are
  19. accessed are, in fact, busses, the PHY Abstraction Layer treats them as such.
  20. In doing so, it has these goals:
  21. #. Increase code-reuse
  22. #. Increase overall code-maintainability
  23. #. Speed development time for new network drivers, and for new systems
  24. Basically, this layer is meant to provide an interface to PHY devices which
  25. allows network driver writers to write as little code as possible, while
  26. still providing a full feature set.
  27. The MDIO bus
  28. ============
  29. Most network devices are connected to a PHY by means of a management bus.
  30. Different devices use different busses (though some share common interfaces).
  31. In order to take advantage of the PAL, each bus interface needs to be
  32. registered as a distinct device.
  33. #. read and write functions must be implemented. Their prototypes are::
  34. int write(struct mii_bus *bus, int mii_id, int regnum, u16 value);
  35. int read(struct mii_bus *bus, int mii_id, int regnum);
  36. mii_id is the address on the bus for the PHY, and regnum is the register
  37. number. These functions are guaranteed not to be called from interrupt
  38. time, so it is safe for them to block, waiting for an interrupt to signal
  39. the operation is complete
  40. #. A reset function is optional. This is used to return the bus to an
  41. initialized state.
  42. #. A probe function is needed. This function should set up anything the bus
  43. driver needs, setup the mii_bus structure, and register with the PAL using
  44. mdiobus_register. Similarly, there's a remove function to undo all of
  45. that (use mdiobus_unregister).
  46. #. Like any driver, the device_driver structure must be configured, and init
  47. exit functions are used to register the driver.
  48. #. The bus must also be declared somewhere as a device, and registered.
  49. As an example for how one driver implemented an mdio bus driver, see
  50. drivers/net/ethernet/freescale/fsl_pq_mdio.c and an associated DTS file
  51. for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
  52. (RG)MII/electrical interface considerations
  53. ===========================================
  54. The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
  55. electrical signal interface using a synchronous 125Mhz clock signal and several
  56. data lines. Due to this design decision, a 1.5ns to 2ns delay must be added
  57. between the clock line (RXC or TXC) and the data lines to let the PHY (clock
  58. sink) have a large enough setup and hold time to sample the data lines correctly. The
  59. PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
  60. the PHY driver and optionally the MAC driver, implement the required delay. The
  61. values of phy_interface_t must be understood from the perspective of the PHY
  62. device itself, leading to the following:
  63. * PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any
  64. internal delay by itself, it assumes that either the Ethernet MAC (if capable
  65. or the PCB traces) insert the correct 1.5-2ns delay
  66. * PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay
  67. for the transmit data lines (TXD[3:0]) processed by the PHY device
  68. * PHY_INTERFACE_MODE_RGMII_RXID: the PHY should insert an internal delay
  69. for the receive data lines (RXD[3:0]) processed by the PHY device
  70. * PHY_INTERFACE_MODE_RGMII_ID: the PHY should insert internal delays for
  71. both transmit AND receive data lines from/to the PHY device
  72. Whenever possible, use the PHY side RGMII delay for these reasons:
  73. * PHY devices may offer sub-nanosecond granularity in how they allow a
  74. receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such
  75. precision may be required to account for differences in PCB trace lengths
  76. * PHY devices are typically qualified for a large range of applications
  77. (industrial, medical, automotive...), and they provide a constant and
  78. reliable delay across temperature/pressure/voltage ranges
  79. * PHY device drivers in PHYLIB being reusable by nature, being able to
  80. configure correctly a specified delay enables more designs with similar delay
  81. requirements to be operate correctly
  82. For cases where the PHY is not capable of providing this delay, but the
  83. Ethernet MAC driver is capable of doing so, the correct phy_interface_t value
  84. should be PHY_INTERFACE_MODE_RGMII, and the Ethernet MAC driver should be
  85. configured correctly in order to provide the required transmit and/or receive
  86. side delay from the perspective of the PHY device. Conversely, if the Ethernet
  87. MAC driver looks at the phy_interface_t value, for any other mode but
  88. PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
  89. disabled.
  90. In case neither the Ethernet MAC, nor the PHY are capable of providing the
  91. required delays, as defined per the RGMII standard, several options may be
  92. available:
  93. * Some SoCs may offer a pin pad/mux/controller capable of configuring a given
  94. set of pins'strength, delays, and voltage; and it may be a suitable
  95. option to insert the expected 2ns RGMII delay.
  96. * Modifying the PCB design to include a fixed delay (e.g: using a specifically
  97. designed serpentine), which may not require software configuration at all.
  98. Common problems with RGMII delay mismatch
  99. -----------------------------------------
  100. When there is a RGMII delay mismatch between the Ethernet MAC and the PHY, this
  101. will most likely result in the clock and data line signals to be unstable when
  102. the PHY or MAC take a snapshot of these signals to translate them into logical
  103. 1 or 0 states and reconstruct the data being transmitted/received. Typical
  104. symptoms include:
  105. * Transmission/reception partially works, and there is frequent or occasional
  106. packet loss observed
  107. * Ethernet MAC may report some or all packets ingressing with a FCS/CRC error,
  108. or just discard them all
  109. * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
  110. (since there is enough setup/hold time in that case)
  111. Connecting to a PHY
  112. ===================
  113. Sometime during startup, the network driver needs to establish a connection
  114. between the PHY device, and the network device. At this time, the PHY's bus
  115. and drivers need to all have been loaded, so it is ready for the connection.
  116. At this point, there are several ways to connect to the PHY:
  117. #. The PAL handles everything, and only calls the network driver when
  118. the link state changes, so it can react.
  119. #. The PAL handles everything except interrupts (usually because the
  120. controller has the interrupt registers).
  121. #. The PAL handles everything, but checks in with the driver every second,
  122. allowing the network driver to react first to any changes before the PAL
  123. does.
  124. #. The PAL serves only as a library of functions, with the network device
  125. manually calling functions to update status, and configure the PHY
  126. Letting the PHY Abstraction Layer do Everything
  127. ===============================================
  128. If you choose option 1 (The hope is that every driver can, but to still be
  129. useful to drivers that can't), connecting to the PHY is simple:
  130. First, you need a function to react to changes in the link state. This
  131. function follows this protocol::
  132. static void adjust_link(struct net_device *dev);
  133. Next, you need to know the device name of the PHY connected to this device.
  134. The name will look something like, "0:00", where the first number is the
  135. bus id, and the second is the PHY's address on that bus. Typically,
  136. the bus is responsible for making its ID unique.
  137. Now, to connect, just call this function::
  138. phydev = phy_connect(dev, phy_name, &adjust_link, interface);
  139. *phydev* is a pointer to the phy_device structure which represents the PHY.
  140. If phy_connect is successful, it will return the pointer. dev, here, is the
  141. pointer to your net_device. Once done, this function will have started the
  142. PHY's software state machine, and registered for the PHY's interrupt, if it
  143. has one. The phydev structure will be populated with information about the
  144. current state, though the PHY will not yet be truly operational at this
  145. point.
  146. PHY-specific flags should be set in phydev->dev_flags prior to the call
  147. to phy_connect() such that the underlying PHY driver can check for flags
  148. and perform specific operations based on them.
  149. This is useful if the system has put hardware restrictions on
  150. the PHY/controller, of which the PHY needs to be aware.
  151. *interface* is a u32 which specifies the connection type used
  152. between the controller and the PHY. Examples are GMII, MII,
  153. RGMII, and SGMII. See "PHY interface mode" below. For a full
  154. list, see include/linux/phy.h
  155. Now just make sure that phydev->supported and phydev->advertising have any
  156. values pruned from them which don't make sense for your controller (a 10/100
  157. controller may be connected to a gigabit capable PHY, so you would need to
  158. mask off SUPPORTED_1000baseT*). See include/linux/ethtool.h for definitions
  159. for these bitfields. Note that you should not SET any bits, except the
  160. SUPPORTED_Pause and SUPPORTED_AsymPause bits (see below), or the PHY may get
  161. put into an unsupported state.
  162. Lastly, once the controller is ready to handle network traffic, you call
  163. phy_start(phydev). This tells the PAL that you are ready, and configures the
  164. PHY to connect to the network. If the MAC interrupt of your network driver
  165. also handles PHY status changes, just set phydev->irq to PHY_IGNORE_INTERRUPT
  166. before you call phy_start and use phy_mac_interrupt() from the network
  167. driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
  168. phy_start() enables the PHY interrupts (if applicable) and starts the
  169. phylib state machine.
  170. When you want to disconnect from the network (even if just briefly), you call
  171. phy_stop(phydev). This function also stops the phylib state machine and
  172. disables PHY interrupts.
  173. PHY interface modes
  174. ===================
  175. The PHY interface mode supplied in the phy_connect() family of functions
  176. defines the initial operating mode of the PHY interface. This is not
  177. guaranteed to remain constant; there are PHYs which dynamically change
  178. their interface mode without software interaction depending on the
  179. negotiation results.
  180. Some of the interface modes are described below:
  181. ``PHY_INTERFACE_MODE_1000BASEX``
  182. This defines the 1000BASE-X single-lane serdes link as defined by the
  183. 802.3 standard section 36. The link operates at a fixed bit rate of
  184. 1.25Gbaud using a 10B/8B encoding scheme, resulting in an underlying
  185. data rate of 1Gbps. Embedded in the data stream is a 16-bit control
  186. word which is used to negotiate the duplex and pause modes with the
  187. remote end. This does not include "up-clocked" variants such as 2.5Gbps
  188. speeds (see below.)
  189. ``PHY_INTERFACE_MODE_2500BASEX``
  190. This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
  191. as the 802.3 standard, giving a fixed bit rate of 3.125Gbaud.
  192. ``PHY_INTERFACE_MODE_SGMII``
  193. This is used for Cisco SGMII, which is a modification of 1000BASE-X
  194. as defined by the 802.3 standard. The SGMII link consists of a single
  195. serdes lane running at a fixed bit rate of 1.25Gbaud with 10B/8B
  196. encoding. The underlying data rate is 1Gbps, with the slower speeds of
  197. 100Mbps and 10Mbps being achieved through replication of each data symbol.
  198. The 802.3 control word is re-purposed to send the negotiated speed and
  199. duplex information from to the MAC, and for the MAC to acknowledge
  200. receipt. This does not include "up-clocked" variants such as 2.5Gbps
  201. speeds.
  202. Note: mismatched SGMII vs 1000BASE-X configuration on a link can
  203. successfully pass data in some circumstances, but the 16-bit control
  204. word will not be correctly interpreted, which may cause mismatches in
  205. duplex, pause or other settings. This is dependent on the MAC and/or
  206. PHY behaviour.
  207. ``PHY_INTERFACE_MODE_10GBASER``
  208. This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
  209. various different mediums. Please refer to the IEEE standard for a
  210. definition of this.
  211. Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
  212. XFI and SFI permit multiple protocols over a single SERDES lane, and
  213. also defines the electrical characteristics of the signals with a host
  214. compliance board plugged into the host XFP/SFP connector. Therefore,
  215. XFI and SFI are not PHY interface types in their own right.
  216. ``PHY_INTERFACE_MODE_10GKR``
  217. This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
  218. autonegotiation. Please refer to the IEEE standard for further
  219. information.
  220. Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
  221. use of this definition.
  222. Pause frames / flow control
  223. ===========================
  224. The PHY does not participate directly in flow control/pause frames except by
  225. making sure that the SUPPORTED_Pause and SUPPORTED_AsymPause bits are set in
  226. MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
  227. controller supports such a thing. Since flow control/pause frames generation
  228. involves the Ethernet MAC driver, it is recommended that this driver takes care
  229. of properly indicating advertisement and support for such features by setting
  230. the SUPPORTED_Pause and SUPPORTED_AsymPause bits accordingly. This can be done
  231. either before or after phy_connect() and/or as a result of implementing the
  232. ethtool::set_pauseparam feature.
  233. Keeping Close Tabs on the PAL
  234. =============================
  235. It is possible that the PAL's built-in state machine needs a little help to
  236. keep your network device and the PHY properly in sync. If so, you can
  237. register a helper function when connecting to the PHY, which will be called
  238. every second before the state machine reacts to any changes. To do this, you
  239. need to manually call phy_attach() and phy_prepare_link(), and then call
  240. phy_start_machine() with the second argument set to point to your special
  241. handler.
  242. Currently there are no examples of how to use this functionality, and testing
  243. on it has been limited because the author does not have any drivers which use
  244. it (they all use option 1). So Caveat Emptor.
  245. Doing it all yourself
  246. =====================
  247. There's a remote chance that the PAL's built-in state machine cannot track
  248. the complex interactions between the PHY and your network device. If this is
  249. so, you can simply call phy_attach(), and not call phy_start_machine or
  250. phy_prepare_link(). This will mean that phydev->state is entirely yours to
  251. handle (phy_start and phy_stop toggle between some of the states, so you
  252. might need to avoid them).
  253. An effort has been made to make sure that useful functionality can be
  254. accessed without the state-machine running, and most of these functions are
  255. descended from functions which did not interact with a complex state-machine.
  256. However, again, no effort has been made so far to test running without the
  257. state machine, so tryer beware.
  258. Here is a brief rundown of the functions::
  259. int phy_read(struct phy_device *phydev, u16 regnum);
  260. int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
  261. Simple read/write primitives. They invoke the bus's read/write function
  262. pointers.
  263. ::
  264. void phy_print_status(struct phy_device *phydev);
  265. A convenience function to print out the PHY status neatly.
  266. ::
  267. void phy_request_interrupt(struct phy_device *phydev);
  268. Requests the IRQ for the PHY interrupts.
  269. ::
  270. struct phy_device * phy_attach(struct net_device *dev, const char *phy_id,
  271. phy_interface_t interface);
  272. Attaches a network device to a particular PHY, binding the PHY to a generic
  273. driver if none was found during bus initialization.
  274. ::
  275. int phy_start_aneg(struct phy_device *phydev);
  276. Using variables inside the phydev structure, either configures advertising
  277. and resets autonegotiation, or disables autonegotiation, and configures
  278. forced settings.
  279. ::
  280. static inline int phy_read_status(struct phy_device *phydev);
  281. Fills the phydev structure with up-to-date information about the current
  282. settings in the PHY.
  283. ::
  284. int phy_ethtool_ksettings_set(struct phy_device *phydev,
  285. const struct ethtool_link_ksettings *cmd);
  286. Ethtool convenience functions.
  287. ::
  288. int phy_mii_ioctl(struct phy_device *phydev,
  289. struct mii_ioctl_data *mii_data, int cmd);
  290. The MII ioctl. Note that this function will completely screw up the state
  291. machine if you write registers like BMCR, BMSR, ADVERTISE, etc. Best to
  292. use this only to write registers which are not standard, and don't set off
  293. a renegotiation.
  294. PHY Device Drivers
  295. ==================
  296. With the PHY Abstraction Layer, adding support for new PHYs is
  297. quite easy. In some cases, no work is required at all! However,
  298. many PHYs require a little hand-holding to get up-and-running.
  299. Generic PHY driver
  300. ------------------
  301. If the desired PHY doesn't have any errata, quirks, or special
  302. features you want to support, then it may be best to not add
  303. support, and let the PHY Abstraction Layer's Generic PHY Driver
  304. do all of the work.
  305. Writing a PHY driver
  306. --------------------
  307. If you do need to write a PHY driver, the first thing to do is
  308. make sure it can be matched with an appropriate PHY device.
  309. This is done during bus initialization by reading the device's
  310. UID (stored in registers 2 and 3), then comparing it to each
  311. driver's phy_id field by ANDing it with each driver's
  312. phy_id_mask field. Also, it needs a name. Here's an example::
  313. static struct phy_driver dm9161_driver = {
  314. .phy_id = 0x0181b880,
  315. .name = "Davicom DM9161E",
  316. .phy_id_mask = 0x0ffffff0,
  317. ...
  318. }
  319. Next, you need to specify what features (speed, duplex, autoneg,
  320. etc) your PHY device and driver support. Most PHYs support
  321. PHY_BASIC_FEATURES, but you can look in include/mii.h for other
  322. features.
  323. Each driver consists of a number of function pointers, documented
  324. in include/linux/phy.h under the phy_driver structure.
  325. Of these, only config_aneg and read_status are required to be
  326. assigned by the driver code. The rest are optional. Also, it is
  327. preferred to use the generic phy driver's versions of these two
  328. functions if at all possible: genphy_read_status and
  329. genphy_config_aneg. If this is not possible, it is likely that
  330. you only need to perform some actions before and after invoking
  331. these functions, and so your functions will wrap the generic
  332. ones.
  333. Feel free to look at the Marvell, Cicada, and Davicom drivers in
  334. drivers/net/phy/ for examples (the lxt and qsemi drivers have
  335. not been tested as of this writing).
  336. The PHY's MMD register accesses are handled by the PAL framework
  337. by default, but can be overridden by a specific PHY driver if
  338. required. This could be the case if a PHY was released for
  339. manufacturing before the MMD PHY register definitions were
  340. standardized by the IEEE. Most modern PHYs will be able to use
  341. the generic PAL framework for accessing the PHY's MMD registers.
  342. An example of such usage is for Energy Efficient Ethernet support,
  343. implemented in the PAL. This support uses the PAL to access MMD
  344. registers for EEE query and configuration if the PHY supports
  345. the IEEE standard access mechanisms, or can use the PHY's specific
  346. access interfaces if overridden by the specific PHY driver. See
  347. the Micrel driver in drivers/net/phy/ for an example of how this
  348. can be implemented.
  349. Board Fixups
  350. ============
  351. Sometimes the specific interaction between the platform and the PHY requires
  352. special handling. For instance, to change where the PHY's clock input is,
  353. or to add a delay to account for latency issues in the data path. In order
  354. to support such contingencies, the PHY Layer allows platform code to register
  355. fixups to be run when the PHY is brought up (or subsequently reset).
  356. When the PHY Layer brings up a PHY it checks to see if there are any fixups
  357. registered for it, matching based on UID (contained in the PHY device's phy_id
  358. field) and the bus identifier (contained in phydev->dev.bus_id). Both must
  359. match, however two constants, PHY_ANY_ID and PHY_ANY_UID, are provided as
  360. wildcards for the bus ID and UID, respectively.
  361. When a match is found, the PHY layer will invoke the run function associated
  362. with the fixup. This function is passed a pointer to the phy_device of
  363. interest. It should therefore only operate on that PHY.
  364. The platform code can either register the fixup using phy_register_fixup()::
  365. int phy_register_fixup(const char *phy_id,
  366. u32 phy_uid, u32 phy_uid_mask,
  367. int (*run)(struct phy_device *));
  368. Or using one of the two stubs, phy_register_fixup_for_uid() and
  369. phy_register_fixup_for_id()::
  370. int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask,
  371. int (*run)(struct phy_device *));
  372. int phy_register_fixup_for_id(const char *phy_id,
  373. int (*run)(struct phy_device *));
  374. The stubs set one of the two matching criteria, and set the other one to
  375. match anything.
  376. When phy_register_fixup() or \*_for_uid()/\*_for_id() is called at module load
  377. time, the module needs to unregister the fixup and free allocated memory when
  378. it's unloaded.
  379. Call one of following function before unloading module::
  380. int phy_unregister_fixup(const char *phy_id, u32 phy_uid, u32 phy_uid_mask);
  381. int phy_unregister_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask);
  382. int phy_register_fixup_for_id(const char *phy_id);
  383. Standards
  384. =========
  385. IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two:
  386. http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf
  387. RGMII v1.3:
  388. http://web.archive.org/web/20160303212629/http://www.hp.com/rnd/pdfs/RGMIIv1_3.pdf
  389. RGMII v2.0:
  390. http://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf