i2c-topology.rst 16 KB

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  1. ================================
  2. I2C muxes and complex topologies
  3. ================================
  4. There are a couple of reasons for building more complex I2C topologies
  5. than a straight-forward I2C bus with one adapter and one or more devices.
  6. 1. A mux may be needed on the bus to prevent address collisions.
  7. 2. The bus may be accessible from some external bus master, and arbitration
  8. may be needed to determine if it is ok to access the bus.
  9. 3. A device (particularly RF tuners) may want to avoid the digital noise
  10. from the I2C bus, at least most of the time, and sits behind a gate
  11. that has to be operated before the device can be accessed.
  12. Etc
  13. ===
  14. These constructs are represented as I2C adapter trees by Linux, where
  15. each adapter has a parent adapter (except the root adapter) and zero or
  16. more child adapters. The root adapter is the actual adapter that issues
  17. I2C transfers, and all adapters with a parent are part of an "i2c-mux"
  18. object (quoted, since it can also be an arbitrator or a gate).
  19. Depending of the particular mux driver, something happens when there is
  20. an I2C transfer on one of its child adapters. The mux driver can
  21. obviously operate a mux, but it can also do arbitration with an external
  22. bus master or open a gate. The mux driver has two operations for this,
  23. select and deselect. select is called before the transfer and (the
  24. optional) deselect is called after the transfer.
  25. Locking
  26. =======
  27. There are two variants of locking available to I2C muxes, they can be
  28. mux-locked or parent-locked muxes. As is evident from below, it can be
  29. useful to know if a mux is mux-locked or if it is parent-locked. The
  30. following list was correct at the time of writing:
  31. In drivers/i2c/muxes/:
  32. ====================== =============================================
  33. i2c-arb-gpio-challenge Parent-locked
  34. i2c-mux-gpio Normally parent-locked, mux-locked iff
  35. all involved gpio pins are controlled by the
  36. same I2C root adapter that they mux.
  37. i2c-mux-gpmux Normally parent-locked, mux-locked iff
  38. specified in device-tree.
  39. i2c-mux-ltc4306 Mux-locked
  40. i2c-mux-mlxcpld Parent-locked
  41. i2c-mux-pca9541 Parent-locked
  42. i2c-mux-pca954x Parent-locked
  43. i2c-mux-pinctrl Normally parent-locked, mux-locked iff
  44. all involved pinctrl devices are controlled
  45. by the same I2C root adapter that they mux.
  46. i2c-mux-reg Parent-locked
  47. ====================== =============================================
  48. In drivers/iio/:
  49. ====================== =============================================
  50. gyro/mpu3050 Mux-locked
  51. imu/inv_mpu6050/ Mux-locked
  52. ====================== =============================================
  53. In drivers/media/:
  54. ======================= =============================================
  55. dvb-frontends/lgdt3306a Mux-locked
  56. dvb-frontends/m88ds3103 Parent-locked
  57. dvb-frontends/rtl2830 Parent-locked
  58. dvb-frontends/rtl2832 Mux-locked
  59. dvb-frontends/si2168 Mux-locked
  60. usb/cx231xx/ Parent-locked
  61. ======================= =============================================
  62. Mux-locked muxes
  63. ----------------
  64. Mux-locked muxes does not lock the entire parent adapter during the
  65. full select-transfer-deselect transaction, only the muxes on the parent
  66. adapter are locked. Mux-locked muxes are mostly interesting if the
  67. select and/or deselect operations must use I2C transfers to complete
  68. their tasks. Since the parent adapter is not fully locked during the
  69. full transaction, unrelated I2C transfers may interleave the different
  70. stages of the transaction. This has the benefit that the mux driver
  71. may be easier and cleaner to implement, but it has some caveats.
  72. ==== =====================================================================
  73. ML1. If you build a topology with a mux-locked mux being the parent
  74. of a parent-locked mux, this might break the expectation from the
  75. parent-locked mux that the root adapter is locked during the
  76. transaction.
  77. ML2. It is not safe to build arbitrary topologies with two (or more)
  78. mux-locked muxes that are not siblings, when there are address
  79. collisions between the devices on the child adapters of these
  80. non-sibling muxes.
  81. I.e. the select-transfer-deselect transaction targeting e.g. device
  82. address 0x42 behind mux-one may be interleaved with a similar
  83. operation targeting device address 0x42 behind mux-two. The
  84. intension with such a topology would in this hypothetical example
  85. be that mux-one and mux-two should not be selected simultaneously,
  86. but mux-locked muxes do not guarantee that in all topologies.
  87. ML3. A mux-locked mux cannot be used by a driver for auto-closing
  88. gates/muxes, i.e. something that closes automatically after a given
  89. number (one, in most cases) of I2C transfers. Unrelated I2C transfers
  90. may creep in and close prematurely.
  91. ML4. If any non-I2C operation in the mux driver changes the I2C mux state,
  92. the driver has to lock the root adapter during that operation.
  93. Otherwise garbage may appear on the bus as seen from devices
  94. behind the mux, when an unrelated I2C transfer is in flight during
  95. the non-I2C mux-changing operation.
  96. ==== =====================================================================
  97. Mux-locked Example
  98. ------------------
  99. ::
  100. .----------. .--------.
  101. .--------. | mux- |-----| dev D1 |
  102. | root |--+--| locked | '--------'
  103. '--------' | | mux M1 |--. .--------.
  104. | '----------' '--| dev D2 |
  105. | .--------. '--------'
  106. '--| dev D3 |
  107. '--------'
  108. When there is an access to D1, this happens:
  109. 1. Someone issues an I2C transfer to D1.
  110. 2. M1 locks muxes on its parent (the root adapter in this case).
  111. 3. M1 calls ->select to ready the mux.
  112. 4. M1 (presumably) does some I2C transfers as part of its select.
  113. These transfers are normal I2C transfers that locks the parent
  114. adapter.
  115. 5. M1 feeds the I2C transfer from step 1 to its parent adapter as a
  116. normal I2C transfer that locks the parent adapter.
  117. 6. M1 calls ->deselect, if it has one.
  118. 7. Same rules as in step 4, but for ->deselect.
  119. 8. M1 unlocks muxes on its parent.
  120. This means that accesses to D2 are lockout out for the full duration
  121. of the entire operation. But accesses to D3 are possibly interleaved
  122. at any point.
  123. Parent-locked muxes
  124. -------------------
  125. Parent-locked muxes lock the parent adapter during the full select-
  126. transfer-deselect transaction. The implication is that the mux driver
  127. has to ensure that any and all I2C transfers through that parent
  128. adapter during the transaction are unlocked I2C transfers (using e.g.
  129. __i2c_transfer), or a deadlock will follow. There are a couple of
  130. caveats.
  131. ==== ====================================================================
  132. PL1. If you build a topology with a parent-locked mux being the child
  133. of another mux, this might break a possible assumption from the
  134. child mux that the root adapter is unused between its select op
  135. and the actual transfer (e.g. if the child mux is auto-closing
  136. and the parent mux issues I2C transfers as part of its select).
  137. This is especially the case if the parent mux is mux-locked, but
  138. it may also happen if the parent mux is parent-locked.
  139. PL2. If select/deselect calls out to other subsystems such as gpio,
  140. pinctrl, regmap or iio, it is essential that any I2C transfers
  141. caused by these subsystems are unlocked. This can be convoluted to
  142. accomplish, maybe even impossible if an acceptably clean solution
  143. is sought.
  144. ==== ====================================================================
  145. Parent-locked Example
  146. ---------------------
  147. ::
  148. .----------. .--------.
  149. .--------. | parent- |-----| dev D1 |
  150. | root |--+--| locked | '--------'
  151. '--------' | | mux M1 |--. .--------.
  152. | '----------' '--| dev D2 |
  153. | .--------. '--------'
  154. '--| dev D3 |
  155. '--------'
  156. When there is an access to D1, this happens:
  157. 1. Someone issues an I2C transfer to D1.
  158. 2. M1 locks muxes on its parent (the root adapter in this case).
  159. 3. M1 locks its parent adapter.
  160. 4. M1 calls ->select to ready the mux.
  161. 5. If M1 does any I2C transfers (on this root adapter) as part of
  162. its select, those transfers must be unlocked I2C transfers so
  163. that they do not deadlock the root adapter.
  164. 6. M1 feeds the I2C transfer from step 1 to the root adapter as an
  165. unlocked I2C transfer, so that it does not deadlock the parent
  166. adapter.
  167. 7. M1 calls ->deselect, if it has one.
  168. 8. Same rules as in step 5, but for ->deselect.
  169. 9. M1 unlocks its parent adapter.
  170. 10. M1 unlocks muxes on its parent.
  171. This means that accesses to both D2 and D3 are locked out for the full
  172. duration of the entire operation.
  173. Complex Examples
  174. ================
  175. Parent-locked mux as parent of parent-locked mux
  176. ------------------------------------------------
  177. This is a useful topology, but it can be bad::
  178. .----------. .----------. .--------.
  179. .--------. | parent- |-----| parent- |-----| dev D1 |
  180. | root |--+--| locked | | locked | '--------'
  181. '--------' | | mux M1 |--. | mux M2 |--. .--------.
  182. | '----------' | '----------' '--| dev D2 |
  183. | .--------. | .--------. '--------'
  184. '--| dev D4 | '--| dev D3 |
  185. '--------' '--------'
  186. When any device is accessed, all other devices are locked out for
  187. the full duration of the operation (both muxes lock their parent,
  188. and specifically when M2 requests its parent to lock, M1 passes
  189. the buck to the root adapter).
  190. This topology is bad if M2 is an auto-closing mux and M1->select
  191. issues any unlocked I2C transfers on the root adapter that may leak
  192. through and be seen by the M2 adapter, thus closing M2 prematurely.
  193. Mux-locked mux as parent of mux-locked mux
  194. ------------------------------------------
  195. This is a good topology::
  196. .----------. .----------. .--------.
  197. .--------. | mux- |-----| mux- |-----| dev D1 |
  198. | root |--+--| locked | | locked | '--------'
  199. '--------' | | mux M1 |--. | mux M2 |--. .--------.
  200. | '----------' | '----------' '--| dev D2 |
  201. | .--------. | .--------. '--------'
  202. '--| dev D4 | '--| dev D3 |
  203. '--------' '--------'
  204. When device D1 is accessed, accesses to D2 are locked out for the
  205. full duration of the operation (muxes on the top child adapter of M1
  206. are locked). But accesses to D3 and D4 are possibly interleaved at
  207. any point. Accesses to D3 locks out D1 and D2, but accesses to D4
  208. are still possibly interleaved.
  209. Mux-locked mux as parent of parent-locked mux
  210. ---------------------------------------------
  211. This is probably a bad topology::
  212. .----------. .----------. .--------.
  213. .--------. | mux- |-----| parent- |-----| dev D1 |
  214. | root |--+--| locked | | locked | '--------'
  215. '--------' | | mux M1 |--. | mux M2 |--. .--------.
  216. | '----------' | '----------' '--| dev D2 |
  217. | .--------. | .--------. '--------'
  218. '--| dev D4 | '--| dev D3 |
  219. '--------' '--------'
  220. When device D1 is accessed, accesses to D2 and D3 are locked out
  221. for the full duration of the operation (M1 locks child muxes on the
  222. root adapter). But accesses to D4 are possibly interleaved at any
  223. point.
  224. This kind of topology is generally not suitable and should probably
  225. be avoided. The reason is that M2 probably assumes that there will
  226. be no I2C transfers during its calls to ->select and ->deselect, and
  227. if there are, any such transfers might appear on the slave side of M2
  228. as partial I2C transfers, i.e. garbage or worse. This might cause
  229. device lockups and/or other problems.
  230. The topology is especially troublesome if M2 is an auto-closing
  231. mux. In that case, any interleaved accesses to D4 might close M2
  232. prematurely, as might any I2C transfers part of M1->select.
  233. But if M2 is not making the above stated assumption, and if M2 is not
  234. auto-closing, the topology is fine.
  235. Parent-locked mux as parent of mux-locked mux
  236. ---------------------------------------------
  237. This is a good topology::
  238. .----------. .----------. .--------.
  239. .--------. | parent- |-----| mux- |-----| dev D1 |
  240. | root |--+--| locked | | locked | '--------'
  241. '--------' | | mux M1 |--. | mux M2 |--. .--------.
  242. | '----------' | '----------' '--| dev D2 |
  243. | .--------. | .--------. '--------'
  244. '--| dev D4 | '--| dev D3 |
  245. '--------' '--------'
  246. When D1 is accessed, accesses to D2 are locked out for the full
  247. duration of the operation (muxes on the top child adapter of M1
  248. are locked). Accesses to D3 and D4 are possibly interleaved at
  249. any point, just as is expected for mux-locked muxes.
  250. When D3 or D4 are accessed, everything else is locked out. For D3
  251. accesses, M1 locks the root adapter. For D4 accesses, the root
  252. adapter is locked directly.
  253. Two mux-locked sibling muxes
  254. ----------------------------
  255. This is a good topology::
  256. .--------.
  257. .----------. .--| dev D1 |
  258. | mux- |--' '--------'
  259. .--| locked | .--------.
  260. | | mux M1 |-----| dev D2 |
  261. | '----------' '--------'
  262. | .----------. .--------.
  263. .--------. | | mux- |-----| dev D3 |
  264. | root |--+--| locked | '--------'
  265. '--------' | | mux M2 |--. .--------.
  266. | '----------' '--| dev D4 |
  267. | .--------. '--------'
  268. '--| dev D5 |
  269. '--------'
  270. When D1 is accessed, accesses to D2, D3 and D4 are locked out. But
  271. accesses to D5 may be interleaved at any time.
  272. Two parent-locked sibling muxes
  273. -------------------------------
  274. This is a good topology::
  275. .--------.
  276. .----------. .--| dev D1 |
  277. | parent- |--' '--------'
  278. .--| locked | .--------.
  279. | | mux M1 |-----| dev D2 |
  280. | '----------' '--------'
  281. | .----------. .--------.
  282. .--------. | | parent- |-----| dev D3 |
  283. | root |--+--| locked | '--------'
  284. '--------' | | mux M2 |--. .--------.
  285. | '----------' '--| dev D4 |
  286. | .--------. '--------'
  287. '--| dev D5 |
  288. '--------'
  289. When any device is accessed, accesses to all other devices are locked
  290. out.
  291. Mux-locked and parent-locked sibling muxes
  292. ------------------------------------------
  293. This is a good topology::
  294. .--------.
  295. .----------. .--| dev D1 |
  296. | mux- |--' '--------'
  297. .--| locked | .--------.
  298. | | mux M1 |-----| dev D2 |
  299. | '----------' '--------'
  300. | .----------. .--------.
  301. .--------. | | parent- |-----| dev D3 |
  302. | root |--+--| locked | '--------'
  303. '--------' | | mux M2 |--. .--------.
  304. | '----------' '--| dev D4 |
  305. | .--------. '--------'
  306. '--| dev D5 |
  307. '--------'
  308. When D1 or D2 are accessed, accesses to D3 and D4 are locked out while
  309. accesses to D5 may interleave. When D3 or D4 are accessed, accesses to
  310. all other devices are locked out.