i915.rst 21 KB

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  1. ===========================
  2. drm/i915 Intel GFX Driver
  3. ===========================
  4. The drm/i915 driver supports all (with the exception of some very early
  5. models) integrated GFX chipsets with both Intel display and rendering
  6. blocks. This excludes a set of SoC platforms with an SGX rendering unit,
  7. those have basic support through the gma500 drm driver.
  8. Core Driver Infrastructure
  9. ==========================
  10. This section covers core driver infrastructure used by both the display
  11. and the GEM parts of the driver.
  12. Runtime Power Management
  13. ------------------------
  14. .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
  15. :doc: runtime pm
  16. .. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c
  17. :internal:
  18. .. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c
  19. :internal:
  20. Interrupt Handling
  21. ------------------
  22. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  23. :doc: interrupt handling
  24. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  25. :functions: intel_irq_init intel_irq_init_hw intel_hpd_init
  26. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  27. :functions: intel_runtime_pm_disable_interrupts
  28. .. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c
  29. :functions: intel_runtime_pm_enable_interrupts
  30. Intel GVT-g Guest Support(vGPU)
  31. -------------------------------
  32. .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
  33. :doc: Intel GVT-g guest support
  34. .. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c
  35. :internal:
  36. Intel GVT-g Host Support(vGPU device model)
  37. -------------------------------------------
  38. .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
  39. :doc: Intel GVT-g host support
  40. .. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c
  41. :internal:
  42. Workarounds
  43. -----------
  44. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c
  45. :doc: Hardware workarounds
  46. Display Hardware Handling
  47. =========================
  48. This section covers everything related to the display hardware including
  49. the mode setting infrastructure, plane, sprite and cursor handling and
  50. display, output probing and related topics.
  51. Mode Setting Infrastructure
  52. ---------------------------
  53. The i915 driver is thus far the only DRM driver which doesn't use the
  54. common DRM helper code to implement mode setting sequences. Thus it has
  55. its own tailor-made infrastructure for executing a display configuration
  56. change.
  57. Frontbuffer Tracking
  58. --------------------
  59. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
  60. :doc: frontbuffer tracking
  61. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h
  62. :internal:
  63. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c
  64. :internal:
  65. Display FIFO Underrun Reporting
  66. -------------------------------
  67. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
  68. :doc: fifo underrun handling
  69. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c
  70. :internal:
  71. Plane Configuration
  72. -------------------
  73. This section covers plane configuration and composition with the primary
  74. plane, sprites, cursors and overlays. This includes the infrastructure
  75. to do atomic vsync'ed updates of all this state and also tightly coupled
  76. topics like watermark setup and computation, framebuffer compression and
  77. panel self refresh.
  78. Atomic Plane Helpers
  79. --------------------
  80. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
  81. :doc: atomic plane helpers
  82. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
  83. :internal:
  84. Output Probing
  85. --------------
  86. This section covers output probing and related infrastructure like the
  87. hotplug interrupt storm detection and mitigation code. Note that the
  88. i915 driver still uses most of the common DRM helper code for output
  89. probing, so those sections fully apply.
  90. Hotplug
  91. -------
  92. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
  93. :doc: Hotplug
  94. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c
  95. :internal:
  96. High Definition Audio
  97. ---------------------
  98. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
  99. :doc: High Definition Audio over HDMI and Display Port
  100. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
  101. :internal:
  102. .. kernel-doc:: include/drm/i915_component.h
  103. :internal:
  104. Intel HDMI LPE Audio Support
  105. ----------------------------
  106. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
  107. :doc: LPE Audio integration for HDMI or DP playback
  108. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c
  109. :internal:
  110. Panel Self Refresh PSR (PSR/SRD)
  111. --------------------------------
  112. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
  113. :doc: Panel Self Refresh (PSR/SRD)
  114. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c
  115. :internal:
  116. Frame Buffer Compression (FBC)
  117. ------------------------------
  118. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
  119. :doc: Frame Buffer Compression (FBC)
  120. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c
  121. :internal:
  122. Display Refresh Rate Switching (DRRS)
  123. -------------------------------------
  124. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  125. :doc: Display Refresh Rate Switching (DRRS)
  126. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  127. :functions: intel_dp_set_drrs_state
  128. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  129. :functions: intel_edp_drrs_enable
  130. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  131. :functions: intel_edp_drrs_disable
  132. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  133. :functions: intel_edp_drrs_invalidate
  134. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  135. :functions: intel_edp_drrs_flush
  136. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c
  137. :functions: intel_dp_drrs_init
  138. DPIO
  139. ----
  140. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c
  141. :doc: DPIO
  142. CSR firmware support for DMC
  143. ----------------------------
  144. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
  145. :doc: csr support for dmc
  146. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_csr.c
  147. :internal:
  148. Video BIOS Table (VBT)
  149. ----------------------
  150. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
  151. :doc: Video BIOS Table (VBT)
  152. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c
  153. :internal:
  154. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h
  155. :internal:
  156. Display clocks
  157. --------------
  158. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
  159. :doc: CDCLK / RAWCLK
  160. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c
  161. :internal:
  162. Display PLLs
  163. ------------
  164. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
  165. :doc: Display PLLs
  166. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c
  167. :internal:
  168. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h
  169. :internal:
  170. Display State Buffer
  171. --------------------
  172. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
  173. :doc: DSB
  174. .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c
  175. :internal:
  176. Memory Management and Command Submission
  177. ========================================
  178. This sections covers all things related to the GEM implementation in the
  179. i915 driver.
  180. Intel GPU Basics
  181. ----------------
  182. An Intel GPU has multiple engines. There are several engine types.
  183. - RCS engine is for rendering 3D and performing compute, this is named
  184. `I915_EXEC_RENDER` in user space.
  185. - BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
  186. space.
  187. - VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
  188. in user space
  189. - VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
  190. space.
  191. - The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
  192. instead it is to be used by user space to specify a default rendering
  193. engine (for 3D) that may or may not be the same as RCS.
  194. The Intel GPU family is a family of integrated GPU's using Unified
  195. Memory Access. For having the GPU "do work", user space will feed the
  196. GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2`
  197. or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will
  198. instruct the GPU to perform work (for example rendering) and that work
  199. needs memory from which to read and memory to which to write. All memory
  200. is encapsulated within GEM buffer objects (usually created with the ioctl
  201. `DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU
  202. to create will also list all GEM buffer objects that the batchbuffer reads
  203. and/or writes. For implementation details of memory management see
  204. `GEM BO Management Implementation Details`_.
  205. The i915 driver allows user space to create a context via the ioctl
  206. `DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit
  207. integer. Such a context should be viewed by user-space as -loosely-
  208. analogous to the idea of a CPU process of an operating system. The i915
  209. driver guarantees that commands issued to a fixed context are to be
  210. executed so that writes of a previously issued command are seen by
  211. reads of following commands. Actions issued between different contexts
  212. (even if from the same file descriptor) are NOT given that guarantee
  213. and the only way to synchronize across contexts (even from the same
  214. file descriptor) is through the use of fences. At least as far back as
  215. Gen4, also have that a context carries with it a GPU HW context;
  216. the HW context is essentially (most of atleast) the state of a GPU.
  217. In addition to the ordering guarantees, the kernel will restore GPU
  218. state via HW context when commands are issued to a context, this saves
  219. user space the need to restore (most of atleast) the GPU state at the
  220. start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer
  221. work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1)
  222. to identify what context to use with the command.
  223. The GPU has its own memory management and address space. The kernel
  224. driver maintains the memory translation table for the GPU. For older
  225. GPUs (i.e. those before Gen8), there is a single global such translation
  226. table, a global Graphics Translation Table (GTT). For newer generation
  227. GPUs each context has its own translation table, called Per-Process
  228. Graphics Translation Table (PPGTT). Of important note, is that although
  229. PPGTT is named per-process it is actually per context. When user space
  230. submits a batchbuffer, the kernel walks the list of GEM buffer objects
  231. used by the batchbuffer and guarantees that not only is the memory of
  232. each such GEM buffer object resident but it is also present in the
  233. (PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT,
  234. then it is given an address. Two consequences of this are: the kernel
  235. needs to edit the batchbuffer submitted to write the correct value of
  236. the GPU address when a GEM BO is assigned a GPU address and the kernel
  237. might evict a different GEM BO from the (PP)GTT to make address room
  238. for another GEM BO. Consequently, the ioctls submitting a batchbuffer
  239. for execution also include a list of all locations within buffers that
  240. refer to GPU-addresses so that the kernel can edit the buffer correctly.
  241. This process is dubbed relocation.
  242. Locking Guidelines
  243. ------------------
  244. .. note::
  245. This is a description of how the locking should be after
  246. refactoring is done. Does not necessarily reflect what the locking
  247. looks like while WIP.
  248. #. All locking rules and interface contracts with cross-driver interfaces
  249. (dma-buf, dma_fence) need to be followed.
  250. #. No struct_mutex anywhere in the code
  251. #. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx
  252. is to be hoisted at highest level and passed down within i915_gem_ctx
  253. in the call chain
  254. #. While holding lru/memory manager (buddy, drm_mm, whatever) locks
  255. system memory allocations are not allowed
  256. * Enforce this by priming lockdep (with fs_reclaim). If we
  257. allocate memory while holding these looks we get a rehash
  258. of the shrinker vs. struct_mutex saga, and that would be
  259. real bad.
  260. #. Do not nest different lru/memory manager locks within each other.
  261. Take them in turn to update memory allocations, relying on the object’s
  262. dma_resv ww_mutex to serialize against other operations.
  263. #. The suggestion for lru/memory managers locks is that they are small
  264. enough to be spinlocks.
  265. #. All features need to come with exhaustive kernel selftests and/or
  266. IGT tests when appropriate
  267. #. All LMEM uAPI paths need to be fully restartable (_interruptible()
  268. for all locks/waits/sleeps)
  269. * Error handling validation through signal injection.
  270. Still the best strategy we have for validating GEM uAPI
  271. corner cases.
  272. Must be excessively used in the IGT, and we need to check
  273. that we really have full path coverage of all error cases.
  274. * -EDEADLK handling with ww_mutex
  275. GEM BO Management Implementation Details
  276. ----------------------------------------
  277. .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
  278. :doc: Virtual Memory Address
  279. Buffer Object Eviction
  280. ----------------------
  281. This section documents the interface functions for evicting buffer
  282. objects to make space available in the virtual gpu address spaces. Note
  283. that this is mostly orthogonal to shrinking buffer objects caches, which
  284. has the goal to make main memory (shared with the gpu through the
  285. unified memory architecture) available.
  286. .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c
  287. :internal:
  288. Buffer Object Memory Shrinking
  289. ------------------------------
  290. This section documents the interface function for shrinking memory usage
  291. of buffer object caches. Shrinking is used to make main memory
  292. available. Note that this is mostly orthogonal to evicting buffer
  293. objects, which has the goal to make space in gpu virtual address spaces.
  294. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c
  295. :internal:
  296. Batchbuffer Parsing
  297. -------------------
  298. .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
  299. :doc: batch buffer command parser
  300. .. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c
  301. :internal:
  302. User Batchbuffer Execution
  303. --------------------------
  304. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
  305. :doc: User command execution
  306. Logical Rings, Logical Ring Contexts and Execlists
  307. --------------------------------------------------
  308. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_lrc.c
  309. :doc: Logical Rings, Logical Ring Contexts and Execlists
  310. Global GTT views
  311. ----------------
  312. .. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h
  313. :doc: Global GTT views
  314. .. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c
  315. :internal:
  316. GTT Fences and Swizzling
  317. ------------------------
  318. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
  319. :internal:
  320. Global GTT Fence Handling
  321. ~~~~~~~~~~~~~~~~~~~~~~~~~
  322. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
  323. :doc: fence register handling
  324. Hardware Tiling and Swizzling Details
  325. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  326. .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
  327. :doc: tiling swizzling details
  328. Object Tiling IOCTLs
  329. --------------------
  330. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
  331. :internal:
  332. .. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c
  333. :doc: buffer object tiling
  334. Microcontrollers
  335. ================
  336. Starting from gen9, three microcontrollers are available on the HW: the
  337. graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the
  338. display microcontroller (DMC). The driver is responsible for loading the
  339. firmwares on the microcontrollers; the GuC and HuC firmwares are transferred
  340. to WOPCM using the DMA engine, while the DMC firmware is written through MMIO.
  341. WOPCM
  342. -----
  343. WOPCM Layout
  344. ~~~~~~~~~~~~
  345. .. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c
  346. :doc: WOPCM Layout
  347. GuC
  348. ---
  349. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
  350. :doc: GuC
  351. GuC Firmware Layout
  352. ~~~~~~~~~~~~~~~~~~~
  353. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
  354. :doc: Firmware Layout
  355. GuC Memory Management
  356. ~~~~~~~~~~~~~~~~~~~~~
  357. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
  358. :doc: GuC Memory Management
  359. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
  360. :functions: intel_guc_allocate_vma
  361. GuC-specific firmware loader
  362. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  363. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
  364. :internal:
  365. GuC-based command submission
  366. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  367. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
  368. :doc: GuC-based command submission
  369. HuC
  370. ---
  371. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
  372. :doc: HuC
  373. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
  374. :functions: intel_huc_auth
  375. HuC Memory Management
  376. ~~~~~~~~~~~~~~~~~~~~~
  377. .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c
  378. :doc: HuC Memory Management
  379. HuC Firmware Layout
  380. ~~~~~~~~~~~~~~~~~~~
  381. The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_
  382. DMC
  383. ---
  384. See `CSR firmware support for DMC`_
  385. Tracing
  386. =======
  387. This sections covers all things related to the tracepoints implemented
  388. in the i915 driver.
  389. i915_ppgtt_create and i915_ppgtt_release
  390. ----------------------------------------
  391. .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
  392. :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints
  393. i915_context_create and i915_context_free
  394. -----------------------------------------
  395. .. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h
  396. :doc: i915_context_create and i915_context_free tracepoints
  397. Perf
  398. ====
  399. Overview
  400. --------
  401. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  402. :doc: i915 Perf Overview
  403. Comparison with Core Perf
  404. -------------------------
  405. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  406. :doc: i915 Perf History and Comparison with Core Perf
  407. i915 Driver Entry Points
  408. ------------------------
  409. This section covers the entrypoints exported outside of i915_perf.c to
  410. integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl.
  411. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  412. :functions: i915_perf_init
  413. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  414. :functions: i915_perf_fini
  415. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  416. :functions: i915_perf_register
  417. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  418. :functions: i915_perf_unregister
  419. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  420. :functions: i915_perf_open_ioctl
  421. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  422. :functions: i915_perf_release
  423. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  424. :functions: i915_perf_add_config_ioctl
  425. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  426. :functions: i915_perf_remove_config_ioctl
  427. i915 Perf Stream
  428. ----------------
  429. This section covers the stream-semantics-agnostic structures and functions
  430. for representing an i915 perf stream FD and associated file operations.
  431. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
  432. :functions: i915_perf_stream
  433. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
  434. :functions: i915_perf_stream_ops
  435. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  436. :functions: read_properties_unlocked
  437. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  438. :functions: i915_perf_open_ioctl_locked
  439. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  440. :functions: i915_perf_destroy_locked
  441. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  442. :functions: i915_perf_read
  443. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  444. :functions: i915_perf_ioctl
  445. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  446. :functions: i915_perf_enable_locked
  447. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  448. :functions: i915_perf_disable_locked
  449. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  450. :functions: i915_perf_poll
  451. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  452. :functions: i915_perf_poll_locked
  453. i915 Perf Observation Architecture Stream
  454. -----------------------------------------
  455. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h
  456. :functions: i915_oa_ops
  457. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  458. :functions: i915_oa_stream_init
  459. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  460. :functions: i915_oa_read
  461. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  462. :functions: i915_oa_stream_enable
  463. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  464. :functions: i915_oa_stream_disable
  465. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  466. :functions: i915_oa_wait_unlocked
  467. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  468. :functions: i915_oa_poll_wait
  469. Other i915 Perf Internals
  470. -------------------------
  471. This section simply includes all other currently documented i915 perf internals,
  472. in no particular order, but may include some more minor utilities or platform
  473. specific details than found in the more high-level sections.
  474. .. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c
  475. :internal:
  476. :no-identifiers:
  477. i915_perf_init
  478. i915_perf_fini
  479. i915_perf_register
  480. i915_perf_unregister
  481. i915_perf_open_ioctl
  482. i915_perf_release
  483. i915_perf_add_config_ioctl
  484. i915_perf_remove_config_ioctl
  485. read_properties_unlocked
  486. i915_perf_open_ioctl_locked
  487. i915_perf_destroy_locked
  488. i915_perf_read i915_perf_ioctl
  489. i915_perf_enable_locked
  490. i915_perf_disable_locked
  491. i915_perf_poll i915_perf_poll_locked
  492. i915_oa_stream_init i915_oa_read
  493. i915_oa_stream_enable
  494. i915_oa_stream_disable
  495. i915_oa_wait_unlocked
  496. i915_oa_poll_wait
  497. Style
  498. =====
  499. The drm/i915 driver codebase has some style rules in addition to (and, in some
  500. cases, deviating from) the kernel coding style.
  501. Register macro definition style
  502. -------------------------------
  503. The style guide for ``i915_reg.h``.
  504. .. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
  505. :doc: The i915 register macro definition style guide