ti-gpmc.rst 4.3 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. ========================================
  3. GPMC (General Purpose Memory Controller)
  4. ========================================
  5. GPMC is an unified memory controller dedicated to interfacing external
  6. memory devices like
  7. * Asynchronous SRAM like memories and application specific integrated
  8. circuit devices.
  9. * Asynchronous, synchronous, and page mode burst NOR flash devices
  10. NAND flash
  11. * Pseudo-SRAM devices
  12. GPMC is found on Texas Instruments SoC's (OMAP based)
  13. IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
  14. GPMC generic timing calculation:
  15. ================================
  16. GPMC has certain timings that has to be programmed for proper
  17. functioning of the peripheral, while peripheral has another set of
  18. timings. To have peripheral work with gpmc, peripheral timings has to
  19. be translated to the form gpmc can understand. The way it has to be
  20. translated depends on the connected peripheral. Also there is a
  21. dependency for certain gpmc timings on gpmc clock frequency. Hence a
  22. generic timing routine was developed to achieve above requirements.
  23. Generic routine provides a generic method to calculate gpmc timings
  24. from gpmc peripheral timings. struct gpmc_device_timings fields has to
  25. be updated with timings from the datasheet of the peripheral that is
  26. connected to gpmc. A few of the peripheral timings can be fed either
  27. in time or in cycles, provision to handle this scenario has been
  28. provided (refer struct gpmc_device_timings definition). It may so
  29. happen that timing as specified by peripheral datasheet is not present
  30. in timing structure, in this scenario, try to correlate peripheral
  31. timing to the one available. If that doesn't work, try to add a new
  32. field as required by peripheral, educate generic timing routine to
  33. handle it, make sure that it does not break any of the existing.
  34. Then there may be cases where peripheral datasheet doesn't mention
  35. certain fields of struct gpmc_device_timings, zero those entries.
  36. Generic timing routine has been verified to work properly on
  37. multiple onenand's and tusb6010 peripherals.
  38. A word of caution: generic timing routine has been developed based
  39. on understanding of gpmc timings, peripheral timings, available
  40. custom timing routines, a kind of reverse engineering without
  41. most of the datasheets & hardware (to be exact none of those supported
  42. in mainline having custom timing routine) and by simulation.
  43. gpmc timing dependency on peripheral timings:
  44. [<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]
  45. 1. common
  46. cs_on:
  47. t_ceasu
  48. adv_on:
  49. t_avdasu, t_ceavd
  50. 2. sync common
  51. sync_clk:
  52. clk
  53. page_burst_access:
  54. t_bacc
  55. clk_activation:
  56. t_ces, t_avds
  57. 3. read async muxed
  58. adv_rd_off:
  59. t_avdp_r
  60. oe_on:
  61. t_oeasu, t_aavdh
  62. access:
  63. t_iaa, t_oe, t_ce, t_aa
  64. rd_cycle:
  65. t_rd_cycle, t_cez_r, t_oez
  66. 4. read async non-muxed
  67. adv_rd_off:
  68. t_avdp_r
  69. oe_on:
  70. t_oeasu
  71. access:
  72. t_iaa, t_oe, t_ce, t_aa
  73. rd_cycle:
  74. t_rd_cycle, t_cez_r, t_oez
  75. 5. read sync muxed
  76. adv_rd_off:
  77. t_avdp_r, t_avdh
  78. oe_on:
  79. t_oeasu, t_ach, cyc_aavdh_oe
  80. access:
  81. t_iaa, cyc_iaa, cyc_oe
  82. rd_cycle:
  83. t_cez_r, t_oez, t_ce_rdyz
  84. 6. read sync non-muxed
  85. adv_rd_off:
  86. t_avdp_r
  87. oe_on:
  88. t_oeasu
  89. access:
  90. t_iaa, cyc_iaa, cyc_oe
  91. rd_cycle:
  92. t_cez_r, t_oez, t_ce_rdyz
  93. 7. write async muxed
  94. adv_wr_off:
  95. t_avdp_w
  96. we_on, wr_data_mux_bus:
  97. t_weasu, t_aavdh, cyc_aavhd_we
  98. we_off:
  99. t_wpl
  100. cs_wr_off:
  101. t_wph
  102. wr_cycle:
  103. t_cez_w, t_wr_cycle
  104. 8. write async non-muxed
  105. adv_wr_off:
  106. t_avdp_w
  107. we_on, wr_data_mux_bus:
  108. t_weasu
  109. we_off:
  110. t_wpl
  111. cs_wr_off:
  112. t_wph
  113. wr_cycle:
  114. t_cez_w, t_wr_cycle
  115. 9. write sync muxed
  116. adv_wr_off:
  117. t_avdp_w, t_avdh
  118. we_on, wr_data_mux_bus:
  119. t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we
  120. we_off:
  121. t_wpl, cyc_wpl
  122. cs_wr_off:
  123. t_wph
  124. wr_cycle:
  125. t_cez_w, t_ce_rdyz
  126. 10. write sync non-muxed
  127. adv_wr_off:
  128. t_avdp_w
  129. we_on, wr_data_mux_bus:
  130. t_weasu, t_rdyo
  131. we_off:
  132. t_wpl, cyc_wpl
  133. cs_wr_off:
  134. t_wph
  135. wr_cycle:
  136. t_cez_w, t_ce_rdyz
  137. Note:
  138. Many of gpmc timings are dependent on other gpmc timings (a few
  139. gpmc timings purely dependent on other gpmc timings, a reason that
  140. some of the gpmc timings are missing above), and it will result in
  141. indirect dependency of peripheral timings to gpmc timings other than
  142. mentioned above, refer timing routine for more details. To know what
  143. these peripheral timings correspond to, please see explanations in
  144. struct gpmc_device_timings definition. And for gpmc timings refer
  145. IP details (link above).