io_ordering.rst 2.0 KB

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  1. ==============================================
  2. Ordering I/O writes to memory-mapped addresses
  3. ==============================================
  4. On some platforms, so-called memory-mapped I/O is weakly ordered. On such
  5. platforms, driver writers are responsible for ensuring that I/O writes to
  6. memory-mapped addresses on their device arrive in the order intended. This is
  7. typically done by reading a 'safe' device or bridge register, causing the I/O
  8. chipset to flush pending writes to the device before any reads are posted. A
  9. driver would usually use this technique immediately prior to the exit of a
  10. critical section of code protected by spinlocks. This would ensure that
  11. subsequent writes to I/O space arrived only after all prior writes (much like a
  12. memory barrier op, mb(), only with respect to I/O).
  13. A more concrete example from a hypothetical device driver::
  14. ...
  15. CPU A: spin_lock_irqsave(&dev_lock, flags)
  16. CPU A: val = readl(my_status);
  17. CPU A: ...
  18. CPU A: writel(newval, ring_ptr);
  19. CPU A: spin_unlock_irqrestore(&dev_lock, flags)
  20. ...
  21. CPU B: spin_lock_irqsave(&dev_lock, flags)
  22. CPU B: val = readl(my_status);
  23. CPU B: ...
  24. CPU B: writel(newval2, ring_ptr);
  25. CPU B: spin_unlock_irqrestore(&dev_lock, flags)
  26. ...
  27. In the case above, the device may receive newval2 before it receives newval,
  28. which could cause problems. Fixing it is easy enough though::
  29. ...
  30. CPU A: spin_lock_irqsave(&dev_lock, flags)
  31. CPU A: val = readl(my_status);
  32. CPU A: ...
  33. CPU A: writel(newval, ring_ptr);
  34. CPU A: (void)readl(safe_register); /* maybe a config register? */
  35. CPU A: spin_unlock_irqrestore(&dev_lock, flags)
  36. ...
  37. CPU B: spin_lock_irqsave(&dev_lock, flags)
  38. CPU B: val = readl(my_status);
  39. CPU B: ...
  40. CPU B: writel(newval2, ring_ptr);
  41. CPU B: (void)readl(safe_register); /* maybe a config register? */
  42. CPU B: spin_unlock_irqrestore(&dev_lock, flags)
  43. Here, the reads from safe_register will cause the I/O chipset to flush any
  44. pending writes before actually posting the read to the chipset, preventing
  45. possible data corruption.