edac.rst 6.1 KB

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  1. Error Detection And Correction (EDAC) Devices
  2. =============================================
  3. Main Concepts used at the EDAC subsystem
  4. ----------------------------------------
  5. There are several things to be aware of that aren't at all obvious, like
  6. *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
  7. etc...
  8. These are some of the many terms that are thrown about that don't always
  9. mean what people think they mean (Inconceivable!). In the interest of
  10. creating a common ground for discussion, terms and their definitions
  11. will be established.
  12. * Memory devices
  13. The individual DRAM chips on a memory stick. These devices commonly
  14. output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
  15. provides the number of bits that the memory controller expects:
  16. typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
  17. * Memory Stick
  18. A printed circuit board that aggregates multiple memory devices in
  19. parallel. In general, this is the Field Replaceable Unit (FRU) which
  20. gets replaced, in the case of excessive errors. Most often it is also
  21. called DIMM (Dual Inline Memory Module).
  22. * Memory Socket
  23. A physical connector on the motherboard that accepts a single memory
  24. stick. Also called as "slot" on several datasheets.
  25. * Channel
  26. A memory controller channel, responsible to communicate with a group of
  27. DIMMs. Each channel has its own independent control (command) and data
  28. bus, and can be used independently or grouped with other channels.
  29. * Branch
  30. It is typically the highest hierarchy on a Fully-Buffered DIMM memory
  31. controller. Typically, it contains two channels. Two channels at the
  32. same branch can be used in single mode or in lockstep mode. When
  33. lockstep is enabled, the cacheline is doubled, but it generally brings
  34. some performance penalty. Also, it is generally not possible to point to
  35. just one memory stick when an error occurs, as the error correction code
  36. is calculated using two DIMMs instead of one. Due to that, it is capable
  37. of correcting more errors than on single mode.
  38. * Single-channel
  39. The data accessed by the memory controller is contained into one dimm
  40. only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
  41. one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
  42. memories. FB-DIMM and RAMBUS use a different concept for channel, so
  43. this concept doesn't apply there.
  44. * Double-channel
  45. The data size accessed by the memory controller is interlaced into two
  46. dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
  47. bits with ECC), the data flows to the CPU using a 128 bits parallel
  48. access.
  49. * Chip-select row
  50. This is the name of the DRAM signal used to select the DRAM ranks to be
  51. accessed. Common chip-select rows for single channel are 64 bits, for
  52. dual channel 128 bits. It may not be visible by the memory controller,
  53. as some DIMM types have a memory buffer that can hide direct access to
  54. it from the Memory Controller.
  55. * Single-Ranked stick
  56. A Single-ranked stick has 1 chip-select row of memory. Motherboards
  57. commonly drive two chip-select pins to a memory stick. A single-ranked
  58. stick, will occupy only one of those rows. The other will be unused.
  59. .. _doubleranked:
  60. * Double-Ranked stick
  61. A double-ranked stick has two chip-select rows which access different
  62. sets of memory devices. The two rows cannot be accessed concurrently.
  63. * Double-sided stick
  64. **DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
  65. A double-sided stick has two chip-select rows which access different sets
  66. of memory devices. The two rows cannot be accessed concurrently.
  67. "Double-sided" is irrespective of the memory devices being mounted on
  68. both sides of the memory stick.
  69. * Socket set
  70. All of the memory sticks that are required for a single memory access or
  71. all of the memory sticks spanned by a chip-select row. A single socket
  72. set has two chip-select rows and if double-sided sticks are used these
  73. will occupy those chip-select rows.
  74. * Bank
  75. This term is avoided because it is unclear when needing to distinguish
  76. between chip-select rows and socket sets.
  77. Memory Controllers
  78. ------------------
  79. Most of the EDAC core is focused on doing Memory Controller error detection.
  80. The :c:func:`edac_mc_alloc`. It uses internally the struct ``mem_ctl_info``
  81. to describe the memory controllers, with is an opaque struct for the EDAC
  82. drivers. Only the EDAC core is allowed to touch it.
  83. .. kernel-doc:: include/linux/edac.h
  84. .. kernel-doc:: drivers/edac/edac_mc.h
  85. PCI Controllers
  86. ---------------
  87. The EDAC subsystem provides a mechanism to handle PCI controllers by calling
  88. the :c:func:`edac_pci_alloc_ctl_info`. It will use the struct
  89. :c:type:`edac_pci_ctl_info` to describe the PCI controllers.
  90. .. kernel-doc:: drivers/edac/edac_pci.h
  91. EDAC Blocks
  92. -----------
  93. The EDAC subsystem also provides a generic mechanism to report errors on
  94. other parts of the hardware via :c:func:`edac_device_alloc_ctl_info` function.
  95. The structures :c:type:`edac_dev_sysfs_block_attribute`,
  96. :c:type:`edac_device_block`, :c:type:`edac_device_instance` and
  97. :c:type:`edac_device_ctl_info` provide a generic or abstract 'edac_device'
  98. representation at sysfs.
  99. This set of structures and the code that implements the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or
  100. PCI, like:
  101. - CPU caches (L1 and L2)
  102. - DMA engines
  103. - Core CPU switches
  104. - Fabric switch units
  105. - PCIe interface controllers
  106. - other EDAC/ECC type devices that can be monitored for
  107. errors, etc.
  108. It allows for a 2 level set of hierarchy.
  109. For example, a cache could be composed of L1, L2 and L3 levels of cache.
  110. Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
  111. caches. On such case, those can be represented via the following sysfs
  112. nodes::
  113. /sys/devices/system/edac/..
  114. pci/ <existing pci directory (if available)>
  115. mc/ <existing memory device directory>
  116. cpu/cpu0/.. <L1 and L2 block directory>
  117. /L1-cache/ce_count
  118. /ue_count
  119. /L2-cache/ce_count
  120. /ue_count
  121. cpu/cpu1/.. <L1 and L2 block directory>
  122. /L1-cache/ce_count
  123. /ue_count
  124. /L2-cache/ce_count
  125. /ue_count
  126. ...
  127. the L1 and L2 directories would be "edac_device_block's"
  128. .. kernel-doc:: drivers/edac/edac_device.h