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  1. ==================================
  2. DMAengine controller documentation
  3. ==================================
  4. Hardware Introduction
  5. =====================
  6. Most of the Slave DMA controllers have the same general principles of
  7. operations.
  8. They have a given number of channels to use for the DMA transfers, and
  9. a given number of requests lines.
  10. Requests and channels are pretty much orthogonal. Channels can be used
  11. to serve several to any requests. To simplify, channels are the
  12. entities that will be doing the copy, and requests what endpoints are
  13. involved.
  14. The request lines actually correspond to physical lines going from the
  15. DMA-eligible devices to the controller itself. Whenever the device
  16. will want to start a transfer, it will assert a DMA request (DRQ) by
  17. asserting that request line.
  18. A very simple DMA controller would only take into account a single
  19. parameter: the transfer size. At each clock cycle, it would transfer a
  20. byte of data from one buffer to another, until the transfer size has
  21. been reached.
  22. That wouldn't work well in the real world, since slave devices might
  23. require a specific number of bits to be transferred in a single
  24. cycle. For example, we may want to transfer as much data as the
  25. physical bus allows to maximize performances when doing a simple
  26. memory copy operation, but our audio device could have a narrower FIFO
  27. that requires data to be written exactly 16 or 24 bits at a time. This
  28. is why most if not all of the DMA controllers can adjust this, using a
  29. parameter called the transfer width.
  30. Moreover, some DMA controllers, whenever the RAM is used as a source
  31. or destination, can group the reads or writes in memory into a buffer,
  32. so instead of having a lot of small memory accesses, which is not
  33. really efficient, you'll get several bigger transfers. This is done
  34. using a parameter called the burst size, that defines how many single
  35. reads/writes it's allowed to do without the controller splitting the
  36. transfer into smaller sub-transfers.
  37. Our theoretical DMA controller would then only be able to do transfers
  38. that involve a single contiguous block of data. However, some of the
  39. transfers we usually have are not, and want to copy data from
  40. non-contiguous buffers to a contiguous buffer, which is called
  41. scatter-gather.
  42. DMAEngine, at least for mem2dev transfers, require support for
  43. scatter-gather. So we're left with two cases here: either we have a
  44. quite simple DMA controller that doesn't support it, and we'll have to
  45. implement it in software, or we have a more advanced DMA controller,
  46. that implements in hardware scatter-gather.
  47. The latter are usually programmed using a collection of chunks to
  48. transfer, and whenever the transfer is started, the controller will go
  49. over that collection, doing whatever we programmed there.
  50. This collection is usually either a table or a linked list. You will
  51. then push either the address of the table and its number of elements,
  52. or the first item of the list to one channel of the DMA controller,
  53. and whenever a DRQ will be asserted, it will go through the collection
  54. to know where to fetch the data from.
  55. Either way, the format of this collection is completely dependent on
  56. your hardware. Each DMA controller will require a different structure,
  57. but all of them will require, for every chunk, at least the source and
  58. destination addresses, whether it should increment these addresses or
  59. not and the three parameters we saw earlier: the burst size, the
  60. transfer width and the transfer size.
  61. The one last thing is that usually, slave devices won't issue DRQ by
  62. default, and you have to enable this in your slave device driver first
  63. whenever you're willing to use DMA.
  64. These were just the general memory-to-memory (also called mem2mem) or
  65. memory-to-device (mem2dev) kind of transfers. Most devices often
  66. support other kind of transfers or memory operations that dmaengine
  67. support and will be detailed later in this document.
  68. DMA Support in Linux
  69. ====================
  70. Historically, DMA controller drivers have been implemented using the
  71. async TX API, to offload operations such as memory copy, XOR,
  72. cryptography, etc., basically any memory to memory operation.
  73. Over time, the need for memory to device transfers arose, and
  74. dmaengine was extended. Nowadays, the async TX API is written as a
  75. layer on top of dmaengine, and acts as a client. Still, dmaengine
  76. accommodates that API in some cases, and made some design choices to
  77. ensure that it stayed compatible.
  78. For more information on the Async TX API, please look the relevant
  79. documentation file in Documentation/crypto/async-tx-api.rst.
  80. DMAEngine APIs
  81. ==============
  82. ``struct dma_device`` Initialization
  83. ------------------------------------
  84. Just like any other kernel framework, the whole DMAEngine registration
  85. relies on the driver filling a structure and registering against the
  86. framework. In our case, that structure is dma_device.
  87. The first thing you need to do in your driver is to allocate this
  88. structure. Any of the usual memory allocators will do, but you'll also
  89. need to initialize a few fields in there:
  90. - ``channels``: should be initialized as a list using the
  91. INIT_LIST_HEAD macro for example
  92. - ``src_addr_widths``:
  93. should contain a bitmask of the supported source transfer width
  94. - ``dst_addr_widths``:
  95. should contain a bitmask of the supported destination transfer width
  96. - ``directions``:
  97. should contain a bitmask of the supported slave directions
  98. (i.e. excluding mem2mem transfers)
  99. - ``residue_granularity``:
  100. granularity of the transfer residue reported to dma_set_residue.
  101. This can be either:
  102. - Descriptor:
  103. your device doesn't support any kind of residue
  104. reporting. The framework will only know that a particular
  105. transaction descriptor is done.
  106. - Segment:
  107. your device is able to report which chunks have been transferred
  108. - Burst:
  109. your device is able to report which burst have been transferred
  110. - ``dev``: should hold the pointer to the ``struct device`` associated
  111. to your current driver instance.
  112. Supported transaction types
  113. ---------------------------
  114. The next thing you need is to set which transaction types your device
  115. (and driver) supports.
  116. Our ``dma_device structure`` has a field called cap_mask that holds the
  117. various types of transaction supported, and you need to modify this
  118. mask using the dma_cap_set function, with various flags depending on
  119. transaction types you support as an argument.
  120. All those capabilities are defined in the ``dma_transaction_type enum``,
  121. in ``include/linux/dmaengine.h``
  122. Currently, the types available are:
  123. - DMA_MEMCPY
  124. - The device is able to do memory to memory copies
  125. - DMA_XOR
  126. - The device is able to perform XOR operations on memory areas
  127. - Used to accelerate XOR intensive tasks, such as RAID5
  128. - DMA_XOR_VAL
  129. - The device is able to perform parity check using the XOR
  130. algorithm against a memory buffer.
  131. - DMA_PQ
  132. - The device is able to perform RAID6 P+Q computations, P being a
  133. simple XOR, and Q being a Reed-Solomon algorithm.
  134. - DMA_PQ_VAL
  135. - The device is able to perform parity check using RAID6 P+Q
  136. algorithm against a memory buffer.
  137. - DMA_INTERRUPT
  138. - The device is able to trigger a dummy transfer that will
  139. generate periodic interrupts
  140. - Used by the client drivers to register a callback that will be
  141. called on a regular basis through the DMA controller interrupt
  142. - DMA_PRIVATE
  143. - The devices only supports slave transfers, and as such isn't
  144. available for async transfers.
  145. - DMA_ASYNC_TX
  146. - Must not be set by the device, and will be set by the framework
  147. if needed
  148. - TODO: What is it about?
  149. - DMA_SLAVE
  150. - The device can handle device to memory transfers, including
  151. scatter-gather transfers.
  152. - While in the mem2mem case we were having two distinct types to
  153. deal with a single chunk to copy or a collection of them, here,
  154. we just have a single transaction type that is supposed to
  155. handle both.
  156. - If you want to transfer a single contiguous memory buffer,
  157. simply build a scatter list with only one item.
  158. - DMA_CYCLIC
  159. - The device can handle cyclic transfers.
  160. - A cyclic transfer is a transfer where the chunk collection will
  161. loop over itself, with the last item pointing to the first.
  162. - It's usually used for audio transfers, where you want to operate
  163. on a single ring buffer that you will fill with your audio data.
  164. - DMA_INTERLEAVE
  165. - The device supports interleaved transfer.
  166. - These transfers can transfer data from a non-contiguous buffer
  167. to a non-contiguous buffer, opposed to DMA_SLAVE that can
  168. transfer data from a non-contiguous data set to a continuous
  169. destination buffer.
  170. - It's usually used for 2d content transfers, in which case you
  171. want to transfer a portion of uncompressed data directly to the
  172. display to print it
  173. - DMA_COMPLETION_NO_ORDER
  174. - The device does not support in order completion.
  175. - The driver should return DMA_OUT_OF_ORDER for device_tx_status if
  176. the device is setting this capability.
  177. - All cookie tracking and checking API should be treated as invalid if
  178. the device exports this capability.
  179. - At this point, this is incompatible with polling option for dmatest.
  180. - If this cap is set, the user is recommended to provide an unique
  181. identifier for each descriptor sent to the DMA device in order to
  182. properly track the completion.
  183. - DMA_REPEAT
  184. - The device supports repeated transfers. A repeated transfer, indicated by
  185. the DMA_PREP_REPEAT transfer flag, is similar to a cyclic transfer in that
  186. it gets automatically repeated when it ends, but can additionally be
  187. replaced by the client.
  188. - This feature is limited to interleaved transfers, this flag should thus not
  189. be set if the DMA_INTERLEAVE flag isn't set. This limitation is based on
  190. the current needs of DMA clients, support for additional transfer types
  191. should be added in the future if and when the need arises.
  192. - DMA_LOAD_EOT
  193. - The device supports replacing repeated transfers at end of transfer (EOT)
  194. by queuing a new transfer with the DMA_PREP_LOAD_EOT flag set.
  195. - Support for replacing a currently running transfer at another point (such
  196. as end of burst instead of end of transfer) will be added in the future
  197. based on DMA clients needs, if and when the need arises.
  198. These various types will also affect how the source and destination
  199. addresses change over time.
  200. Addresses pointing to RAM are typically incremented (or decremented)
  201. after each transfer. In case of a ring buffer, they may loop
  202. (DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO)
  203. are typically fixed.
  204. Per descriptor metadata support
  205. -------------------------------
  206. Some data movement architecture (DMA controller and peripherals) uses metadata
  207. associated with a transaction. The DMA controller role is to transfer the
  208. payload and the metadata alongside.
  209. The metadata itself is not used by the DMA engine itself, but it contains
  210. parameters, keys, vectors, etc for peripheral or from the peripheral.
  211. The DMAengine framework provides a generic ways to facilitate the metadata for
  212. descriptors. Depending on the architecture the DMA driver can implement either
  213. or both of the methods and it is up to the client driver to choose which one
  214. to use.
  215. - DESC_METADATA_CLIENT
  216. The metadata buffer is allocated/provided by the client driver and it is
  217. attached (via the dmaengine_desc_attach_metadata() helper to the descriptor.
  218. From the DMA driver the following is expected for this mode:
  219. - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM
  220. The data from the provided metadata buffer should be prepared for the DMA
  221. controller to be sent alongside of the payload data. Either by copying to a
  222. hardware descriptor, or highly coupled packet.
  223. - DMA_DEV_TO_MEM
  224. On transfer completion the DMA driver must copy the metadata to the client
  225. provided metadata buffer before notifying the client about the completion.
  226. After the transfer completion, DMA drivers must not touch the metadata
  227. buffer provided by the client.
  228. - DESC_METADATA_ENGINE
  229. The metadata buffer is allocated/managed by the DMA driver. The client driver
  230. can ask for the pointer, maximum size and the currently used size of the
  231. metadata and can directly update or read it. dmaengine_desc_get_metadata_ptr()
  232. and dmaengine_desc_set_metadata_len() is provided as helper functions.
  233. From the DMA driver the following is expected for this mode:
  234. - get_metadata_ptr()
  235. Should return a pointer for the metadata buffer, the maximum size of the
  236. metadata buffer and the currently used / valid (if any) bytes in the buffer.
  237. - set_metadata_len()
  238. It is called by the clients after it have placed the metadata to the buffer
  239. to let the DMA driver know the number of valid bytes provided.
  240. Note: since the client will ask for the metadata pointer in the completion
  241. callback (in DMA_DEV_TO_MEM case) the DMA driver must ensure that the
  242. descriptor is not freed up prior the callback is called.
  243. Device operations
  244. -----------------
  245. Our dma_device structure also requires a few function pointers in
  246. order to implement the actual logic, now that we described what
  247. operations we were able to perform.
  248. The functions that we have to fill in there, and hence have to
  249. implement, obviously depend on the transaction types you reported as
  250. supported.
  251. - ``device_alloc_chan_resources``
  252. - ``device_free_chan_resources``
  253. - These functions will be called whenever a driver will call
  254. ``dma_request_channel`` or ``dma_release_channel`` for the first/last
  255. time on the channel associated to that driver.
  256. - They are in charge of allocating/freeing all the needed
  257. resources in order for that channel to be useful for your driver.
  258. - These functions can sleep.
  259. - ``device_prep_dma_*``
  260. - These functions are matching the capabilities you registered
  261. previously.
  262. - These functions all take the buffer or the scatterlist relevant
  263. for the transfer being prepared, and should create a hardware
  264. descriptor or a list of hardware descriptors from it
  265. - These functions can be called from an interrupt context
  266. - Any allocation you might do should be using the GFP_NOWAIT
  267. flag, in order not to potentially sleep, but without depleting
  268. the emergency pool either.
  269. - Drivers should try to pre-allocate any memory they might need
  270. during the transfer setup at probe time to avoid putting to
  271. much pressure on the nowait allocator.
  272. - It should return a unique instance of the
  273. ``dma_async_tx_descriptor structure``, that further represents this
  274. particular transfer.
  275. - This structure can be initialized using the function
  276. ``dma_async_tx_descriptor_init``.
  277. - You'll also need to set two fields in this structure:
  278. - flags:
  279. TODO: Can it be modified by the driver itself, or
  280. should it be always the flags passed in the arguments
  281. - tx_submit: A pointer to a function you have to implement,
  282. that is supposed to push the current transaction descriptor to a
  283. pending queue, waiting for issue_pending to be called.
  284. - In this structure the function pointer callback_result can be
  285. initialized in order for the submitter to be notified that a
  286. transaction has completed. In the earlier code the function pointer
  287. callback has been used. However it does not provide any status to the
  288. transaction and will be deprecated. The result structure defined as
  289. ``dmaengine_result`` that is passed in to callback_result
  290. has two fields:
  291. - result: This provides the transfer result defined by
  292. ``dmaengine_tx_result``. Either success or some error condition.
  293. - residue: Provides the residue bytes of the transfer for those that
  294. support residue.
  295. - ``device_issue_pending``
  296. - Takes the first transaction descriptor in the pending queue,
  297. and starts the transfer. Whenever that transfer is done, it
  298. should move to the next transaction in the list.
  299. - This function can be called in an interrupt context
  300. - ``device_tx_status``
  301. - Should report the bytes left to go over on the given channel
  302. - Should only care about the transaction descriptor passed as
  303. argument, not the currently active one on a given channel
  304. - The tx_state argument might be NULL
  305. - Should use dma_set_residue to report it
  306. - In the case of a cyclic transfer, it should only take into
  307. account the current period.
  308. - Should return DMA_OUT_OF_ORDER if the device does not support in order
  309. completion and is completing the operation out of order.
  310. - This function can be called in an interrupt context.
  311. - device_config
  312. - Reconfigures the channel with the configuration given as argument
  313. - This command should NOT perform synchronously, or on any
  314. currently queued transfers, but only on subsequent ones
  315. - In this case, the function will receive a ``dma_slave_config``
  316. structure pointer as an argument, that will detail which
  317. configuration to use.
  318. - Even though that structure contains a direction field, this
  319. field is deprecated in favor of the direction argument given to
  320. the prep_* functions
  321. - This call is mandatory for slave operations only. This should NOT be
  322. set or expected to be set for memcpy operations.
  323. If a driver support both, it should use this call for slave
  324. operations only and not for memcpy ones.
  325. - device_pause
  326. - Pauses a transfer on the channel
  327. - This command should operate synchronously on the channel,
  328. pausing right away the work of the given channel
  329. - device_resume
  330. - Resumes a transfer on the channel
  331. - This command should operate synchronously on the channel,
  332. resuming right away the work of the given channel
  333. - device_terminate_all
  334. - Aborts all the pending and ongoing transfers on the channel
  335. - For aborted transfers the complete callback should not be called
  336. - Can be called from atomic context or from within a complete
  337. callback of a descriptor. Must not sleep. Drivers must be able
  338. to handle this correctly.
  339. - Termination may be asynchronous. The driver does not have to
  340. wait until the currently active transfer has completely stopped.
  341. See device_synchronize.
  342. - device_synchronize
  343. - Must synchronize the termination of a channel to the current
  344. context.
  345. - Must make sure that memory for previously submitted
  346. descriptors is no longer accessed by the DMA controller.
  347. - Must make sure that all complete callbacks for previously
  348. submitted descriptors have finished running and none are
  349. scheduled to run.
  350. - May sleep.
  351. Misc notes
  352. ==========
  353. (stuff that should be documented, but don't really know
  354. where to put them)
  355. ``dma_run_dependencies``
  356. - Should be called at the end of an async TX transfer, and can be
  357. ignored in the slave transfers case.
  358. - Makes sure that dependent operations are run before marking it
  359. as complete.
  360. dma_cookie_t
  361. - it's a DMA transaction ID that will increment over time.
  362. - Not really relevant any more since the introduction of ``virt-dma``
  363. that abstracts it away.
  364. DMA_CTRL_ACK
  365. - If clear, the descriptor cannot be reused by provider until the
  366. client acknowledges receipt, i.e. has a chance to establish any
  367. dependency chains
  368. - This can be acked by invoking async_tx_ack()
  369. - If set, does not mean descriptor can be reused
  370. DMA_CTRL_REUSE
  371. - If set, the descriptor can be reused after being completed. It should
  372. not be freed by provider if this flag is set.
  373. - The descriptor should be prepared for reuse by invoking
  374. ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE.
  375. - ``dmaengine_desc_set_reuse()`` will succeed only when channel support
  376. reusable descriptor as exhibited by capabilities
  377. - As a consequence, if a device driver wants to skip the
  378. ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers,
  379. because the DMA'd data wasn't used, it can resubmit the transfer right after
  380. its completion.
  381. - Descriptor can be freed in few ways
  382. - Clearing DMA_CTRL_REUSE by invoking
  383. ``dmaengine_desc_clear_reuse()`` and submitting for last txn
  384. - Explicitly invoking ``dmaengine_desc_free()``, this can succeed only
  385. when DMA_CTRL_REUSE is already set
  386. - Terminating the channel
  387. - DMA_PREP_CMD
  388. - If set, the client driver tells DMA controller that passed data in DMA
  389. API is command data.
  390. - Interpretation of command data is DMA controller specific. It can be
  391. used for issuing commands to other peripherals/register reads/register
  392. writes for which the descriptor should be in different format from
  393. normal data descriptors.
  394. - DMA_PREP_REPEAT
  395. - If set, the transfer will be automatically repeated when it ends until a
  396. new transfer is queued on the same channel with the DMA_PREP_LOAD_EOT flag.
  397. If the next transfer to be queued on the channel does not have the
  398. DMA_PREP_LOAD_EOT flag set, the current transfer will be repeated until the
  399. client terminates all transfers.
  400. - This flag is only supported if the channel reports the DMA_REPEAT
  401. capability.
  402. - DMA_PREP_LOAD_EOT
  403. - If set, the transfer will replace the transfer currently being executed at
  404. the end of the transfer.
  405. - This is the default behaviour for non-repeated transfers, specifying
  406. DMA_PREP_LOAD_EOT for non-repeated transfers will thus make no difference.
  407. - When using repeated transfers, DMA clients will usually need to set the
  408. DMA_PREP_LOAD_EOT flag on all transfers, otherwise the channel will keep
  409. repeating the last repeated transfer and ignore the new transfers being
  410. queued. Failure to set DMA_PREP_LOAD_EOT will appear as if the channel was
  411. stuck on the previous transfer.
  412. - This flag is only supported if the channel reports the DMA_LOAD_EOT
  413. capability.
  414. General Design Notes
  415. ====================
  416. Most of the DMAEngine drivers you'll see are based on a similar design
  417. that handles the end of transfer interrupts in the handler, but defer
  418. most work to a tasklet, including the start of a new transfer whenever
  419. the previous transfer ended.
  420. This is a rather inefficient design though, because the inter-transfer
  421. latency will be not only the interrupt latency, but also the
  422. scheduling latency of the tasklet, which will leave the channel idle
  423. in between, which will slow down the global transfer rate.
  424. You should avoid this kind of practice, and instead of electing a new
  425. transfer in your tasklet, move that part to the interrupt handler in
  426. order to have a shorter idle window (that we can't really avoid
  427. anyway).
  428. Glossary
  429. ========
  430. - Burst: A number of consecutive read or write operations that
  431. can be queued to buffers before being flushed to memory.
  432. - Chunk: A contiguous collection of bursts
  433. - Transfer: A collection of chunks (be it contiguous or not)