xilinx.txt 6.5 KB

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  1. d) Xilinx IP cores
  2. The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
  3. in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
  4. of standard device types (network, serial, etc.) and miscellaneous
  5. devices (gpio, LCD, spi, etc). Also, since these devices are
  6. implemented within the fpga fabric every instance of the device can be
  7. synthesised with different options that change the behaviour.
  8. Each IP-core has a set of parameters which the FPGA designer can use to
  9. control how the core is synthesized. Historically, the EDK tool would
  10. extract the device parameters relevant to device drivers and copy them
  11. into an 'xparameters.h' in the form of #define symbols. This tells the
  12. device drivers how the IP cores are configured, but it requires the kernel
  13. to be recompiled every time the FPGA bitstream is resynthesized.
  14. The new approach is to export the parameters into the device tree and
  15. generate a new device tree each time the FPGA bitstream changes. The
  16. parameters which used to be exported as #defines will now become
  17. properties of the device node. In general, device nodes for IP-cores
  18. will take the following form:
  19. (name): (generic-name)@(base-address) {
  20. compatible = "xlnx,(ip-core-name)-(HW_VER)"
  21. [, (list of compatible devices), ...];
  22. reg = <(baseaddr) (size)>;
  23. interrupt-parent = <&interrupt-controller-phandle>;
  24. interrupts = < ... >;
  25. xlnx,(parameter1) = "(string-value)";
  26. xlnx,(parameter2) = <(int-value)>;
  27. };
  28. (generic-name): an open firmware-style name that describes the
  29. generic class of device. Preferably, this is one word, such
  30. as 'serial' or 'ethernet'.
  31. (ip-core-name): the name of the ip block (given after the BEGIN
  32. directive in system.mhs). Should be in lowercase
  33. and all underscores '_' converted to dashes '-'.
  34. (name): is derived from the "PARAMETER INSTANCE" value.
  35. (parameter#): C_* parameters from system.mhs. The C_ prefix is
  36. dropped from the parameter name, the name is converted
  37. to lowercase and all underscore '_' characters are
  38. converted to dashes '-'.
  39. (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
  40. (HW_VER): from the HW_VER parameter.
  41. (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
  42. Typically, the compatible list will include the exact IP core version
  43. followed by an older IP core version which implements the same
  44. interface or any other device with the same interface.
  45. 'reg' and 'interrupts' are all optional properties.
  46. For example, the following block from system.mhs:
  47. BEGIN opb_uartlite
  48. PARAMETER INSTANCE = opb_uartlite_0
  49. PARAMETER HW_VER = 1.00.b
  50. PARAMETER C_BAUDRATE = 115200
  51. PARAMETER C_DATA_BITS = 8
  52. PARAMETER C_ODD_PARITY = 0
  53. PARAMETER C_USE_PARITY = 0
  54. PARAMETER C_CLK_FREQ = 50000000
  55. PARAMETER C_BASEADDR = 0xEC100000
  56. PARAMETER C_HIGHADDR = 0xEC10FFFF
  57. BUS_INTERFACE SOPB = opb_7
  58. PORT OPB_Clk = CLK_50MHz
  59. PORT Interrupt = opb_uartlite_0_Interrupt
  60. PORT RX = opb_uartlite_0_RX
  61. PORT TX = opb_uartlite_0_TX
  62. PORT OPB_Rst = sys_bus_reset_0
  63. END
  64. becomes the following device tree node:
  65. opb_uartlite_0: serial@ec100000 {
  66. device_type = "serial";
  67. compatible = "xlnx,opb-uartlite-1.00.b";
  68. reg = <ec100000 10000>;
  69. interrupt-parent = <&opb_intc_0>;
  70. interrupts = <1 0>; // got this from the opb_intc parameters
  71. current-speed = <d#115200>; // standard serial device prop
  72. clock-frequency = <d#50000000>; // standard serial device prop
  73. xlnx,data-bits = <8>;
  74. xlnx,odd-parity = <0>;
  75. xlnx,use-parity = <0>;
  76. };
  77. That covers the general approach to binding xilinx IP cores into the
  78. device tree. The following are bindings for specific devices:
  79. i) Xilinx ML300 Framebuffer
  80. Simple framebuffer device from the ML300 reference design (also on the
  81. ML403 reference design as well as others).
  82. Optional properties:
  83. - resolution = <xres yres> : pixel resolution of framebuffer. Some
  84. implementations use a different resolution.
  85. Default is <d#640 d#480>
  86. - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
  87. Default is <d#1024 d#480>.
  88. - rotate-display (empty) : rotate display 180 degrees.
  89. ii) Xilinx SystemACE
  90. The Xilinx SystemACE device is used to program FPGAs from an FPGA
  91. bitstream stored on a CF card. It can also be used as a generic CF
  92. interface device.
  93. Optional properties:
  94. - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
  95. iii) Xilinx EMAC and Xilinx TEMAC
  96. Xilinx Ethernet devices. In addition to general xilinx properties
  97. listed above, nodes for these devices should include a phy-handle
  98. property, and may include other common network device properties
  99. like local-mac-address.
  100. iv) Xilinx Uartlite
  101. Xilinx uartlite devices are simple fixed speed serial ports.
  102. Required properties:
  103. - current-speed : Baud rate of uartlite
  104. v) Xilinx hwicap
  105. Xilinx hwicap devices provide access to the configuration logic
  106. of the FPGA through the Internal Configuration Access Port
  107. (ICAP). The ICAP enables partial reconfiguration of the FPGA,
  108. readback of the configuration information, and some control over
  109. 'warm boots' of the FPGA fabric.
  110. Required properties:
  111. - xlnx,family : The family of the FPGA, necessary since the
  112. capabilities of the underlying ICAP hardware
  113. differ between different families. May be
  114. 'virtex2p', 'virtex4', or 'virtex5'.
  115. - compatible : should contain "xlnx,xps-hwicap-1.00.a" or
  116. "xlnx,opb-hwicap-1.00.b".
  117. vi) Xilinx Uart 16550
  118. Xilinx UART 16550 devices are very similar to the NS16550 but with
  119. different register spacing and an offset from the base address.
  120. Required properties:
  121. - clock-frequency : Frequency of the clock input
  122. - reg-offset : A value of 3 is required
  123. - reg-shift : A value of 2 is required
  124. vii) Xilinx USB Host controller
  125. The Xilinx USB host controller is EHCI compatible but with a different
  126. base address for the EHCI registers, and it is always a big-endian
  127. USB Host controller. The hardware can be configured as high speed only,
  128. or high speed/full speed hybrid.
  129. Required properties:
  130. - xlnx,support-usb-fs: A value 0 means the core is built as high speed
  131. only. A value 1 means the core also supports
  132. full speed devices.