async-tx-api.rst 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270
  1. .. SPDX-License-Identifier: GPL-2.0
  2. =====================================
  3. Asynchronous Transfers/Transforms API
  4. =====================================
  5. .. Contents
  6. 1. INTRODUCTION
  7. 2 GENEALOGY
  8. 3 USAGE
  9. 3.1 General format of the API
  10. 3.2 Supported operations
  11. 3.3 Descriptor management
  12. 3.4 When does the operation execute?
  13. 3.5 When does the operation complete?
  14. 3.6 Constraints
  15. 3.7 Example
  16. 4 DMAENGINE DRIVER DEVELOPER NOTES
  17. 4.1 Conformance points
  18. 4.2 "My application needs exclusive control of hardware channels"
  19. 5 SOURCE
  20. 1. Introduction
  21. ===============
  22. The async_tx API provides methods for describing a chain of asynchronous
  23. bulk memory transfers/transforms with support for inter-transactional
  24. dependencies. It is implemented as a dmaengine client that smooths over
  25. the details of different hardware offload engine implementations. Code
  26. that is written to the API can optimize for asynchronous operation and
  27. the API will fit the chain of operations to the available offload
  28. resources.
  29. 2.Genealogy
  30. ===========
  31. The API was initially designed to offload the memory copy and
  32. xor-parity-calculations of the md-raid5 driver using the offload engines
  33. present in the Intel(R) Xscale series of I/O processors. It also built
  34. on the 'dmaengine' layer developed for offloading memory copies in the
  35. network stack using Intel(R) I/OAT engines. The following design
  36. features surfaced as a result:
  37. 1. implicit synchronous path: users of the API do not need to know if
  38. the platform they are running on has offload capabilities. The
  39. operation will be offloaded when an engine is available and carried out
  40. in software otherwise.
  41. 2. cross channel dependency chains: the API allows a chain of dependent
  42. operations to be submitted, like xor->copy->xor in the raid5 case. The
  43. API automatically handles cases where the transition from one operation
  44. to another implies a hardware channel switch.
  45. 3. dmaengine extensions to support multiple clients and operation types
  46. beyond 'memcpy'
  47. 3. Usage
  48. ========
  49. 3.1 General format of the API
  50. -----------------------------
  51. ::
  52. struct dma_async_tx_descriptor *
  53. async_<operation>(<op specific parameters>, struct async_submit ctl *submit)
  54. 3.2 Supported operations
  55. ------------------------
  56. ======== ====================================================================
  57. memcpy memory copy between a source and a destination buffer
  58. memset fill a destination buffer with a byte value
  59. xor xor a series of source buffers and write the result to a
  60. destination buffer
  61. xor_val xor a series of source buffers and set a flag if the
  62. result is zero. The implementation attempts to prevent
  63. writes to memory
  64. pq generate the p+q (raid6 syndrome) from a series of source buffers
  65. pq_val validate that a p and or q buffer are in sync with a given series of
  66. sources
  67. datap (raid6_datap_recov) recover a raid6 data block and the p block
  68. from the given sources
  69. 2data (raid6_2data_recov) recover 2 raid6 data blocks from the given
  70. sources
  71. ======== ====================================================================
  72. 3.3 Descriptor management
  73. -------------------------
  74. The return value is non-NULL and points to a 'descriptor' when the operation
  75. has been queued to execute asynchronously. Descriptors are recycled
  76. resources, under control of the offload engine driver, to be reused as
  77. operations complete. When an application needs to submit a chain of
  78. operations it must guarantee that the descriptor is not automatically recycled
  79. before the dependency is submitted. This requires that all descriptors be
  80. acknowledged by the application before the offload engine driver is allowed to
  81. recycle (or free) the descriptor. A descriptor can be acked by one of the
  82. following methods:
  83. 1. setting the ASYNC_TX_ACK flag if no child operations are to be submitted
  84. 2. submitting an unacknowledged descriptor as a dependency to another
  85. async_tx call will implicitly set the acknowledged state.
  86. 3. calling async_tx_ack() on the descriptor.
  87. 3.4 When does the operation execute?
  88. ------------------------------------
  89. Operations do not immediately issue after return from the
  90. async_<operation> call. Offload engine drivers batch operations to
  91. improve performance by reducing the number of mmio cycles needed to
  92. manage the channel. Once a driver-specific threshold is met the driver
  93. automatically issues pending operations. An application can force this
  94. event by calling async_tx_issue_pending_all(). This operates on all
  95. channels since the application has no knowledge of channel to operation
  96. mapping.
  97. 3.5 When does the operation complete?
  98. -------------------------------------
  99. There are two methods for an application to learn about the completion
  100. of an operation.
  101. 1. Call dma_wait_for_async_tx(). This call causes the CPU to spin while
  102. it polls for the completion of the operation. It handles dependency
  103. chains and issuing pending operations.
  104. 2. Specify a completion callback. The callback routine runs in tasklet
  105. context if the offload engine driver supports interrupts, or it is
  106. called in application context if the operation is carried out
  107. synchronously in software. The callback can be set in the call to
  108. async_<operation>, or when the application needs to submit a chain of
  109. unknown length it can use the async_trigger_callback() routine to set a
  110. completion interrupt/callback at the end of the chain.
  111. 3.6 Constraints
  112. ---------------
  113. 1. Calls to async_<operation> are not permitted in IRQ context. Other
  114. contexts are permitted provided constraint #2 is not violated.
  115. 2. Completion callback routines cannot submit new operations. This
  116. results in recursion in the synchronous case and spin_locks being
  117. acquired twice in the asynchronous case.
  118. 3.7 Example
  119. -----------
  120. Perform a xor->copy->xor operation where each operation depends on the
  121. result from the previous operation::
  122. void callback(void *param)
  123. {
  124. struct completion *cmp = param;
  125. complete(cmp);
  126. }
  127. void run_xor_copy_xor(struct page **xor_srcs,
  128. int xor_src_cnt,
  129. struct page *xor_dest,
  130. size_t xor_len,
  131. struct page *copy_src,
  132. struct page *copy_dest,
  133. size_t copy_len)
  134. {
  135. struct dma_async_tx_descriptor *tx;
  136. addr_conv_t addr_conv[xor_src_cnt];
  137. struct async_submit_ctl submit;
  138. addr_conv_t addr_conv[NDISKS];
  139. struct completion cmp;
  140. init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST, NULL, NULL, NULL,
  141. addr_conv);
  142. tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit)
  143. submit->depend_tx = tx;
  144. tx = async_memcpy(copy_dest, copy_src, 0, 0, copy_len, &submit);
  145. init_completion(&cmp);
  146. init_async_submit(&submit, ASYNC_TX_XOR_DROP_DST | ASYNC_TX_ACK, tx,
  147. callback, &cmp, addr_conv);
  148. tx = async_xor(xor_dest, xor_srcs, 0, xor_src_cnt, xor_len, &submit);
  149. async_tx_issue_pending_all();
  150. wait_for_completion(&cmp);
  151. }
  152. See include/linux/async_tx.h for more information on the flags. See the
  153. ops_run_* and ops_complete_* routines in drivers/md/raid5.c for more
  154. implementation examples.
  155. 4. Driver Development Notes
  156. ===========================
  157. 4.1 Conformance points
  158. ----------------------
  159. There are a few conformance points required in dmaengine drivers to
  160. accommodate assumptions made by applications using the async_tx API:
  161. 1. Completion callbacks are expected to happen in tasklet context
  162. 2. dma_async_tx_descriptor fields are never manipulated in IRQ context
  163. 3. Use async_tx_run_dependencies() in the descriptor clean up path to
  164. handle submission of dependent operations
  165. 4.2 "My application needs exclusive control of hardware channels"
  166. -----------------------------------------------------------------
  167. Primarily this requirement arises from cases where a DMA engine driver
  168. is being used to support device-to-memory operations. A channel that is
  169. performing these operations cannot, for many platform specific reasons,
  170. be shared. For these cases the dma_request_channel() interface is
  171. provided.
  172. The interface is::
  173. struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
  174. dma_filter_fn filter_fn,
  175. void *filter_param);
  176. Where dma_filter_fn is defined as::
  177. typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
  178. When the optional 'filter_fn' parameter is set to NULL
  179. dma_request_channel simply returns the first channel that satisfies the
  180. capability mask. Otherwise, when the mask parameter is insufficient for
  181. specifying the necessary channel, the filter_fn routine can be used to
  182. disposition the available channels in the system. The filter_fn routine
  183. is called once for each free channel in the system. Upon seeing a
  184. suitable channel filter_fn returns DMA_ACK which flags that channel to
  185. be the return value from dma_request_channel. A channel allocated via
  186. this interface is exclusive to the caller, until dma_release_channel()
  187. is called.
  188. The DMA_PRIVATE capability flag is used to tag dma devices that should
  189. not be used by the general-purpose allocator. It can be set at
  190. initialization time if it is known that a channel will always be
  191. private. Alternatively, it is set when dma_request_channel() finds an
  192. unused "public" channel.
  193. A couple caveats to note when implementing a driver and consumer:
  194. 1. Once a channel has been privately allocated it will no longer be
  195. considered by the general-purpose allocator even after a call to
  196. dma_release_channel().
  197. 2. Since capabilities are specified at the device level a dma_device
  198. with multiple channels will either have all channels public, or all
  199. channels private.
  200. 5. Source
  201. ---------
  202. include/linux/dmaengine.h:
  203. core header file for DMA drivers and api users
  204. drivers/dma/dmaengine.c:
  205. offload engine channel management routines
  206. drivers/dma/:
  207. location for offload engine drivers
  208. include/linux/async_tx.h:
  209. core header file for the async_tx api
  210. crypto/async_tx/async_tx.c:
  211. async_tx interface to dmaengine and common code
  212. crypto/async_tx/async_memcpy.c:
  213. copy offload
  214. crypto/async_tx/async_xor.c:
  215. xor and xor zero sum offload