cachetlb.rst 17 KB

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  1. ==================================
  2. Cache and TLB Flushing Under Linux
  3. ==================================
  4. :Author: David S. Miller <davem@redhat.com>
  5. This document describes the cache/tlb flushing interfaces called
  6. by the Linux VM subsystem. It enumerates over each interface,
  7. describes its intended purpose, and what side effect is expected
  8. after the interface is invoked.
  9. The side effects described below are stated for a uniprocessor
  10. implementation, and what is to happen on that single processor. The
  11. SMP cases are a simple extension, in that you just extend the
  12. definition such that the side effect for a particular interface occurs
  13. on all processors in the system. Don't let this scare you into
  14. thinking SMP cache/tlb flushing must be so inefficient, this is in
  15. fact an area where many optimizations are possible. For example,
  16. if it can be proven that a user address space has never executed
  17. on a cpu (see mm_cpumask()), one need not perform a flush
  18. for this address space on that cpu.
  19. First, the TLB flushing interfaces, since they are the simplest. The
  20. "TLB" is abstracted under Linux as something the cpu uses to cache
  21. virtual-->physical address translations obtained from the software
  22. page tables. Meaning that if the software page tables change, it is
  23. possible for stale translations to exist in this "TLB" cache.
  24. Therefore when software page table changes occur, the kernel will
  25. invoke one of the following flush methods _after_ the page table
  26. changes occur:
  27. 1) ``void flush_tlb_all(void)``
  28. The most severe flush of all. After this interface runs,
  29. any previous page table modification whatsoever will be
  30. visible to the cpu.
  31. This is usually invoked when the kernel page tables are
  32. changed, since such translations are "global" in nature.
  33. 2) ``void flush_tlb_mm(struct mm_struct *mm)``
  34. This interface flushes an entire user address space from
  35. the TLB. After running, this interface must make sure that
  36. any previous page table modifications for the address space
  37. 'mm' will be visible to the cpu. That is, after running,
  38. there will be no entries in the TLB for 'mm'.
  39. This interface is used to handle whole address space
  40. page table operations such as what happens during
  41. fork, and exec.
  42. 3) ``void flush_tlb_range(struct vm_area_struct *vma,
  43. unsigned long start, unsigned long end)``
  44. Here we are flushing a specific range of (user) virtual
  45. address translations from the TLB. After running, this
  46. interface must make sure that any previous page table
  47. modifications for the address space 'vma->vm_mm' in the range
  48. 'start' to 'end-1' will be visible to the cpu. That is, after
  49. running, there will be no entries in the TLB for 'mm' for
  50. virtual addresses in the range 'start' to 'end-1'.
  51. The "vma" is the backing store being used for the region.
  52. Primarily, this is used for munmap() type operations.
  53. The interface is provided in hopes that the port can find
  54. a suitably efficient method for removing multiple page
  55. sized translations from the TLB, instead of having the kernel
  56. call flush_tlb_page (see below) for each entry which may be
  57. modified.
  58. 4) ``void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)``
  59. This time we need to remove the PAGE_SIZE sized translation
  60. from the TLB. The 'vma' is the backing structure used by
  61. Linux to keep track of mmap'd regions for a process, the
  62. address space is available via vma->vm_mm. Also, one may
  63. test (vma->vm_flags & VM_EXEC) to see if this region is
  64. executable (and thus could be in the 'instruction TLB' in
  65. split-tlb type setups).
  66. After running, this interface must make sure that any previous
  67. page table modification for address space 'vma->vm_mm' for
  68. user virtual address 'addr' will be visible to the cpu. That
  69. is, after running, there will be no entries in the TLB for
  70. 'vma->vm_mm' for virtual address 'addr'.
  71. This is used primarily during fault processing.
  72. 5) ``void update_mmu_cache(struct vm_area_struct *vma,
  73. unsigned long address, pte_t *ptep)``
  74. At the end of every page fault, this routine is invoked to
  75. tell the architecture specific code that a translation
  76. now exists at virtual address "address" for address space
  77. "vma->vm_mm", in the software page tables.
  78. A port may use this information in any way it so chooses.
  79. For example, it could use this event to pre-load TLB
  80. translations for software managed TLB configurations.
  81. The sparc64 port currently does this.
  82. Next, we have the cache flushing interfaces. In general, when Linux
  83. is changing an existing virtual-->physical mapping to a new value,
  84. the sequence will be in one of the following forms::
  85. 1) flush_cache_mm(mm);
  86. change_all_page_tables_of(mm);
  87. flush_tlb_mm(mm);
  88. 2) flush_cache_range(vma, start, end);
  89. change_range_of_page_tables(mm, start, end);
  90. flush_tlb_range(vma, start, end);
  91. 3) flush_cache_page(vma, addr, pfn);
  92. set_pte(pte_pointer, new_pte_val);
  93. flush_tlb_page(vma, addr);
  94. The cache level flush will always be first, because this allows
  95. us to properly handle systems whose caches are strict and require
  96. a virtual-->physical translation to exist for a virtual address
  97. when that virtual address is flushed from the cache. The HyperSparc
  98. cpu is one such cpu with this attribute.
  99. The cache flushing routines below need only deal with cache flushing
  100. to the extent that it is necessary for a particular cpu. Mostly,
  101. these routines must be implemented for cpus which have virtually
  102. indexed caches which must be flushed when virtual-->physical
  103. translations are changed or removed. So, for example, the physically
  104. indexed physically tagged caches of IA32 processors have no need to
  105. implement these interfaces since the caches are fully synchronized
  106. and have no dependency on translation information.
  107. Here are the routines, one by one:
  108. 1) ``void flush_cache_mm(struct mm_struct *mm)``
  109. This interface flushes an entire user address space from
  110. the caches. That is, after running, there will be no cache
  111. lines associated with 'mm'.
  112. This interface is used to handle whole address space
  113. page table operations such as what happens during exit and exec.
  114. 2) ``void flush_cache_dup_mm(struct mm_struct *mm)``
  115. This interface flushes an entire user address space from
  116. the caches. That is, after running, there will be no cache
  117. lines associated with 'mm'.
  118. This interface is used to handle whole address space
  119. page table operations such as what happens during fork.
  120. This option is separate from flush_cache_mm to allow some
  121. optimizations for VIPT caches.
  122. 3) ``void flush_cache_range(struct vm_area_struct *vma,
  123. unsigned long start, unsigned long end)``
  124. Here we are flushing a specific range of (user) virtual
  125. addresses from the cache. After running, there will be no
  126. entries in the cache for 'vma->vm_mm' for virtual addresses in
  127. the range 'start' to 'end-1'.
  128. The "vma" is the backing store being used for the region.
  129. Primarily, this is used for munmap() type operations.
  130. The interface is provided in hopes that the port can find
  131. a suitably efficient method for removing multiple page
  132. sized regions from the cache, instead of having the kernel
  133. call flush_cache_page (see below) for each entry which may be
  134. modified.
  135. 4) ``void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)``
  136. This time we need to remove a PAGE_SIZE sized range
  137. from the cache. The 'vma' is the backing structure used by
  138. Linux to keep track of mmap'd regions for a process, the
  139. address space is available via vma->vm_mm. Also, one may
  140. test (vma->vm_flags & VM_EXEC) to see if this region is
  141. executable (and thus could be in the 'instruction cache' in
  142. "Harvard" type cache layouts).
  143. The 'pfn' indicates the physical page frame (shift this value
  144. left by PAGE_SHIFT to get the physical address) that 'addr'
  145. translates to. It is this mapping which should be removed from
  146. the cache.
  147. After running, there will be no entries in the cache for
  148. 'vma->vm_mm' for virtual address 'addr' which translates
  149. to 'pfn'.
  150. This is used primarily during fault processing.
  151. 5) ``void flush_cache_kmaps(void)``
  152. This routine need only be implemented if the platform utilizes
  153. highmem. It will be called right before all of the kmaps
  154. are invalidated.
  155. After running, there will be no entries in the cache for
  156. the kernel virtual address range PKMAP_ADDR(0) to
  157. PKMAP_ADDR(LAST_PKMAP).
  158. This routing should be implemented in asm/highmem.h
  159. 6) ``void flush_cache_vmap(unsigned long start, unsigned long end)``
  160. ``void flush_cache_vunmap(unsigned long start, unsigned long end)``
  161. Here in these two interfaces we are flushing a specific range
  162. of (kernel) virtual addresses from the cache. After running,
  163. there will be no entries in the cache for the kernel address
  164. space for virtual addresses in the range 'start' to 'end-1'.
  165. The first of these two routines is invoked after map_kernel_range()
  166. has installed the page table entries. The second is invoked
  167. before unmap_kernel_range() deletes the page table entries.
  168. There exists another whole class of cpu cache issues which currently
  169. require a whole different set of interfaces to handle properly.
  170. The biggest problem is that of virtual aliasing in the data cache
  171. of a processor.
  172. Is your port susceptible to virtual aliasing in its D-cache?
  173. Well, if your D-cache is virtually indexed, is larger in size than
  174. PAGE_SIZE, and does not prevent multiple cache lines for the same
  175. physical address from existing at once, you have this problem.
  176. If your D-cache has this problem, first define asm/shmparam.h SHMLBA
  177. properly, it should essentially be the size of your virtually
  178. addressed D-cache (or if the size is variable, the largest possible
  179. size). This setting will force the SYSv IPC layer to only allow user
  180. processes to mmap shared memory at address which are a multiple of
  181. this value.
  182. .. note::
  183. This does not fix shared mmaps, check out the sparc64 port for
  184. one way to solve this (in particular SPARC_FLAG_MMAPSHARED).
  185. Next, you have to solve the D-cache aliasing issue for all
  186. other cases. Please keep in mind that fact that, for a given page
  187. mapped into some user address space, there is always at least one more
  188. mapping, that of the kernel in its linear mapping starting at
  189. PAGE_OFFSET. So immediately, once the first user maps a given
  190. physical page into its address space, by implication the D-cache
  191. aliasing problem has the potential to exist since the kernel already
  192. maps this page at its virtual address.
  193. ``void copy_user_page(void *to, void *from, unsigned long addr, struct page *page)``
  194. ``void clear_user_page(void *to, unsigned long addr, struct page *page)``
  195. These two routines store data in user anonymous or COW
  196. pages. It allows a port to efficiently avoid D-cache alias
  197. issues between userspace and the kernel.
  198. For example, a port may temporarily map 'from' and 'to' to
  199. kernel virtual addresses during the copy. The virtual address
  200. for these two pages is chosen in such a way that the kernel
  201. load/store instructions happen to virtual addresses which are
  202. of the same "color" as the user mapping of the page. Sparc64
  203. for example, uses this technique.
  204. The 'addr' parameter tells the virtual address where the
  205. user will ultimately have this page mapped, and the 'page'
  206. parameter gives a pointer to the struct page of the target.
  207. If D-cache aliasing is not an issue, these two routines may
  208. simply call memcpy/memset directly and do nothing more.
  209. ``void flush_dcache_page(struct page *page)``
  210. Any time the kernel writes to a page cache page, _OR_
  211. the kernel is about to read from a page cache page and
  212. user space shared/writable mappings of this page potentially
  213. exist, this routine is called.
  214. .. note::
  215. This routine need only be called for page cache pages
  216. which can potentially ever be mapped into the address
  217. space of a user process. So for example, VFS layer code
  218. handling vfs symlinks in the page cache need not call
  219. this interface at all.
  220. The phrase "kernel writes to a page cache page" means,
  221. specifically, that the kernel executes store instructions
  222. that dirty data in that page at the page->virtual mapping
  223. of that page. It is important to flush here to handle
  224. D-cache aliasing, to make sure these kernel stores are
  225. visible to user space mappings of that page.
  226. The corollary case is just as important, if there are users
  227. which have shared+writable mappings of this file, we must make
  228. sure that kernel reads of these pages will see the most recent
  229. stores done by the user.
  230. If D-cache aliasing is not an issue, this routine may
  231. simply be defined as a nop on that architecture.
  232. There is a bit set aside in page->flags (PG_arch_1) as
  233. "architecture private". The kernel guarantees that,
  234. for pagecache pages, it will clear this bit when such
  235. a page first enters the pagecache.
  236. This allows these interfaces to be implemented much more
  237. efficiently. It allows one to "defer" (perhaps indefinitely)
  238. the actual flush if there are currently no user processes
  239. mapping this page. See sparc64's flush_dcache_page and
  240. update_mmu_cache implementations for an example of how to go
  241. about doing this.
  242. The idea is, first at flush_dcache_page() time, if
  243. page->mapping->i_mmap is an empty tree, just mark the architecture
  244. private page flag bit. Later, in update_mmu_cache(), a check is
  245. made of this flag bit, and if set the flush is done and the flag
  246. bit is cleared.
  247. .. important::
  248. It is often important, if you defer the flush,
  249. that the actual flush occurs on the same CPU
  250. as did the cpu stores into the page to make it
  251. dirty. Again, see sparc64 for examples of how
  252. to deal with this.
  253. ``void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
  254. unsigned long user_vaddr, void *dst, void *src, int len)``
  255. ``void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
  256. unsigned long user_vaddr, void *dst, void *src, int len)``
  257. When the kernel needs to copy arbitrary data in and out
  258. of arbitrary user pages (f.e. for ptrace()) it will use
  259. these two routines.
  260. Any necessary cache flushing or other coherency operations
  261. that need to occur should happen here. If the processor's
  262. instruction cache does not snoop cpu stores, it is very
  263. likely that you will need to flush the instruction cache
  264. for copy_to_user_page().
  265. ``void flush_anon_page(struct vm_area_struct *vma, struct page *page,
  266. unsigned long vmaddr)``
  267. When the kernel needs to access the contents of an anonymous
  268. page, it calls this function (currently only
  269. get_user_pages()). Note: flush_dcache_page() deliberately
  270. doesn't work for an anonymous page. The default
  271. implementation is a nop (and should remain so for all coherent
  272. architectures). For incoherent architectures, it should flush
  273. the cache of the page at vmaddr.
  274. ``void flush_kernel_dcache_page(struct page *page)``
  275. When the kernel needs to modify a user page is has obtained
  276. with kmap, it calls this function after all modifications are
  277. complete (but before kunmapping it) to bring the underlying
  278. page up to date. It is assumed here that the user has no
  279. incoherent cached copies (i.e. the original page was obtained
  280. from a mechanism like get_user_pages()). The default
  281. implementation is a nop and should remain so on all coherent
  282. architectures. On incoherent architectures, this should flush
  283. the kernel cache for page (using page_address(page)).
  284. ``void flush_icache_range(unsigned long start, unsigned long end)``
  285. When the kernel stores into addresses that it will execute
  286. out of (eg when loading modules), this function is called.
  287. If the icache does not snoop stores then this routine will need
  288. to flush it.
  289. ``void flush_icache_page(struct vm_area_struct *vma, struct page *page)``
  290. All the functionality of flush_icache_page can be implemented in
  291. flush_dcache_page and update_mmu_cache. In the future, the hope
  292. is to remove this interface completely.
  293. The final category of APIs is for I/O to deliberately aliased address
  294. ranges inside the kernel. Such aliases are set up by use of the
  295. vmap/vmalloc API. Since kernel I/O goes via physical pages, the I/O
  296. subsystem assumes that the user mapping and kernel offset mapping are
  297. the only aliases. This isn't true for vmap aliases, so anything in
  298. the kernel trying to do I/O to vmap areas must manually manage
  299. coherency. It must do this by flushing the vmap range before doing
  300. I/O and invalidating it after the I/O returns.
  301. ``void flush_kernel_vmap_range(void *vaddr, int size)``
  302. flushes the kernel cache for a given virtual address range in
  303. the vmap area. This is to make sure that any data the kernel
  304. modified in the vmap range is made visible to the physical
  305. page. The design is to make this area safe to perform I/O on.
  306. Note that this API does *not* also flush the offset map alias
  307. of the area.
  308. ``void invalidate_kernel_vmap_range(void *vaddr, int size) invalidates``
  309. the cache for a given virtual address range in the vmap area
  310. which prevents the processor from making the cache stale by
  311. speculatively reading data while the I/O was occurring to the
  312. physical pages. This is only necessary for data reads into the
  313. vmap area.