atomic_ops.rst 23 KB

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  1. =======================================================
  2. Semantics and Behavior of Atomic and Bitmask Operations
  3. =======================================================
  4. :Author: David S. Miller
  5. This document is intended to serve as a guide to Linux port
  6. maintainers on how to implement atomic counter, bitops, and spinlock
  7. interfaces properly.
  8. Atomic Type And Operations
  9. ==========================
  10. The atomic_t type should be defined as a signed integer and
  11. the atomic_long_t type as a signed long integer. Also, they should
  12. be made opaque such that any kind of cast to a normal C integer type
  13. will fail. Something like the following should suffice::
  14. typedef struct { int counter; } atomic_t;
  15. typedef struct { long counter; } atomic_long_t;
  16. Historically, counter has been declared volatile. This is now discouraged.
  17. See :ref:`Documentation/process/volatile-considered-harmful.rst
  18. <volatile_considered_harmful>` for the complete rationale.
  19. local_t is very similar to atomic_t. If the counter is per CPU and only
  20. updated by one CPU, local_t is probably more appropriate. Please see
  21. :ref:`Documentation/core-api/local_ops.rst <local_ops>` for the semantics of
  22. local_t.
  23. The first operations to implement for atomic_t's are the initializers and
  24. plain writes. ::
  25. #define ATOMIC_INIT(i) { (i) }
  26. #define atomic_set(v, i) ((v)->counter = (i))
  27. The first macro is used in definitions, such as::
  28. static atomic_t my_counter = ATOMIC_INIT(1);
  29. The initializer is atomic in that the return values of the atomic operations
  30. are guaranteed to be correct reflecting the initialized value if the
  31. initializer is used before runtime. If the initializer is used at runtime, a
  32. proper implicit or explicit read memory barrier is needed before reading the
  33. value with atomic_read from another thread.
  34. As with all of the ``atomic_`` interfaces, replace the leading ``atomic_``
  35. with ``atomic_long_`` to operate on atomic_long_t.
  36. The second interface can be used at runtime, as in::
  37. struct foo { atomic_t counter; };
  38. ...
  39. struct foo *k;
  40. k = kmalloc(sizeof(*k), GFP_KERNEL);
  41. if (!k)
  42. return -ENOMEM;
  43. atomic_set(&k->counter, 0);
  44. The setting is atomic in that the return values of the atomic operations by
  45. all threads are guaranteed to be correct reflecting either the value that has
  46. been set with this operation or set with another operation. A proper implicit
  47. or explicit memory barrier is needed before the value set with the operation
  48. is guaranteed to be readable with atomic_read from another thread.
  49. Next, we have::
  50. #define atomic_read(v) ((v)->counter)
  51. which simply reads the counter value currently visible to the calling thread.
  52. The read is atomic in that the return value is guaranteed to be one of the
  53. values initialized or modified with the interface operations if a proper
  54. implicit or explicit memory barrier is used after possible runtime
  55. initialization by any other thread and the value is modified only with the
  56. interface operations. atomic_read does not guarantee that the runtime
  57. initialization by any other thread is visible yet, so the user of the
  58. interface must take care of that with a proper implicit or explicit memory
  59. barrier.
  60. .. warning::
  61. ``atomic_read()`` and ``atomic_set()`` DO NOT IMPLY BARRIERS!
  62. Some architectures may choose to use the volatile keyword, barriers, or
  63. inline assembly to guarantee some degree of immediacy for atomic_read()
  64. and atomic_set(). This is not uniformly guaranteed, and may change in
  65. the future, so all users of atomic_t should treat atomic_read() and
  66. atomic_set() as simple C statements that may be reordered or optimized
  67. away entirely by the compiler or processor, and explicitly invoke the
  68. appropriate compiler and/or memory barrier for each use case. Failure
  69. to do so will result in code that may suddenly break when used with
  70. different architectures or compiler optimizations, or even changes in
  71. unrelated code which changes how the compiler optimizes the section
  72. accessing atomic_t variables.
  73. Properly aligned pointers, longs, ints, and chars (and unsigned
  74. equivalents) may be atomically loaded from and stored to in the same
  75. sense as described for atomic_read() and atomic_set(). The READ_ONCE()
  76. and WRITE_ONCE() macros should be used to prevent the compiler from using
  77. optimizations that might otherwise optimize accesses out of existence on
  78. the one hand, or that might create unsolicited accesses on the other.
  79. For example consider the following code::
  80. while (a > 0)
  81. do_something();
  82. If the compiler can prove that do_something() does not store to the
  83. variable a, then the compiler is within its rights transforming this to
  84. the following::
  85. if (a > 0)
  86. for (;;)
  87. do_something();
  88. If you don't want the compiler to do this (and you probably don't), then
  89. you should use something like the following::
  90. while (READ_ONCE(a) > 0)
  91. do_something();
  92. Alternatively, you could place a barrier() call in the loop.
  93. For another example, consider the following code::
  94. tmp_a = a;
  95. do_something_with(tmp_a);
  96. do_something_else_with(tmp_a);
  97. If the compiler can prove that do_something_with() does not store to the
  98. variable a, then the compiler is within its rights to manufacture an
  99. additional load as follows::
  100. tmp_a = a;
  101. do_something_with(tmp_a);
  102. tmp_a = a;
  103. do_something_else_with(tmp_a);
  104. This could fatally confuse your code if it expected the same value
  105. to be passed to do_something_with() and do_something_else_with().
  106. The compiler would be likely to manufacture this additional load if
  107. do_something_with() was an inline function that made very heavy use
  108. of registers: reloading from variable a could save a flush to the
  109. stack and later reload. To prevent the compiler from attacking your
  110. code in this manner, write the following::
  111. tmp_a = READ_ONCE(a);
  112. do_something_with(tmp_a);
  113. do_something_else_with(tmp_a);
  114. For a final example, consider the following code, assuming that the
  115. variable a is set at boot time before the second CPU is brought online
  116. and never changed later, so that memory barriers are not needed::
  117. if (a)
  118. b = 9;
  119. else
  120. b = 42;
  121. The compiler is within its rights to manufacture an additional store
  122. by transforming the above code into the following::
  123. b = 42;
  124. if (a)
  125. b = 9;
  126. This could come as a fatal surprise to other code running concurrently
  127. that expected b to never have the value 42 if a was zero. To prevent
  128. the compiler from doing this, write something like::
  129. if (a)
  130. WRITE_ONCE(b, 9);
  131. else
  132. WRITE_ONCE(b, 42);
  133. Don't even -think- about doing this without proper use of memory barriers,
  134. locks, or atomic operations if variable a can change at runtime!
  135. .. warning::
  136. ``READ_ONCE()`` OR ``WRITE_ONCE()`` DO NOT IMPLY A BARRIER!
  137. Now, we move onto the atomic operation interfaces typically implemented with
  138. the help of assembly code. ::
  139. void atomic_add(int i, atomic_t *v);
  140. void atomic_sub(int i, atomic_t *v);
  141. void atomic_inc(atomic_t *v);
  142. void atomic_dec(atomic_t *v);
  143. These four routines add and subtract integral values to/from the given
  144. atomic_t value. The first two routines pass explicit integers by
  145. which to make the adjustment, whereas the latter two use an implicit
  146. adjustment value of "1".
  147. One very important aspect of these two routines is that they DO NOT
  148. require any explicit memory barriers. They need only perform the
  149. atomic_t counter update in an SMP safe manner.
  150. Next, we have::
  151. int atomic_inc_return(atomic_t *v);
  152. int atomic_dec_return(atomic_t *v);
  153. These routines add 1 and subtract 1, respectively, from the given
  154. atomic_t and return the new counter value after the operation is
  155. performed.
  156. Unlike the above routines, it is required that these primitives
  157. include explicit memory barriers that are performed before and after
  158. the operation. It must be done such that all memory operations before
  159. and after the atomic operation calls are strongly ordered with respect
  160. to the atomic operation itself.
  161. For example, it should behave as if a smp_mb() call existed both
  162. before and after the atomic operation.
  163. If the atomic instructions used in an implementation provide explicit
  164. memory barrier semantics which satisfy the above requirements, that is
  165. fine as well.
  166. Let's move on::
  167. int atomic_add_return(int i, atomic_t *v);
  168. int atomic_sub_return(int i, atomic_t *v);
  169. These behave just like atomic_{inc,dec}_return() except that an
  170. explicit counter adjustment is given instead of the implicit "1".
  171. This means that like atomic_{inc,dec}_return(), the memory barrier
  172. semantics are required.
  173. Next::
  174. int atomic_inc_and_test(atomic_t *v);
  175. int atomic_dec_and_test(atomic_t *v);
  176. These two routines increment and decrement by 1, respectively, the
  177. given atomic counter. They return a boolean indicating whether the
  178. resulting counter value was zero or not.
  179. Again, these primitives provide explicit memory barrier semantics around
  180. the atomic operation::
  181. int atomic_sub_and_test(int i, atomic_t *v);
  182. This is identical to atomic_dec_and_test() except that an explicit
  183. decrement is given instead of the implicit "1". This primitive must
  184. provide explicit memory barrier semantics around the operation::
  185. int atomic_add_negative(int i, atomic_t *v);
  186. The given increment is added to the given atomic counter value. A boolean
  187. is return which indicates whether the resulting counter value is negative.
  188. This primitive must provide explicit memory barrier semantics around
  189. the operation.
  190. Then::
  191. int atomic_xchg(atomic_t *v, int new);
  192. This performs an atomic exchange operation on the atomic variable v, setting
  193. the given new value. It returns the old value that the atomic variable v had
  194. just before the operation.
  195. atomic_xchg must provide explicit memory barriers around the operation. ::
  196. int atomic_cmpxchg(atomic_t *v, int old, int new);
  197. This performs an atomic compare exchange operation on the atomic value v,
  198. with the given old and new values. Like all atomic_xxx operations,
  199. atomic_cmpxchg will only satisfy its atomicity semantics as long as all
  200. other accesses of \*v are performed through atomic_xxx operations.
  201. atomic_cmpxchg must provide explicit memory barriers around the operation,
  202. although if the comparison fails then no memory ordering guarantees are
  203. required.
  204. The semantics for atomic_cmpxchg are the same as those defined for 'cas'
  205. below.
  206. Finally::
  207. int atomic_add_unless(atomic_t *v, int a, int u);
  208. If the atomic value v is not equal to u, this function adds a to v, and
  209. returns non zero. If v is equal to u then it returns zero. This is done as
  210. an atomic operation.
  211. atomic_add_unless must provide explicit memory barriers around the
  212. operation unless it fails (returns 0).
  213. atomic_inc_not_zero, equivalent to atomic_add_unless(v, 1, 0)
  214. If a caller requires memory barrier semantics around an atomic_t
  215. operation which does not return a value, a set of interfaces are
  216. defined which accomplish this::
  217. void smp_mb__before_atomic(void);
  218. void smp_mb__after_atomic(void);
  219. Preceding a non-value-returning read-modify-write atomic operation with
  220. smp_mb__before_atomic() and following it with smp_mb__after_atomic()
  221. provides the same full ordering that is provided by value-returning
  222. read-modify-write atomic operations.
  223. For example, smp_mb__before_atomic() can be used like so::
  224. obj->dead = 1;
  225. smp_mb__before_atomic();
  226. atomic_dec(&obj->ref_count);
  227. It makes sure that all memory operations preceding the atomic_dec()
  228. call are strongly ordered with respect to the atomic counter
  229. operation. In the above example, it guarantees that the assignment of
  230. "1" to obj->dead will be globally visible to other cpus before the
  231. atomic counter decrement.
  232. Without the explicit smp_mb__before_atomic() call, the
  233. implementation could legally allow the atomic counter update visible
  234. to other cpus before the "obj->dead = 1;" assignment.
  235. A missing memory barrier in the cases where they are required by the
  236. atomic_t implementation above can have disastrous results. Here is
  237. an example, which follows a pattern occurring frequently in the Linux
  238. kernel. It is the use of atomic counters to implement reference
  239. counting, and it works such that once the counter falls to zero it can
  240. be guaranteed that no other entity can be accessing the object::
  241. static void obj_list_add(struct obj *obj, struct list_head *head)
  242. {
  243. obj->active = 1;
  244. list_add(&obj->list, head);
  245. }
  246. static void obj_list_del(struct obj *obj)
  247. {
  248. list_del(&obj->list);
  249. obj->active = 0;
  250. }
  251. static void obj_destroy(struct obj *obj)
  252. {
  253. BUG_ON(obj->active);
  254. kfree(obj);
  255. }
  256. struct obj *obj_list_peek(struct list_head *head)
  257. {
  258. if (!list_empty(head)) {
  259. struct obj *obj;
  260. obj = list_entry(head->next, struct obj, list);
  261. atomic_inc(&obj->refcnt);
  262. return obj;
  263. }
  264. return NULL;
  265. }
  266. void obj_poke(void)
  267. {
  268. struct obj *obj;
  269. spin_lock(&global_list_lock);
  270. obj = obj_list_peek(&global_list);
  271. spin_unlock(&global_list_lock);
  272. if (obj) {
  273. obj->ops->poke(obj);
  274. if (atomic_dec_and_test(&obj->refcnt))
  275. obj_destroy(obj);
  276. }
  277. }
  278. void obj_timeout(struct obj *obj)
  279. {
  280. spin_lock(&global_list_lock);
  281. obj_list_del(obj);
  282. spin_unlock(&global_list_lock);
  283. if (atomic_dec_and_test(&obj->refcnt))
  284. obj_destroy(obj);
  285. }
  286. .. note::
  287. This is a simplification of the ARP queue management in the generic
  288. neighbour discover code of the networking. Olaf Kirch found a bug wrt.
  289. memory barriers in kfree_skb() that exposed the atomic_t memory barrier
  290. requirements quite clearly.
  291. Given the above scheme, it must be the case that the obj->active
  292. update done by the obj list deletion be visible to other processors
  293. before the atomic counter decrement is performed.
  294. Otherwise, the counter could fall to zero, yet obj->active would still
  295. be set, thus triggering the assertion in obj_destroy(). The error
  296. sequence looks like this::
  297. cpu 0 cpu 1
  298. obj_poke() obj_timeout()
  299. obj = obj_list_peek();
  300. ... gains ref to obj, refcnt=2
  301. obj_list_del(obj);
  302. obj->active = 0 ...
  303. ... visibility delayed ...
  304. atomic_dec_and_test()
  305. ... refcnt drops to 1 ...
  306. atomic_dec_and_test()
  307. ... refcount drops to 0 ...
  308. obj_destroy()
  309. BUG() triggers since obj->active
  310. still seen as one
  311. obj->active update visibility occurs
  312. With the memory barrier semantics required of the atomic_t operations
  313. which return values, the above sequence of memory visibility can never
  314. happen. Specifically, in the above case the atomic_dec_and_test()
  315. counter decrement would not become globally visible until the
  316. obj->active update does.
  317. As a historical note, 32-bit Sparc used to only allow usage of
  318. 24-bits of its atomic_t type. This was because it used 8 bits
  319. as a spinlock for SMP safety. Sparc32 lacked a "compare and swap"
  320. type instruction. However, 32-bit Sparc has since been moved over
  321. to a "hash table of spinlocks" scheme, that allows the full 32-bit
  322. counter to be realized. Essentially, an array of spinlocks are
  323. indexed into based upon the address of the atomic_t being operated
  324. on, and that lock protects the atomic operation. Parisc uses the
  325. same scheme.
  326. Another note is that the atomic_t operations returning values are
  327. extremely slow on an old 386.
  328. Atomic Bitmask
  329. ==============
  330. We will now cover the atomic bitmask operations. You will find that
  331. their SMP and memory barrier semantics are similar in shape and scope
  332. to the atomic_t ops above.
  333. Native atomic bit operations are defined to operate on objects aligned
  334. to the size of an "unsigned long" C data type, and are least of that
  335. size. The endianness of the bits within each "unsigned long" are the
  336. native endianness of the cpu. ::
  337. void set_bit(unsigned long nr, volatile unsigned long *addr);
  338. void clear_bit(unsigned long nr, volatile unsigned long *addr);
  339. void change_bit(unsigned long nr, volatile unsigned long *addr);
  340. These routines set, clear, and change, respectively, the bit number
  341. indicated by "nr" on the bit mask pointed to by "ADDR".
  342. They must execute atomically, yet there are no implicit memory barrier
  343. semantics required of these interfaces. ::
  344. int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
  345. int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
  346. int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
  347. Like the above, except that these routines return a boolean which
  348. indicates whether the changed bit was set _BEFORE_ the atomic bit
  349. operation.
  350. .. warning::
  351. It is incredibly important that the value be a boolean, ie. "0" or "1".
  352. Do not try to be fancy and save a few instructions by declaring the
  353. above to return "long" and just returning something like "old_val &
  354. mask" because that will not work.
  355. For one thing, this return value gets truncated to int in many code
  356. paths using these interfaces, so on 64-bit if the bit is set in the
  357. upper 32-bits then testers will never see that.
  358. One great example of where this problem crops up are the thread_info
  359. flag operations. Routines such as test_and_set_ti_thread_flag() chop
  360. the return value into an int. There are other places where things
  361. like this occur as well.
  362. These routines, like the atomic_t counter operations returning values,
  363. must provide explicit memory barrier semantics around their execution.
  364. All memory operations before the atomic bit operation call must be
  365. made visible globally before the atomic bit operation is made visible.
  366. Likewise, the atomic bit operation must be visible globally before any
  367. subsequent memory operation is made visible. For example::
  368. obj->dead = 1;
  369. if (test_and_set_bit(0, &obj->flags))
  370. /* ... */;
  371. obj->killed = 1;
  372. The implementation of test_and_set_bit() must guarantee that
  373. "obj->dead = 1;" is visible to cpus before the atomic memory operation
  374. done by test_and_set_bit() becomes visible. Likewise, the atomic
  375. memory operation done by test_and_set_bit() must become visible before
  376. "obj->killed = 1;" is visible.
  377. Finally there is the basic operation::
  378. int test_bit(unsigned long nr, __const__ volatile unsigned long *addr);
  379. Which returns a boolean indicating if bit "nr" is set in the bitmask
  380. pointed to by "addr".
  381. If explicit memory barriers are required around {set,clear}_bit() (which do
  382. not return a value, and thus does not need to provide memory barrier
  383. semantics), two interfaces are provided::
  384. void smp_mb__before_atomic(void);
  385. void smp_mb__after_atomic(void);
  386. They are used as follows, and are akin to their atomic_t operation
  387. brothers::
  388. /* All memory operations before this call will
  389. * be globally visible before the clear_bit().
  390. */
  391. smp_mb__before_atomic();
  392. clear_bit( ... );
  393. /* The clear_bit() will be visible before all
  394. * subsequent memory operations.
  395. */
  396. smp_mb__after_atomic();
  397. There are two special bitops with lock barrier semantics (acquire/release,
  398. same as spinlocks). These operate in the same way as their non-_lock/unlock
  399. postfixed variants, except that they are to provide acquire/release semantics,
  400. respectively. This means they can be used for bit_spin_trylock and
  401. bit_spin_unlock type operations without specifying any more barriers. ::
  402. int test_and_set_bit_lock(unsigned long nr, unsigned long *addr);
  403. void clear_bit_unlock(unsigned long nr, unsigned long *addr);
  404. void __clear_bit_unlock(unsigned long nr, unsigned long *addr);
  405. The __clear_bit_unlock version is non-atomic, however it still implements
  406. unlock barrier semantics. This can be useful if the lock itself is protecting
  407. the other bits in the word.
  408. Finally, there are non-atomic versions of the bitmask operations
  409. provided. They are used in contexts where some other higher-level SMP
  410. locking scheme is being used to protect the bitmask, and thus less
  411. expensive non-atomic operations may be used in the implementation.
  412. They have names similar to the above bitmask operation interfaces,
  413. except that two underscores are prefixed to the interface name. ::
  414. void __set_bit(unsigned long nr, volatile unsigned long *addr);
  415. void __clear_bit(unsigned long nr, volatile unsigned long *addr);
  416. void __change_bit(unsigned long nr, volatile unsigned long *addr);
  417. int __test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
  418. int __test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
  419. int __test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
  420. These non-atomic variants also do not require any special memory
  421. barrier semantics.
  422. The routines xchg() and cmpxchg() must provide the same exact
  423. memory-barrier semantics as the atomic and bit operations returning
  424. values.
  425. .. note::
  426. If someone wants to use xchg(), cmpxchg() and their variants,
  427. linux/atomic.h should be included rather than asm/cmpxchg.h, unless the
  428. code is in arch/* and can take care of itself.
  429. Spinlocks and rwlocks have memory barrier expectations as well.
  430. The rule to follow is simple:
  431. 1) When acquiring a lock, the implementation must make it globally
  432. visible before any subsequent memory operation.
  433. 2) When releasing a lock, the implementation must make it such that
  434. all previous memory operations are globally visible before the
  435. lock release.
  436. Which finally brings us to _atomic_dec_and_lock(). There is an
  437. architecture-neutral version implemented in lib/dec_and_lock.c,
  438. but most platforms will wish to optimize this in assembler. ::
  439. int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock);
  440. Atomically decrement the given counter, and if will drop to zero
  441. atomically acquire the given spinlock and perform the decrement
  442. of the counter to zero. If it does not drop to zero, do nothing
  443. with the spinlock.
  444. It is actually pretty simple to get the memory barrier correct.
  445. Simply satisfy the spinlock grab requirements, which is make
  446. sure the spinlock operation is globally visible before any
  447. subsequent memory operation.
  448. We can demonstrate this operation more clearly if we define
  449. an abstract atomic operation::
  450. long cas(long *mem, long old, long new);
  451. "cas" stands for "compare and swap". It atomically:
  452. 1) Compares "old" with the value currently at "mem".
  453. 2) If they are equal, "new" is written to "mem".
  454. 3) Regardless, the current value at "mem" is returned.
  455. As an example usage, here is what an atomic counter update
  456. might look like::
  457. void example_atomic_inc(long *counter)
  458. {
  459. long old, new, ret;
  460. while (1) {
  461. old = *counter;
  462. new = old + 1;
  463. ret = cas(counter, old, new);
  464. if (ret == old)
  465. break;
  466. }
  467. }
  468. Let's use cas() in order to build a pseudo-C atomic_dec_and_lock()::
  469. int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
  470. {
  471. long old, new, ret;
  472. int went_to_zero;
  473. went_to_zero = 0;
  474. while (1) {
  475. old = atomic_read(atomic);
  476. new = old - 1;
  477. if (new == 0) {
  478. went_to_zero = 1;
  479. spin_lock(lock);
  480. }
  481. ret = cas(atomic, old, new);
  482. if (ret == old)
  483. break;
  484. if (went_to_zero) {
  485. spin_unlock(lock);
  486. went_to_zero = 0;
  487. }
  488. }
  489. return went_to_zero;
  490. }
  491. Now, as far as memory barriers go, as long as spin_lock()
  492. strictly orders all subsequent memory operations (including
  493. the cas()) with respect to itself, things will be fine.
  494. Said another way, _atomic_dec_and_lock() must guarantee that
  495. a counter dropping to zero is never made visible before the
  496. spinlock being acquired.
  497. .. note::
  498. Note that this also means that for the case where the counter is not
  499. dropping to zero, there are no memory ordering requirements.