cpu-feature-registers.rst 15 KB

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  1. ===========================
  2. ARM64 CPU Feature Registers
  3. ===========================
  4. Author: Suzuki K Poulose <suzuki.poulose@arm.com>
  5. This file describes the ABI for exporting the AArch64 CPU ID/feature
  6. registers to userspace. The availability of this ABI is advertised
  7. via the HWCAP_CPUID in HWCAPs.
  8. 1. Motivation
  9. -------------
  10. The ARM architecture defines a set of feature registers, which describe
  11. the capabilities of the CPU/system. Access to these system registers is
  12. restricted from EL0 and there is no reliable way for an application to
  13. extract this information to make better decisions at runtime. There is
  14. limited information available to the application via HWCAPs, however
  15. there are some issues with their usage.
  16. a) Any change to the HWCAPs requires an update to userspace (e.g libc)
  17. to detect the new changes, which can take a long time to appear in
  18. distributions. Exposing the registers allows applications to get the
  19. information without requiring updates to the toolchains.
  20. b) Access to HWCAPs is sometimes limited (e.g prior to libc, or
  21. when ld is initialised at startup time).
  22. c) HWCAPs cannot represent non-boolean information effectively. The
  23. architecture defines a canonical format for representing features
  24. in the ID registers; this is well defined and is capable of
  25. representing all valid architecture variations.
  26. 2. Requirements
  27. ---------------
  28. a) Safety:
  29. Applications should be able to use the information provided by the
  30. infrastructure to run safely across the system. This has greater
  31. implications on a system with heterogeneous CPUs.
  32. The infrastructure exports a value that is safe across all the
  33. available CPU on the system.
  34. e.g, If at least one CPU doesn't implement CRC32 instructions, while
  35. others do, we should report that the CRC32 is not implemented.
  36. Otherwise an application could crash when scheduled on the CPU
  37. which doesn't support CRC32.
  38. b) Security:
  39. Applications should only be able to receive information that is
  40. relevant to the normal operation in userspace. Hence, some of the
  41. fields are masked out(i.e, made invisible) and their values are set to
  42. indicate the feature is 'not supported'. See Section 4 for the list
  43. of visible features. Also, the kernel may manipulate the fields
  44. based on what it supports. e.g, If FP is not supported by the
  45. kernel, the values could indicate that the FP is not available
  46. (even when the CPU provides it).
  47. c) Implementation Defined Features
  48. The infrastructure doesn't expose any register which is
  49. IMPLEMENTATION DEFINED as per ARMv8-A Architecture.
  50. d) CPU Identification:
  51. MIDR_EL1 is exposed to help identify the processor. On a
  52. heterogeneous system, this could be racy (just like getcpu()). The
  53. process could be migrated to another CPU by the time it uses the
  54. register value, unless the CPU affinity is set. Hence, there is no
  55. guarantee that the value reflects the processor that it is
  56. currently executing on. The REVIDR is not exposed due to this
  57. constraint, as REVIDR makes sense only in conjunction with the
  58. MIDR. Alternately, MIDR_EL1 and REVIDR_EL1 are exposed via sysfs
  59. at::
  60. /sys/devices/system/cpu/cpu$ID/regs/identification/
  61. \- midr
  62. \- revidr
  63. 3. Implementation
  64. --------------------
  65. The infrastructure is built on the emulation of the 'MRS' instruction.
  66. Accessing a restricted system register from an application generates an
  67. exception and ends up in SIGILL being delivered to the process.
  68. The infrastructure hooks into the exception handler and emulates the
  69. operation if the source belongs to the supported system register space.
  70. The infrastructure emulates only the following system register space::
  71. Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
  72. (See Table C5-6 'System instruction encodings for non-Debug System
  73. register accesses' in ARMv8 ARM DDI 0487A.h, for the list of
  74. registers).
  75. The following rules are applied to the value returned by the
  76. infrastructure:
  77. a) The value of an 'IMPLEMENTATION DEFINED' field is set to 0.
  78. b) The value of a reserved field is populated with the reserved
  79. value as defined by the architecture.
  80. c) The value of a 'visible' field holds the system wide safe value
  81. for the particular feature (except for MIDR_EL1, see section 4).
  82. d) All other fields (i.e, invisible fields) are set to indicate
  83. the feature is missing (as defined by the architecture).
  84. 4. List of registers with visible features
  85. -------------------------------------------
  86. 1) ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
  87. +------------------------------+---------+---------+
  88. | Name | bits | visible |
  89. +------------------------------+---------+---------+
  90. | RNDR | [63-60] | y |
  91. +------------------------------+---------+---------+
  92. | TS | [55-52] | y |
  93. +------------------------------+---------+---------+
  94. | FHM | [51-48] | y |
  95. +------------------------------+---------+---------+
  96. | DP | [47-44] | y |
  97. +------------------------------+---------+---------+
  98. | SM4 | [43-40] | y |
  99. +------------------------------+---------+---------+
  100. | SM3 | [39-36] | y |
  101. +------------------------------+---------+---------+
  102. | SHA3 | [35-32] | y |
  103. +------------------------------+---------+---------+
  104. | RDM | [31-28] | y |
  105. +------------------------------+---------+---------+
  106. | ATOMICS | [23-20] | y |
  107. +------------------------------+---------+---------+
  108. | CRC32 | [19-16] | y |
  109. +------------------------------+---------+---------+
  110. | SHA2 | [15-12] | y |
  111. +------------------------------+---------+---------+
  112. | SHA1 | [11-8] | y |
  113. +------------------------------+---------+---------+
  114. | AES | [7-4] | y |
  115. +------------------------------+---------+---------+
  116. 2) ID_AA64PFR0_EL1 - Processor Feature Register 0
  117. +------------------------------+---------+---------+
  118. | Name | bits | visible |
  119. +------------------------------+---------+---------+
  120. | DIT | [51-48] | y |
  121. +------------------------------+---------+---------+
  122. | SVE | [35-32] | y |
  123. +------------------------------+---------+---------+
  124. | GIC | [27-24] | n |
  125. +------------------------------+---------+---------+
  126. | AdvSIMD | [23-20] | y |
  127. +------------------------------+---------+---------+
  128. | FP | [19-16] | y |
  129. +------------------------------+---------+---------+
  130. | EL3 | [15-12] | n |
  131. +------------------------------+---------+---------+
  132. | EL2 | [11-8] | n |
  133. +------------------------------+---------+---------+
  134. | EL1 | [7-4] | n |
  135. +------------------------------+---------+---------+
  136. | EL0 | [3-0] | n |
  137. +------------------------------+---------+---------+
  138. 3) ID_AA64PFR1_EL1 - Processor Feature Register 1
  139. +------------------------------+---------+---------+
  140. | Name | bits | visible |
  141. +------------------------------+---------+---------+
  142. | MTE | [11-8] | y |
  143. +------------------------------+---------+---------+
  144. | SSBS | [7-4] | y |
  145. +------------------------------+---------+---------+
  146. | BT | [3-0] | y |
  147. +------------------------------+---------+---------+
  148. 4) MIDR_EL1 - Main ID Register
  149. +------------------------------+---------+---------+
  150. | Name | bits | visible |
  151. +------------------------------+---------+---------+
  152. | Implementer | [31-24] | y |
  153. +------------------------------+---------+---------+
  154. | Variant | [23-20] | y |
  155. +------------------------------+---------+---------+
  156. | Architecture | [19-16] | y |
  157. +------------------------------+---------+---------+
  158. | PartNum | [15-4] | y |
  159. +------------------------------+---------+---------+
  160. | Revision | [3-0] | y |
  161. +------------------------------+---------+---------+
  162. NOTE: The 'visible' fields of MIDR_EL1 will contain the value
  163. as available on the CPU where it is fetched and is not a system
  164. wide safe value.
  165. 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
  166. +------------------------------+---------+---------+
  167. | Name | bits | visible |
  168. +------------------------------+---------+---------+
  169. | I8MM | [55-52] | y |
  170. +------------------------------+---------+---------+
  171. | DGH | [51-48] | y |
  172. +------------------------------+---------+---------+
  173. | BF16 | [47-44] | y |
  174. +------------------------------+---------+---------+
  175. | SB | [39-36] | y |
  176. +------------------------------+---------+---------+
  177. | FRINTTS | [35-32] | y |
  178. +------------------------------+---------+---------+
  179. | GPI | [31-28] | y |
  180. +------------------------------+---------+---------+
  181. | GPA | [27-24] | y |
  182. +------------------------------+---------+---------+
  183. | LRCPC | [23-20] | y |
  184. +------------------------------+---------+---------+
  185. | FCMA | [19-16] | y |
  186. +------------------------------+---------+---------+
  187. | JSCVT | [15-12] | y |
  188. +------------------------------+---------+---------+
  189. | API | [11-8] | y |
  190. +------------------------------+---------+---------+
  191. | APA | [7-4] | y |
  192. +------------------------------+---------+---------+
  193. | DPB | [3-0] | y |
  194. +------------------------------+---------+---------+
  195. 6) ID_AA64MMFR0_EL1 - Memory model feature register 0
  196. +------------------------------+---------+---------+
  197. | Name | bits | visible |
  198. +------------------------------+---------+---------+
  199. | ECV | [63-60] | y |
  200. +------------------------------+---------+---------+
  201. 7) ID_AA64MMFR2_EL1 - Memory model feature register 2
  202. +------------------------------+---------+---------+
  203. | Name | bits | visible |
  204. +------------------------------+---------+---------+
  205. | AT | [35-32] | y |
  206. +------------------------------+---------+---------+
  207. 8) ID_AA64ZFR0_EL1 - SVE feature ID register 0
  208. +------------------------------+---------+---------+
  209. | Name | bits | visible |
  210. +------------------------------+---------+---------+
  211. | F64MM | [59-56] | y |
  212. +------------------------------+---------+---------+
  213. | F32MM | [55-52] | y |
  214. +------------------------------+---------+---------+
  215. | I8MM | [47-44] | y |
  216. +------------------------------+---------+---------+
  217. | SM4 | [43-40] | y |
  218. +------------------------------+---------+---------+
  219. | SHA3 | [35-32] | y |
  220. +------------------------------+---------+---------+
  221. | BF16 | [23-20] | y |
  222. +------------------------------+---------+---------+
  223. | BitPerm | [19-16] | y |
  224. +------------------------------+---------+---------+
  225. | AES | [7-4] | y |
  226. +------------------------------+---------+---------+
  227. | SVEVer | [3-0] | y |
  228. +------------------------------+---------+---------+
  229. 8) ID_AA64MMFR1_EL1 - Memory model feature register 1
  230. +------------------------------+---------+---------+
  231. | Name | bits | visible |
  232. +------------------------------+---------+---------+
  233. | AFP | [47-44] | y |
  234. +------------------------------+---------+---------+
  235. 9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
  236. +------------------------------+---------+---------+
  237. | Name | bits | visible |
  238. +------------------------------+---------+---------+
  239. | RPRES | [7-4] | y |
  240. +------------------------------+---------+---------+
  241. Appendix I: Example
  242. -------------------
  243. ::
  244. /*
  245. * Sample program to demonstrate the MRS emulation ABI.
  246. *
  247. * Copyright (C) 2015-2016, ARM Ltd
  248. *
  249. * Author: Suzuki K Poulose <suzuki.poulose@arm.com>
  250. *
  251. * This program is free software; you can redistribute it and/or modify
  252. * it under the terms of the GNU General Public License version 2 as
  253. * published by the Free Software Foundation.
  254. *
  255. * This program is distributed in the hope that it will be useful,
  256. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  257. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  258. * GNU General Public License for more details.
  259. * This program is free software; you can redistribute it and/or modify
  260. * it under the terms of the GNU General Public License version 2 as
  261. * published by the Free Software Foundation.
  262. *
  263. * This program is distributed in the hope that it will be useful,
  264. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  265. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  266. * GNU General Public License for more details.
  267. */
  268. #include <asm/hwcap.h>
  269. #include <stdio.h>
  270. #include <sys/auxv.h>
  271. #define get_cpu_ftr(id) ({ \
  272. unsigned long __val; \
  273. asm("mrs %0, "#id : "=r" (__val)); \
  274. printf("%-20s: 0x%016lx\n", #id, __val); \
  275. })
  276. int main(void)
  277. {
  278. if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) {
  279. fputs("CPUID registers unavailable\n", stderr);
  280. return 1;
  281. }
  282. get_cpu_ftr(ID_AA64ISAR0_EL1);
  283. get_cpu_ftr(ID_AA64ISAR1_EL1);
  284. get_cpu_ftr(ID_AA64MMFR0_EL1);
  285. get_cpu_ftr(ID_AA64MMFR1_EL1);
  286. get_cpu_ftr(ID_AA64PFR0_EL1);
  287. get_cpu_ftr(ID_AA64PFR1_EL1);
  288. get_cpu_ftr(ID_AA64DFR0_EL1);
  289. get_cpu_ftr(ID_AA64DFR1_EL1);
  290. get_cpu_ftr(MIDR_EL1);
  291. get_cpu_ftr(MPIDR_EL1);
  292. get_cpu_ftr(REVIDR_EL1);
  293. #if 0
  294. /* Unexposed register access causes SIGILL */
  295. get_cpu_ftr(ID_MMFR0_EL1);
  296. #endif
  297. return 0;
  298. }