booting.rst 12 KB

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  1. =====================
  2. Booting AArch64 Linux
  3. =====================
  4. Author: Will Deacon <will.deacon@arm.com>
  5. Date : 07 September 2012
  6. This document is based on the ARM booting document by Russell King and
  7. is relevant to all public releases of the AArch64 Linux kernel.
  8. The AArch64 exception model is made up of a number of exception levels
  9. (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
  10. counterpart. EL2 is the hypervisor level and exists only in non-secure
  11. mode. EL3 is the highest priority level and exists only in secure mode.
  12. For the purposes of this document, we will use the term `boot loader`
  13. simply to define all software that executes on the CPU(s) before control
  14. is passed to the Linux kernel. This may include secure monitor and
  15. hypervisor code, or it may just be a handful of instructions for
  16. preparing a minimal boot environment.
  17. Essentially, the boot loader should provide (as a minimum) the
  18. following:
  19. 1. Setup and initialise the RAM
  20. 2. Setup the device tree
  21. 3. Decompress the kernel image
  22. 4. Call the kernel image
  23. 1. Setup and initialise RAM
  24. ---------------------------
  25. Requirement: MANDATORY
  26. The boot loader is expected to find and initialise all RAM that the
  27. kernel will use for volatile data storage in the system. It performs
  28. this in a machine dependent manner. (It may use internal algorithms
  29. to automatically locate and size all RAM, or it may use knowledge of
  30. the RAM in the machine, or any other method the boot loader designer
  31. sees fit.)
  32. 2. Setup the device tree
  33. -------------------------
  34. Requirement: MANDATORY
  35. The device tree blob (dtb) must be placed on an 8-byte boundary and must
  36. not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
  37. using blocks of up to 2 megabytes in size, it must not be placed within
  38. any 2M region which must be mapped with any specific attributes.
  39. NOTE: versions prior to v4.2 also require that the DTB be placed within
  40. the 512 MB region starting at text_offset bytes below the kernel Image.
  41. 3. Decompress the kernel image
  42. ------------------------------
  43. Requirement: OPTIONAL
  44. The AArch64 kernel does not currently provide a decompressor and
  45. therefore requires decompression (gzip etc.) to be performed by the boot
  46. loader if a compressed Image target (e.g. Image.gz) is used. For
  47. bootloaders that do not implement this requirement, the uncompressed
  48. Image target is available instead.
  49. 4. Call the kernel image
  50. ------------------------
  51. Requirement: MANDATORY
  52. The decompressed kernel image contains a 64-byte header as follows::
  53. u32 code0; /* Executable code */
  54. u32 code1; /* Executable code */
  55. u64 text_offset; /* Image load offset, little endian */
  56. u64 image_size; /* Effective Image size, little endian */
  57. u64 flags; /* kernel flags, little endian */
  58. u64 res2 = 0; /* reserved */
  59. u64 res3 = 0; /* reserved */
  60. u64 res4 = 0; /* reserved */
  61. u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */
  62. u32 res5; /* reserved (used for PE COFF offset) */
  63. Header notes:
  64. - As of v3.17, all fields are little endian unless stated otherwise.
  65. - code0/code1 are responsible for branching to stext.
  66. - when booting through EFI, code0/code1 are initially skipped.
  67. res5 is an offset to the PE header and the PE header has the EFI
  68. entry point (efi_stub_entry). When the stub has done its work, it
  69. jumps to code0 to resume the normal boot process.
  70. - Prior to v3.17, the endianness of text_offset was not specified. In
  71. these cases image_size is zero and text_offset is 0x80000 in the
  72. endianness of the kernel. Where image_size is non-zero image_size is
  73. little-endian and must be respected. Where image_size is zero,
  74. text_offset can be assumed to be 0x80000.
  75. - The flags field (introduced in v3.17) is a little-endian 64-bit field
  76. composed as follows:
  77. ============= ===============================================================
  78. Bit 0 Kernel endianness. 1 if BE, 0 if LE.
  79. Bit 1-2 Kernel Page size.
  80. * 0 - Unspecified.
  81. * 1 - 4K
  82. * 2 - 16K
  83. * 3 - 64K
  84. Bit 3 Kernel physical placement
  85. 0
  86. 2MB aligned base should be as close as possible
  87. to the base of DRAM, since memory below it is not
  88. accessible via the linear mapping
  89. 1
  90. 2MB aligned base may be anywhere in physical
  91. memory
  92. Bits 4-63 Reserved.
  93. ============= ===============================================================
  94. - When image_size is zero, a bootloader should attempt to keep as much
  95. memory as possible free for use by the kernel immediately after the
  96. end of the kernel image. The amount of space required will vary
  97. depending on selected features, and is effectively unbound.
  98. The Image must be placed text_offset bytes from a 2MB aligned base
  99. address anywhere in usable system RAM and called there. The region
  100. between the 2 MB aligned base address and the start of the image has no
  101. special significance to the kernel, and may be used for other purposes.
  102. At least image_size bytes from the start of the image must be free for
  103. use by the kernel.
  104. NOTE: versions prior to v4.6 cannot make use of memory below the
  105. physical offset of the Image so it is recommended that the Image be
  106. placed as close as possible to the start of system RAM.
  107. If an initrd/initramfs is passed to the kernel at boot, it must reside
  108. entirely within a 1 GB aligned physical memory window of up to 32 GB in
  109. size that fully covers the kernel Image as well.
  110. Any memory described to the kernel (even that below the start of the
  111. image) which is not marked as reserved from the kernel (e.g., with a
  112. memreserve region in the device tree) will be considered as available to
  113. the kernel.
  114. Before jumping into the kernel, the following conditions must be met:
  115. - Quiesce all DMA capable devices so that memory does not get
  116. corrupted by bogus network packets or disk data. This will save
  117. you many hours of debug.
  118. - Primary CPU general-purpose register settings:
  119. - x0 = physical address of device tree blob (dtb) in system RAM.
  120. - x1 = 0 (reserved for future use)
  121. - x2 = 0 (reserved for future use)
  122. - x3 = 0 (reserved for future use)
  123. - CPU mode
  124. All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
  125. IRQ and FIQ).
  126. The CPU must be in either EL2 (RECOMMENDED in order to have access to
  127. the virtualisation extensions) or non-secure EL1.
  128. - Caches, MMUs
  129. The MMU must be off.
  130. The instruction cache may be on or off, and must not hold any stale
  131. entries corresponding to the loaded kernel image.
  132. The address range corresponding to the loaded kernel image must be
  133. cleaned to the PoC. In the presence of a system cache or other
  134. coherent masters with caches enabled, this will typically require
  135. cache maintenance by VA rather than set/way operations.
  136. System caches which respect the architected cache maintenance by VA
  137. operations must be configured and may be enabled.
  138. System caches which do not respect architected cache maintenance by VA
  139. operations (not recommended) must be configured and disabled.
  140. - Architected timers
  141. CNTFRQ must be programmed with the timer frequency and CNTVOFF must
  142. be programmed with a consistent value on all CPUs. If entering the
  143. kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
  144. available.
  145. - Coherency
  146. All CPUs to be booted by the kernel must be part of the same coherency
  147. domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
  148. initialisation to enable the receiving of maintenance operations on
  149. each CPU.
  150. - System registers
  151. All writable architected system registers at the exception level where
  152. the kernel image will be entered must be initialised by software at a
  153. higher exception level to prevent execution in an UNKNOWN state.
  154. - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
  155. executing on.
  156. - The value of SCR_EL3.FIQ must be the same as the one present at boot
  157. time whenever the kernel is executing.
  158. For systems with a GICv3 interrupt controller to be used in v3 mode:
  159. - If EL3 is present:
  160. - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
  161. - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
  162. - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
  163. all CPUs the kernel is executing on, and must stay constant
  164. for the lifetime of the kernel.
  165. - If the kernel is entered at EL1:
  166. - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
  167. - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
  168. - The DT or ACPI tables must describe a GICv3 interrupt controller.
  169. For systems with a GICv3 interrupt controller to be used in
  170. compatibility (v2) mode:
  171. - If EL3 is present:
  172. ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
  173. - If the kernel is entered at EL1:
  174. ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
  175. - The DT or ACPI tables must describe a GICv2 interrupt controller.
  176. For CPUs with pointer authentication functionality:
  177. - If EL3 is present:
  178. - SCR_EL3.APK (bit 16) must be initialised to 0b1
  179. - SCR_EL3.API (bit 17) must be initialised to 0b1
  180. - If the kernel is entered at EL1:
  181. - HCR_EL2.APK (bit 40) must be initialised to 0b1
  182. - HCR_EL2.API (bit 41) must be initialised to 0b1
  183. For CPUs with Activity Monitors Unit v1 (AMUv1) extension present:
  184. - If EL3 is present:
  185. - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
  186. - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
  187. - AMCNTENSET0_EL0 must be initialised to 0b1111
  188. - AMCNTENSET1_EL0 must be initialised to a platform specific value
  189. having 0b1 set for the corresponding bit for each of the auxiliary
  190. counters present.
  191. - If the kernel is entered at EL1:
  192. - AMCNTENSET0_EL0 must be initialised to 0b1111
  193. - AMCNTENSET1_EL0 must be initialised to a platform specific value
  194. having 0b1 set for the corresponding bit for each of the auxiliary
  195. counters present.
  196. The requirements described above for CPU mode, caches, MMUs, architected
  197. timers, coherency and system registers apply to all CPUs. All CPUs must
  198. enter the kernel in the same exception level.
  199. The boot loader is expected to enter the kernel on each CPU in the
  200. following manner:
  201. - The primary CPU must jump directly to the first instruction of the
  202. kernel image. The device tree blob passed by this CPU must contain
  203. an 'enable-method' property for each cpu node. The supported
  204. enable-methods are described below.
  205. It is expected that the bootloader will generate these device tree
  206. properties and insert them into the blob prior to kernel entry.
  207. - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
  208. property in their cpu node. This property identifies a
  209. naturally-aligned 64-bit zero-initalised memory location.
  210. These CPUs should spin outside of the kernel in a reserved area of
  211. memory (communicated to the kernel by a /memreserve/ region in the
  212. device tree) polling their cpu-release-addr location, which must be
  213. contained in the reserved region. A wfe instruction may be inserted
  214. to reduce the overhead of the busy-loop and a sev will be issued by
  215. the primary CPU. When a read of the location pointed to by the
  216. cpu-release-addr returns a non-zero value, the CPU must jump to this
  217. value. The value will be written as a single 64-bit little-endian
  218. value, so CPUs must convert the read value to their native endianness
  219. before jumping to it.
  220. - CPUs with a "psci" enable method should remain outside of
  221. the kernel (i.e. outside of the regions of memory described to the
  222. kernel in the memory node, or in a reserved area of memory described
  223. to the kernel by a /memreserve/ region in the device tree). The
  224. kernel will issue CPU_ON calls as described in ARM document number ARM
  225. DEN 0022A ("Power State Coordination Interface System Software on ARM
  226. processors") to bring CPUs into the kernel.
  227. The device tree should contain a 'psci' node, as described in
  228. Documentation/devicetree/bindings/arm/psci.yaml.
  229. - Secondary CPU general-purpose register settings
  230. - x0 = 0 (reserved for future use)
  231. - x1 = 0 (reserved for future use)
  232. - x2 = 0 (reserved for future use)
  233. - x3 = 0 (reserved for future use)