ras.rst 42 KB

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  1. .. include:: <isonum.txt>
  2. ============================================
  3. Reliability, Availability and Serviceability
  4. ============================================
  5. RAS concepts
  6. ************
  7. Reliability, Availability and Serviceability (RAS) is a concept used on
  8. servers meant to measure their robustness.
  9. Reliability
  10. is the probability that a system will produce correct outputs.
  11. * Generally measured as Mean Time Between Failures (MTBF)
  12. * Enhanced by features that help to avoid, detect and repair hardware faults
  13. Availability
  14. is the probability that a system is operational at a given time
  15. * Generally measured as a percentage of downtime per a period of time
  16. * Often uses mechanisms to detect and correct hardware faults in
  17. runtime;
  18. Serviceability (or maintainability)
  19. is the simplicity and speed with which a system can be repaired or
  20. maintained
  21. * Generally measured on Mean Time Between Repair (MTBR)
  22. Improving RAS
  23. -------------
  24. In order to reduce systems downtime, a system should be capable of detecting
  25. hardware errors, and, when possible correcting them in runtime. It should
  26. also provide mechanisms to detect hardware degradation, in order to warn
  27. the system administrator to take the action of replacing a component before
  28. it causes data loss or system downtime.
  29. Among the monitoring measures, the most usual ones include:
  30. * CPU – detect errors at instruction execution and at L1/L2/L3 caches;
  31. * Memory – add error correction logic (ECC) to detect and correct errors;
  32. * I/O – add CRC checksums for transferred data;
  33. * Storage – RAID, journal file systems, checksums,
  34. Self-Monitoring, Analysis and Reporting Technology (SMART).
  35. By monitoring the number of occurrences of error detections, it is possible
  36. to identify if the probability of hardware errors is increasing, and, on such
  37. case, do a preventive maintenance to replace a degraded component while
  38. those errors are correctable.
  39. Types of errors
  40. ---------------
  41. Most mechanisms used on modern systems use technologies like Hamming
  42. Codes that allow error correction when the number of errors on a bit packet
  43. is below a threshold. If the number of errors is above, those mechanisms
  44. can indicate with a high degree of confidence that an error happened, but
  45. they can't correct.
  46. Also, sometimes an error occur on a component that it is not used. For
  47. example, a part of the memory that it is not currently allocated.
  48. That defines some categories of errors:
  49. * **Correctable Error (CE)** - the error detection mechanism detected and
  50. corrected the error. Such errors are usually not fatal, although some
  51. Kernel mechanisms allow the system administrator to consider them as fatal.
  52. * **Uncorrected Error (UE)** - the amount of errors happened above the error
  53. correction threshold, and the system was unable to auto-correct.
  54. * **Fatal Error** - when an UE error happens on a critical component of the
  55. system (for example, a piece of the Kernel got corrupted by an UE), the
  56. only reliable way to avoid data corruption is to hang or reboot the machine.
  57. * **Non-fatal Error** - when an UE error happens on an unused component,
  58. like a CPU in power down state or an unused memory bank, the system may
  59. still run, eventually replacing the affected hardware by a hot spare,
  60. if available.
  61. Also, when an error happens on a userspace process, it is also possible to
  62. kill such process and let userspace restart it.
  63. The mechanism for handling non-fatal errors is usually complex and may
  64. require the help of some userspace application, in order to apply the
  65. policy desired by the system administrator.
  66. Identifying a bad hardware component
  67. ------------------------------------
  68. Just detecting a hardware flaw is usually not enough, as the system needs
  69. to pinpoint to the minimal replaceable unit (MRU) that should be exchanged
  70. to make the hardware reliable again.
  71. So, it requires not only error logging facilities, but also mechanisms that
  72. will translate the error message to the silkscreen or component label for
  73. the MRU.
  74. Typically, it is very complex for memory, as modern CPUs interlace memory
  75. from different memory modules, in order to provide a better performance. The
  76. DMI BIOS usually have a list of memory module labels, with can be obtained
  77. using the ``dmidecode`` tool. For example, on a desktop machine, it shows::
  78. Memory Device
  79. Total Width: 64 bits
  80. Data Width: 64 bits
  81. Size: 16384 MB
  82. Form Factor: SODIMM
  83. Set: None
  84. Locator: ChannelA-DIMM0
  85. Bank Locator: BANK 0
  86. Type: DDR4
  87. Type Detail: Synchronous
  88. Speed: 2133 MHz
  89. Rank: 2
  90. Configured Clock Speed: 2133 MHz
  91. On the above example, a DDR4 SO-DIMM memory module is located at the
  92. system's memory labeled as "BANK 0", as given by the *bank locator* field.
  93. Please notice that, on such system, the *total width* is equal to the
  94. *data width*. It means that such memory module doesn't have error
  95. detection/correction mechanisms.
  96. Unfortunately, not all systems use the same field to specify the memory
  97. bank. On this example, from an older server, ``dmidecode`` shows::
  98. Memory Device
  99. Array Handle: 0x1000
  100. Error Information Handle: Not Provided
  101. Total Width: 72 bits
  102. Data Width: 64 bits
  103. Size: 8192 MB
  104. Form Factor: DIMM
  105. Set: 1
  106. Locator: DIMM_A1
  107. Bank Locator: Not Specified
  108. Type: DDR3
  109. Type Detail: Synchronous Registered (Buffered)
  110. Speed: 1600 MHz
  111. Rank: 2
  112. Configured Clock Speed: 1600 MHz
  113. There, the DDR3 RDIMM memory module is located at the system's memory labeled
  114. as "DIMM_A1", as given by the *locator* field. Please notice that this
  115. memory module has 64 bits of *data width* and 72 bits of *total width*. So,
  116. it has 8 extra bits to be used by error detection and correction mechanisms.
  117. Such kind of memory is called Error-correcting code memory (ECC memory).
  118. To make things even worse, it is not uncommon that systems with different
  119. labels on their system's board to use exactly the same BIOS, meaning that
  120. the labels provided by the BIOS won't match the real ones.
  121. ECC memory
  122. ----------
  123. As mentioned in the previous section, ECC memory has extra bits to be
  124. used for error correction. In the above example, a memory module has
  125. 64 bits of *data width*, and 72 bits of *total width*. The extra 8
  126. bits which are used for the error detection and correction mechanisms
  127. are referred to as the *syndrome*\ [#f1]_\ [#f2]_.
  128. So, when the cpu requests the memory controller to write a word with
  129. *data width*, the memory controller calculates the *syndrome* in real time,
  130. using Hamming code, or some other error correction code, like SECDED+,
  131. producing a code with *total width* size. Such code is then written
  132. on the memory modules.
  133. At read, the *total width* bits code is converted back, using the same
  134. ECC code used on write, producing a word with *data width* and a *syndrome*.
  135. The word with *data width* is sent to the CPU, even when errors happen.
  136. The memory controller also looks at the *syndrome* in order to check if
  137. there was an error, and if the ECC code was able to fix such error.
  138. If the error was corrected, a Corrected Error (CE) happened. If not, an
  139. Uncorrected Error (UE) happened.
  140. The information about the CE/UE errors is stored on some special registers
  141. at the memory controller and can be accessed by reading such registers,
  142. either by BIOS, by some special CPUs or by Linux EDAC driver. On x86 64
  143. bit CPUs, such errors can also be retrieved via the Machine Check
  144. Architecture (MCA)\ [#f3]_.
  145. .. [#f1] Please notice that several memory controllers allow operation on a
  146. mode called "Lock-Step", where it groups two memory modules together,
  147. doing 128-bit reads/writes. That gives 16 bits for error correction, with
  148. significantly improves the error correction mechanism, at the expense
  149. that, when an error happens, there's no way to know what memory module is
  150. to blame. So, it has to blame both memory modules.
  151. .. [#f2] Some memory controllers also allow using memory in mirror mode.
  152. On such mode, the same data is written to two memory modules. At read,
  153. the system checks both memory modules, in order to check if both provide
  154. identical data. On such configuration, when an error happens, there's no
  155. way to know what memory module is to blame. So, it has to blame both
  156. memory modules (or 4 memory modules, if the system is also on Lock-step
  157. mode).
  158. .. [#f3] For more details about the Machine Check Architecture (MCA),
  159. please read Documentation/x86/x86_64/machinecheck.rst at the Kernel tree.
  160. EDAC - Error Detection And Correction
  161. *************************************
  162. .. note::
  163. "bluesmoke" was the name for this device driver subsystem when it
  164. was "out-of-tree" and maintained at http://bluesmoke.sourceforge.net.
  165. That site is mostly archaic now and can be used only for historical
  166. purposes.
  167. When the subsystem was pushed upstream for the first time, on
  168. Kernel 2.6.16, it was renamed to ``EDAC``.
  169. Purpose
  170. -------
  171. The ``edac`` kernel module's goal is to detect and report hardware errors
  172. that occur within the computer system running under linux.
  173. Memory
  174. ------
  175. Memory Correctable Errors (CE) and Uncorrectable Errors (UE) are the
  176. primary errors being harvested. These types of errors are harvested by
  177. the ``edac_mc`` device.
  178. Detecting CE events, then harvesting those events and reporting them,
  179. **can** but must not necessarily be a predictor of future UE events. With
  180. CE events only, the system can and will continue to operate as no data
  181. has been damaged yet.
  182. However, preventive maintenance and proactive part replacement of memory
  183. modules exhibiting CEs can reduce the likelihood of the dreaded UE events
  184. and system panics.
  185. Other hardware elements
  186. -----------------------
  187. A new feature for EDAC, the ``edac_device`` class of device, was added in
  188. the 2.6.23 version of the kernel.
  189. This new device type allows for non-memory type of ECC hardware detectors
  190. to have their states harvested and presented to userspace via the sysfs
  191. interface.
  192. Some architectures have ECC detectors for L1, L2 and L3 caches,
  193. along with DMA engines, fabric switches, main data path switches,
  194. interconnections, and various other hardware data paths. If the hardware
  195. reports it, then a edac_device device probably can be constructed to
  196. harvest and present that to userspace.
  197. PCI bus scanning
  198. ----------------
  199. In addition, PCI devices are scanned for PCI Bus Parity and SERR Errors
  200. in order to determine if errors are occurring during data transfers.
  201. The presence of PCI Parity errors must be examined with a grain of salt.
  202. There are several add-in adapters that do **not** follow the PCI specification
  203. with regards to Parity generation and reporting. The specification says
  204. the vendor should tie the parity status bits to 0 if they do not intend
  205. to generate parity. Some vendors do not do this, and thus the parity bit
  206. can "float" giving false positives.
  207. There is a PCI device attribute located in sysfs that is checked by
  208. the EDAC PCI scanning code. If that attribute is set, PCI parity/error
  209. scanning is skipped for that device. The attribute is::
  210. broken_parity_status
  211. and is located in ``/sys/devices/pci<XXX>/0000:XX:YY.Z`` directories for
  212. PCI devices.
  213. Versioning
  214. ----------
  215. EDAC is composed of a "core" module (``edac_core.ko``) and several Memory
  216. Controller (MC) driver modules. On a given system, the CORE is loaded
  217. and one MC driver will be loaded. Both the CORE and the MC driver (or
  218. ``edac_device`` driver) have individual versions that reflect current
  219. release level of their respective modules.
  220. Thus, to "report" on what version a system is running, one must report
  221. both the CORE's and the MC driver's versions.
  222. Loading
  223. -------
  224. If ``edac`` was statically linked with the kernel then no loading
  225. is necessary. If ``edac`` was built as modules then simply modprobe
  226. the ``edac`` pieces that you need. You should be able to modprobe
  227. hardware-specific modules and have the dependencies load the necessary
  228. core modules.
  229. Example::
  230. $ modprobe amd76x_edac
  231. loads both the ``amd76x_edac.ko`` memory controller module and the
  232. ``edac_mc.ko`` core module.
  233. Sysfs interface
  234. ---------------
  235. EDAC presents a ``sysfs`` interface for control and reporting purposes. It
  236. lives in the /sys/devices/system/edac directory.
  237. Within this directory there currently reside 2 components:
  238. ======= ==============================
  239. mc memory controller(s) system
  240. pci PCI control and status system
  241. ======= ==============================
  242. Memory Controller (mc) Model
  243. ----------------------------
  244. Each ``mc`` device controls a set of memory modules [#f4]_. These modules
  245. are laid out in a Chip-Select Row (``csrowX``) and Channel table (``chX``).
  246. There can be multiple csrows and multiple channels.
  247. .. [#f4] Nowadays, the term DIMM (Dual In-line Memory Module) is widely
  248. used to refer to a memory module, although there are other memory
  249. packaging alternatives, like SO-DIMM, SIMM, etc. The UEFI
  250. specification (Version 2.7) defines a memory module in the Common
  251. Platform Error Record (CPER) section to be an SMBIOS Memory Device
  252. (Type 17). Along this document, and inside the EDAC subsystem, the term
  253. "dimm" is used for all memory modules, even when they use a
  254. different kind of packaging.
  255. Memory controllers allow for several csrows, with 8 csrows being a
  256. typical value. Yet, the actual number of csrows depends on the layout of
  257. a given motherboard, memory controller and memory module characteristics.
  258. Dual channels allow for dual data length (e. g. 128 bits, on 64 bit systems)
  259. data transfers to/from the CPU from/to memory. Some newer chipsets allow
  260. for more than 2 channels, like Fully Buffered DIMMs (FB-DIMMs) memory
  261. controllers. The following example will assume 2 channels:
  262. +------------+-----------------------+
  263. | CS Rows | Channels |
  264. +------------+-----------+-----------+
  265. | | ``ch0`` | ``ch1`` |
  266. +============+===========+===========+
  267. | |**DIMM_A0**|**DIMM_B0**|
  268. +------------+-----------+-----------+
  269. | ``csrow0`` | rank0 | rank0 |
  270. +------------+-----------+-----------+
  271. | ``csrow1`` | rank1 | rank1 |
  272. +------------+-----------+-----------+
  273. | |**DIMM_A1**|**DIMM_B1**|
  274. +------------+-----------+-----------+
  275. | ``csrow2`` | rank0 | rank0 |
  276. +------------+-----------+-----------+
  277. | ``csrow3`` | rank1 | rank1 |
  278. +------------+-----------+-----------+
  279. In the above example, there are 4 physical slots on the motherboard
  280. for memory DIMMs:
  281. +---------+---------+
  282. | DIMM_A0 | DIMM_B0 |
  283. +---------+---------+
  284. | DIMM_A1 | DIMM_B1 |
  285. +---------+---------+
  286. Labels for these slots are usually silk-screened on the motherboard.
  287. Slots labeled ``A`` are channel 0 in this example. Slots labeled ``B`` are
  288. channel 1. Notice that there are two csrows possible on a physical DIMM.
  289. These csrows are allocated their csrow assignment based on the slot into
  290. which the memory DIMM is placed. Thus, when 1 DIMM is placed in each
  291. Channel, the csrows cross both DIMMs.
  292. Memory DIMMs come single or dual "ranked". A rank is a populated csrow.
  293. In the example above 2 dual ranked DIMMs are similarly placed. Thus,
  294. both csrow0 and csrow1 are populated. On the other hand, when 2 single
  295. ranked DIMMs are placed in slots DIMM_A0 and DIMM_B0, then they will
  296. have just one csrow (csrow0) and csrow1 will be empty. The pattern
  297. repeats itself for csrow2 and csrow3. Also note that some memory
  298. controllers don't have any logic to identify the memory module, see
  299. ``rankX`` directories below.
  300. The representation of the above is reflected in the directory
  301. tree in EDAC's sysfs interface. Starting in directory
  302. ``/sys/devices/system/edac/mc``, each memory controller will be
  303. represented by its own ``mcX`` directory, where ``X`` is the
  304. index of the MC::
  305. ..../edac/mc/
  306. |
  307. |->mc0
  308. |->mc1
  309. |->mc2
  310. ....
  311. Under each ``mcX`` directory each ``csrowX`` is again represented by a
  312. ``csrowX``, where ``X`` is the csrow index::
  313. .../mc/mc0/
  314. |
  315. |->csrow0
  316. |->csrow2
  317. |->csrow3
  318. ....
  319. Notice that there is no csrow1, which indicates that csrow0 is composed
  320. of a single ranked DIMMs. This should also apply in both Channels, in
  321. order to have dual-channel mode be operational. Since both csrow2 and
  322. csrow3 are populated, this indicates a dual ranked set of DIMMs for
  323. channels 0 and 1.
  324. Within each of the ``mcX`` and ``csrowX`` directories are several EDAC
  325. control and attribute files.
  326. ``mcX`` directories
  327. -------------------
  328. In ``mcX`` directories are EDAC control and attribute files for
  329. this ``X`` instance of the memory controllers.
  330. For a description of the sysfs API, please see:
  331. Documentation/ABI/testing/sysfs-devices-edac
  332. ``dimmX`` or ``rankX`` directories
  333. ----------------------------------
  334. The recommended way to use the EDAC subsystem is to look at the information
  335. provided by the ``dimmX`` or ``rankX`` directories [#f5]_.
  336. A typical EDAC system has the following structure under
  337. ``/sys/devices/system/edac/``\ [#f6]_::
  338. /sys/devices/system/edac/
  339. ├── mc
  340. │   ├── mc0
  341. │   │   ├── ce_count
  342. │   │   ├── ce_noinfo_count
  343. │   │   ├── dimm0
  344. │   │   │   ├── dimm_ce_count
  345. │   │   │   ├── dimm_dev_type
  346. │   │   │   ├── dimm_edac_mode
  347. │   │   │   ├── dimm_label
  348. │   │   │   ├── dimm_location
  349. │   │   │   ├── dimm_mem_type
  350. │   │   │   ├── dimm_ue_count
  351. │   │   │   ├── size
  352. │   │   │   └── uevent
  353. │   │   ├── max_location
  354. │   │   ├── mc_name
  355. │   │   ├── reset_counters
  356. │   │   ├── seconds_since_reset
  357. │   │   ├── size_mb
  358. │   │   ├── ue_count
  359. │   │   ├── ue_noinfo_count
  360. │   │   └── uevent
  361. │   ├── mc1
  362. │   │   ├── ce_count
  363. │   │   ├── ce_noinfo_count
  364. │   │   ├── dimm0
  365. │   │   │   ├── dimm_ce_count
  366. │   │   │   ├── dimm_dev_type
  367. │   │   │   ├── dimm_edac_mode
  368. │   │   │   ├── dimm_label
  369. │   │   │   ├── dimm_location
  370. │   │   │   ├── dimm_mem_type
  371. │   │   │   ├── dimm_ue_count
  372. │   │   │   ├── size
  373. │   │   │   └── uevent
  374. │   │   ├── max_location
  375. │   │   ├── mc_name
  376. │   │   ├── reset_counters
  377. │   │   ├── seconds_since_reset
  378. │   │   ├── size_mb
  379. │   │   ├── ue_count
  380. │   │   ├── ue_noinfo_count
  381. │   │   └── uevent
  382. │   └── uevent
  383. └── uevent
  384. In the ``dimmX`` directories are EDAC control and attribute files for
  385. this ``X`` memory module:
  386. - ``size`` - Total memory managed by this csrow attribute file
  387. This attribute file displays, in count of megabytes, the memory
  388. that this csrow contains.
  389. - ``dimm_ue_count`` - Uncorrectable Errors count attribute file
  390. This attribute file displays the total count of uncorrectable
  391. errors that have occurred on this DIMM. If panic_on_ue is set
  392. this counter will not have a chance to increment, since EDAC
  393. will panic the system.
  394. - ``dimm_ce_count`` - Correctable Errors count attribute file
  395. This attribute file displays the total count of correctable
  396. errors that have occurred on this DIMM. This count is very
  397. important to examine. CEs provide early indications that a
  398. DIMM is beginning to fail. This count field should be
  399. monitored for non-zero values and report such information
  400. to the system administrator.
  401. - ``dimm_dev_type`` - Device type attribute file
  402. This attribute file will display what type of DRAM device is
  403. being utilized on this DIMM.
  404. Examples:
  405. - x1
  406. - x2
  407. - x4
  408. - x8
  409. - ``dimm_edac_mode`` - EDAC Mode of operation attribute file
  410. This attribute file will display what type of Error detection
  411. and correction is being utilized.
  412. - ``dimm_label`` - memory module label control file
  413. This control file allows this DIMM to have a label assigned
  414. to it. With this label in the module, when errors occur
  415. the output can provide the DIMM label in the system log.
  416. This becomes vital for panic events to isolate the
  417. cause of the UE event.
  418. DIMM Labels must be assigned after booting, with information
  419. that correctly identifies the physical slot with its
  420. silk screen label. This information is currently very
  421. motherboard specific and determination of this information
  422. must occur in userland at this time.
  423. - ``dimm_location`` - location of the memory module
  424. The location can have up to 3 levels, and describe how the
  425. memory controller identifies the location of a memory module.
  426. Depending on the type of memory and memory controller, it
  427. can be:
  428. - *csrow* and *channel* - used when the memory controller
  429. doesn't identify a single DIMM - e. g. in ``rankX`` dir;
  430. - *branch*, *channel*, *slot* - typically used on FB-DIMM memory
  431. controllers;
  432. - *channel*, *slot* - used on Nehalem and newer Intel drivers.
  433. - ``dimm_mem_type`` - Memory Type attribute file
  434. This attribute file will display what type of memory is currently
  435. on this csrow. Normally, either buffered or unbuffered memory.
  436. Examples:
  437. - Registered-DDR
  438. - Unbuffered-DDR
  439. .. [#f5] On some systems, the memory controller doesn't have any logic
  440. to identify the memory module. On such systems, the directory is called ``rankX`` and works on a similar way as the ``csrowX`` directories.
  441. On modern Intel memory controllers, the memory controller identifies the
  442. memory modules directly. On such systems, the directory is called ``dimmX``.
  443. .. [#f6] There are also some ``power`` directories and ``subsystem``
  444. symlinks inside the sysfs mapping that are automatically created by
  445. the sysfs subsystem. Currently, they serve no purpose.
  446. ``csrowX`` directories
  447. ----------------------
  448. When CONFIG_EDAC_LEGACY_SYSFS is enabled, sysfs will contain the ``csrowX``
  449. directories. As this API doesn't work properly for Rambus, FB-DIMMs and
  450. modern Intel Memory Controllers, this is being deprecated in favor of
  451. ``dimmX`` directories.
  452. In the ``csrowX`` directories are EDAC control and attribute files for
  453. this ``X`` instance of csrow:
  454. - ``ue_count`` - Total Uncorrectable Errors count attribute file
  455. This attribute file displays the total count of uncorrectable
  456. errors that have occurred on this csrow. If panic_on_ue is set
  457. this counter will not have a chance to increment, since EDAC
  458. will panic the system.
  459. - ``ce_count`` - Total Correctable Errors count attribute file
  460. This attribute file displays the total count of correctable
  461. errors that have occurred on this csrow. This count is very
  462. important to examine. CEs provide early indications that a
  463. DIMM is beginning to fail. This count field should be
  464. monitored for non-zero values and report such information
  465. to the system administrator.
  466. - ``size_mb`` - Total memory managed by this csrow attribute file
  467. This attribute file displays, in count of megabytes, the memory
  468. that this csrow contains.
  469. - ``mem_type`` - Memory Type attribute file
  470. This attribute file will display what type of memory is currently
  471. on this csrow. Normally, either buffered or unbuffered memory.
  472. Examples:
  473. - Registered-DDR
  474. - Unbuffered-DDR
  475. - ``edac_mode`` - EDAC Mode of operation attribute file
  476. This attribute file will display what type of Error detection
  477. and correction is being utilized.
  478. - ``dev_type`` - Device type attribute file
  479. This attribute file will display what type of DRAM device is
  480. being utilized on this DIMM.
  481. Examples:
  482. - x1
  483. - x2
  484. - x4
  485. - x8
  486. - ``ch0_ce_count`` - Channel 0 CE Count attribute file
  487. This attribute file will display the count of CEs on this
  488. DIMM located in channel 0.
  489. - ``ch0_ue_count`` - Channel 0 UE Count attribute file
  490. This attribute file will display the count of UEs on this
  491. DIMM located in channel 0.
  492. - ``ch0_dimm_label`` - Channel 0 DIMM Label control file
  493. This control file allows this DIMM to have a label assigned
  494. to it. With this label in the module, when errors occur
  495. the output can provide the DIMM label in the system log.
  496. This becomes vital for panic events to isolate the
  497. cause of the UE event.
  498. DIMM Labels must be assigned after booting, with information
  499. that correctly identifies the physical slot with its
  500. silk screen label. This information is currently very
  501. motherboard specific and determination of this information
  502. must occur in userland at this time.
  503. - ``ch1_ce_count`` - Channel 1 CE Count attribute file
  504. This attribute file will display the count of CEs on this
  505. DIMM located in channel 1.
  506. - ``ch1_ue_count`` - Channel 1 UE Count attribute file
  507. This attribute file will display the count of UEs on this
  508. DIMM located in channel 0.
  509. - ``ch1_dimm_label`` - Channel 1 DIMM Label control file
  510. This control file allows this DIMM to have a label assigned
  511. to it. With this label in the module, when errors occur
  512. the output can provide the DIMM label in the system log.
  513. This becomes vital for panic events to isolate the
  514. cause of the UE event.
  515. DIMM Labels must be assigned after booting, with information
  516. that correctly identifies the physical slot with its
  517. silk screen label. This information is currently very
  518. motherboard specific and determination of this information
  519. must occur in userland at this time.
  520. System Logging
  521. --------------
  522. If logging for UEs and CEs is enabled, then system logs will contain
  523. information indicating that errors have been detected::
  524. EDAC MC0: CE page 0x283, offset 0xce0, grain 8, syndrome 0x6ec3, row 0, channel 1 "DIMM_B1": amd76x_edac
  525. EDAC MC0: CE page 0x1e5, offset 0xfb0, grain 8, syndrome 0xb741, row 0, channel 1 "DIMM_B1": amd76x_edac
  526. The structure of the message is:
  527. +---------------------------------------+-------------+
  528. | Content | Example |
  529. +=======================================+=============+
  530. | The memory controller | MC0 |
  531. +---------------------------------------+-------------+
  532. | Error type | CE |
  533. +---------------------------------------+-------------+
  534. | Memory page | 0x283 |
  535. +---------------------------------------+-------------+
  536. | Offset in the page | 0xce0 |
  537. +---------------------------------------+-------------+
  538. | The byte granularity | grain 8 |
  539. | or resolution of the error | |
  540. +---------------------------------------+-------------+
  541. | The error syndrome | 0xb741 |
  542. +---------------------------------------+-------------+
  543. | Memory row | row 0 |
  544. +---------------------------------------+-------------+
  545. | Memory channel | channel 1 |
  546. +---------------------------------------+-------------+
  547. | DIMM label, if set prior | DIMM B1 |
  548. +---------------------------------------+-------------+
  549. | And then an optional, driver-specific | |
  550. | message that may have additional | |
  551. | information. | |
  552. +---------------------------------------+-------------+
  553. Both UEs and CEs with no info will lack all but memory controller, error
  554. type, a notice of "no info" and then an optional, driver-specific error
  555. message.
  556. PCI Bus Parity Detection
  557. ------------------------
  558. On Header Type 00 devices, the primary status is looked at for any
  559. parity error regardless of whether parity is enabled on the device or
  560. not. (The spec indicates parity is generated in some cases). On Header
  561. Type 01 bridges, the secondary status register is also looked at to see
  562. if parity occurred on the bus on the other side of the bridge.
  563. Sysfs configuration
  564. -------------------
  565. Under ``/sys/devices/system/edac/pci`` are control and attribute files as
  566. follows:
  567. - ``check_pci_parity`` - Enable/Disable PCI Parity checking control file
  568. This control file enables or disables the PCI Bus Parity scanning
  569. operation. Writing a 1 to this file enables the scanning. Writing
  570. a 0 to this file disables the scanning.
  571. Enable::
  572. echo "1" >/sys/devices/system/edac/pci/check_pci_parity
  573. Disable::
  574. echo "0" >/sys/devices/system/edac/pci/check_pci_parity
  575. - ``pci_parity_count`` - Parity Count
  576. This attribute file will display the number of parity errors that
  577. have been detected.
  578. Module parameters
  579. -----------------
  580. - ``edac_mc_panic_on_ue`` - Panic on UE control file
  581. An uncorrectable error will cause a machine panic. This is usually
  582. desirable. It is a bad idea to continue when an uncorrectable error
  583. occurs - it is indeterminate what was uncorrected and the operating
  584. system context might be so mangled that continuing will lead to further
  585. corruption. If the kernel has MCE configured, then EDAC will never
  586. notice the UE.
  587. LOAD TIME::
  588. module/kernel parameter: edac_mc_panic_on_ue=[0|1]
  589. RUN TIME::
  590. echo "1" > /sys/module/edac_core/parameters/edac_mc_panic_on_ue
  591. - ``edac_mc_log_ue`` - Log UE control file
  592. Generate kernel messages describing uncorrectable errors. These errors
  593. are reported through the system message log system. UE statistics
  594. will be accumulated even when UE logging is disabled.
  595. LOAD TIME::
  596. module/kernel parameter: edac_mc_log_ue=[0|1]
  597. RUN TIME::
  598. echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ue
  599. - ``edac_mc_log_ce`` - Log CE control file
  600. Generate kernel messages describing correctable errors. These
  601. errors are reported through the system message log system.
  602. CE statistics will be accumulated even when CE logging is disabled.
  603. LOAD TIME::
  604. module/kernel parameter: edac_mc_log_ce=[0|1]
  605. RUN TIME::
  606. echo "1" > /sys/module/edac_core/parameters/edac_mc_log_ce
  607. - ``edac_mc_poll_msec`` - Polling period control file
  608. The time period, in milliseconds, for polling for error information.
  609. Too small a value wastes resources. Too large a value might delay
  610. necessary handling of errors and might loose valuable information for
  611. locating the error. 1000 milliseconds (once each second) is the current
  612. default. Systems which require all the bandwidth they can get, may
  613. increase this.
  614. LOAD TIME::
  615. module/kernel parameter: edac_mc_poll_msec=[0|1]
  616. RUN TIME::
  617. echo "1000" > /sys/module/edac_core/parameters/edac_mc_poll_msec
  618. - ``panic_on_pci_parity`` - Panic on PCI PARITY Error
  619. This control file enables or disables panicking when a parity
  620. error has been detected.
  621. module/kernel parameter::
  622. edac_panic_on_pci_pe=[0|1]
  623. Enable::
  624. echo "1" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
  625. Disable::
  626. echo "0" > /sys/module/edac_core/parameters/edac_panic_on_pci_pe
  627. EDAC device type
  628. ----------------
  629. In the header file, edac_pci.h, there is a series of edac_device structures
  630. and APIs for the EDAC_DEVICE.
  631. User space access to an edac_device is through the sysfs interface.
  632. At the location ``/sys/devices/system/edac`` (sysfs) new edac_device devices
  633. will appear.
  634. There is a three level tree beneath the above ``edac`` directory. For example,
  635. the ``test_device_edac`` device (found at the http://bluesmoke.sourceforget.net
  636. website) installs itself as::
  637. /sys/devices/system/edac/test-instance
  638. in this directory are various controls, a symlink and one or more ``instance``
  639. directories.
  640. The standard default controls are:
  641. ============== =======================================================
  642. log_ce boolean to log CE events
  643. log_ue boolean to log UE events
  644. panic_on_ue boolean to ``panic`` the system if an UE is encountered
  645. (default off, can be set true via startup script)
  646. poll_msec time period between POLL cycles for events
  647. ============== =======================================================
  648. The test_device_edac device adds at least one of its own custom control:
  649. ============== ==================================================
  650. test_bits which in the current test driver does nothing but
  651. show how it is installed. A ported driver can
  652. add one or more such controls and/or attributes
  653. for specific uses.
  654. One out-of-tree driver uses controls here to allow
  655. for ERROR INJECTION operations to hardware
  656. injection registers
  657. ============== ==================================================
  658. The symlink points to the 'struct dev' that is registered for this edac_device.
  659. Instances
  660. ---------
  661. One or more instance directories are present. For the ``test_device_edac``
  662. case:
  663. +----------------+
  664. | test-instance0 |
  665. +----------------+
  666. In this directory there are two default counter attributes, which are totals of
  667. counter in deeper subdirectories.
  668. ============== ====================================
  669. ce_count total of CE events of subdirectories
  670. ue_count total of UE events of subdirectories
  671. ============== ====================================
  672. Blocks
  673. ------
  674. At the lowest directory level is the ``block`` directory. There can be 0, 1
  675. or more blocks specified in each instance:
  676. +-------------+
  677. | test-block0 |
  678. +-------------+
  679. In this directory the default attributes are:
  680. ============== ================================================
  681. ce_count which is counter of CE events for this ``block``
  682. of hardware being monitored
  683. ue_count which is counter of UE events for this ``block``
  684. of hardware being monitored
  685. ============== ================================================
  686. The ``test_device_edac`` device adds 4 attributes and 1 control:
  687. ================== ====================================================
  688. test-block-bits-0 for every POLL cycle this counter
  689. is incremented
  690. test-block-bits-1 every 10 cycles, this counter is bumped once,
  691. and test-block-bits-0 is set to 0
  692. test-block-bits-2 every 100 cycles, this counter is bumped once,
  693. and test-block-bits-1 is set to 0
  694. test-block-bits-3 every 1000 cycles, this counter is bumped once,
  695. and test-block-bits-2 is set to 0
  696. ================== ====================================================
  697. ================== ====================================================
  698. reset-counters writing ANY thing to this control will
  699. reset all the above counters.
  700. ================== ====================================================
  701. Use of the ``test_device_edac`` driver should enable any others to create their own
  702. unique drivers for their hardware systems.
  703. The ``test_device_edac`` sample driver is located at the
  704. http://bluesmoke.sourceforge.net project site for EDAC.
  705. Usage of EDAC APIs on Nehalem and newer Intel CPUs
  706. --------------------------------------------------
  707. On older Intel architectures, the memory controller was part of the North
  708. Bridge chipset. Nehalem, Sandy Bridge, Ivy Bridge, Haswell, Sky Lake and
  709. newer Intel architectures integrated an enhanced version of the memory
  710. controller (MC) inside the CPUs.
  711. This chapter will cover the differences of the enhanced memory controllers
  712. found on newer Intel CPUs, such as ``i7core_edac``, ``sb_edac`` and
  713. ``sbx_edac`` drivers.
  714. .. note::
  715. The Xeon E7 processor families use a separate chip for the memory
  716. controller, called Intel Scalable Memory Buffer. This section doesn't
  717. apply for such families.
  718. 1) There is one Memory Controller per Quick Patch Interconnect
  719. (QPI). At the driver, the term "socket" means one QPI. This is
  720. associated with a physical CPU socket.
  721. Each MC have 3 physical read channels, 3 physical write channels and
  722. 3 logic channels. The driver currently sees it as just 3 channels.
  723. Each channel can have up to 3 DIMMs.
  724. The minimum known unity is DIMMs. There are no information about csrows.
  725. As EDAC API maps the minimum unity is csrows, the driver sequentially
  726. maps channel/DIMM into different csrows.
  727. For example, supposing the following layout::
  728. Ch0 phy rd0, wr0 (0x063f4031): 2 ranks, UDIMMs
  729. dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
  730. dimm 1 1024 Mb offset: 4, bank: 8, rank: 1, row: 0x4000, col: 0x400
  731. Ch1 phy rd1, wr1 (0x063f4031): 2 ranks, UDIMMs
  732. dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
  733. Ch2 phy rd3, wr3 (0x063f4031): 2 ranks, UDIMMs
  734. dimm 0 1024 Mb offset: 0, bank: 8, rank: 1, row: 0x4000, col: 0x400
  735. The driver will map it as::
  736. csrow0: channel 0, dimm0
  737. csrow1: channel 0, dimm1
  738. csrow2: channel 1, dimm0
  739. csrow3: channel 2, dimm0
  740. exports one DIMM per csrow.
  741. Each QPI is exported as a different memory controller.
  742. 2) The MC has the ability to inject errors to test drivers. The drivers
  743. implement this functionality via some error injection nodes:
  744. For injecting a memory error, there are some sysfs nodes, under
  745. ``/sys/devices/system/edac/mc/mc?/``:
  746. - ``inject_addrmatch/*``:
  747. Controls the error injection mask register. It is possible to specify
  748. several characteristics of the address to match an error code::
  749. dimm = the affected dimm. Numbers are relative to a channel;
  750. rank = the memory rank;
  751. channel = the channel that will generate an error;
  752. bank = the affected bank;
  753. page = the page address;
  754. column (or col) = the address column.
  755. each of the above values can be set to "any" to match any valid value.
  756. At driver init, all values are set to any.
  757. For example, to generate an error at rank 1 of dimm 2, for any channel,
  758. any bank, any page, any column::
  759. echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
  760. echo 1 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
  761. To return to the default behaviour of matching any, you can do::
  762. echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/dimm
  763. echo any >/sys/devices/system/edac/mc/mc0/inject_addrmatch/rank
  764. - ``inject_eccmask``:
  765. specifies what bits will have troubles,
  766. - ``inject_section``:
  767. specifies what ECC cache section will get the error::
  768. 3 for both
  769. 2 for the highest
  770. 1 for the lowest
  771. - ``inject_type``:
  772. specifies the type of error, being a combination of the following bits::
  773. bit 0 - repeat
  774. bit 1 - ecc
  775. bit 2 - parity
  776. - ``inject_enable``:
  777. starts the error generation when something different than 0 is written.
  778. All inject vars can be read. root permission is needed for write.
  779. Datasheet states that the error will only be generated after a write on an
  780. address that matches inject_addrmatch. It seems, however, that reading will
  781. also produce an error.
  782. For example, the following code will generate an error for any write access
  783. at socket 0, on any DIMM/address on channel 2::
  784. echo 2 >/sys/devices/system/edac/mc/mc0/inject_addrmatch/channel
  785. echo 2 >/sys/devices/system/edac/mc/mc0/inject_type
  786. echo 64 >/sys/devices/system/edac/mc/mc0/inject_eccmask
  787. echo 3 >/sys/devices/system/edac/mc/mc0/inject_section
  788. echo 1 >/sys/devices/system/edac/mc/mc0/inject_enable
  789. dd if=/dev/mem of=/dev/null seek=16k bs=4k count=1 >& /dev/null
  790. For socket 1, it is needed to replace "mc0" by "mc1" at the above
  791. commands.
  792. The generated error message will look like::
  793. EDAC MC0: UE row 0, channel-a= 0 channel-b= 0 labels "-": NON_FATAL (addr = 0x0075b980, socket=0, Dimm=0, Channel=2, syndrome=0x00000040, count=1, Err=8c0000400001009f:4000080482 (read error: read ECC error))
  794. 3) Corrected Error memory register counters
  795. Those newer MCs have some registers to count memory errors. The driver
  796. uses those registers to report Corrected Errors on devices with Registered
  797. DIMMs.
  798. However, those counters don't work with Unregistered DIMM. As the chipset
  799. offers some counters that also work with UDIMMs (but with a worse level of
  800. granularity than the default ones), the driver exposes those registers for
  801. UDIMM memories.
  802. They can be read by looking at the contents of ``all_channel_counts/``::
  803. $ for i in /sys/devices/system/edac/mc/mc0/all_channel_counts/*; do echo $i; cat $i; done
  804. /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm0
  805. 0
  806. /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm1
  807. 0
  808. /sys/devices/system/edac/mc/mc0/all_channel_counts/udimm2
  809. 0
  810. What happens here is that errors on different csrows, but at the same
  811. dimm number will increment the same counter.
  812. So, in this memory mapping::
  813. csrow0: channel 0, dimm0
  814. csrow1: channel 0, dimm1
  815. csrow2: channel 1, dimm0
  816. csrow3: channel 2, dimm0
  817. The hardware will increment udimm0 for an error at the first dimm at either
  818. csrow0, csrow2 or csrow3;
  819. The hardware will increment udimm1 for an error at the second dimm at either
  820. csrow0, csrow2 or csrow3;
  821. The hardware will increment udimm2 for an error at the third dimm at either
  822. csrow0, csrow2 or csrow3;
  823. 4) Standard error counters
  824. The standard error counters are generated when an mcelog error is received
  825. by the driver. Since, with UDIMM, this is counted by software, it is
  826. possible that some errors could be lost. With RDIMM's, they display the
  827. contents of the registers
  828. Reference documents used on ``amd64_edac``
  829. ------------------------------------------
  830. ``amd64_edac`` module is based on the following documents
  831. (available from http://support.amd.com/en-us/search/tech-docs):
  832. 1. :Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD
  833. Opteron Processors
  834. :AMD publication #: 26094
  835. :Revision: 3.26
  836. :Link: http://support.amd.com/TechDocs/26094.PDF
  837. 2. :Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh
  838. Processors
  839. :AMD publication #: 32559
  840. :Revision: 3.00
  841. :Issue Date: May 2006
  842. :Link: http://support.amd.com/TechDocs/32559.pdf
  843. 3. :Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h
  844. Processors
  845. :AMD publication #: 31116
  846. :Revision: 3.00
  847. :Issue Date: September 07, 2007
  848. :Link: http://support.amd.com/TechDocs/31116.pdf
  849. 4. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
  850. Models 30h-3Fh Processors
  851. :AMD publication #: 49125
  852. :Revision: 3.06
  853. :Issue Date: 2/12/2015 (latest release)
  854. :Link: http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf
  855. 5. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
  856. Models 60h-6Fh Processors
  857. :AMD publication #: 50742
  858. :Revision: 3.01
  859. :Issue Date: 7/23/2015 (latest release)
  860. :Link: http://support.amd.com/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf
  861. 6. :Title: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h
  862. Models 00h-0Fh Processors
  863. :AMD publication #: 48751
  864. :Revision: 3.03
  865. :Issue Date: 2/23/2015 (latest release)
  866. :Link: http://support.amd.com/TechDocs/48751_16h_bkdg.pdf
  867. Credits
  868. =======
  869. * Written by Doug Thompson <dougthompson@xmission.com>
  870. - 7 Dec 2005
  871. - 17 Jul 2007 Updated
  872. * |copy| Mauro Carvalho Chehab
  873. - 05 Aug 2009 Nehalem interface
  874. - 26 Oct 2016 Converted to ReST and cleanups at the Nehalem section
  875. * EDAC authors/maintainers:
  876. - Doug Thompson, Dave Jiang, Dave Peterson et al,
  877. - Mauro Carvalho Chehab
  878. - Borislav Petkov
  879. - original author: Thayne Harbaugh