imx-ddr.rst 3.5 KB

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  1. =====================================================
  2. Freescale i.MX8 DDR Performance Monitoring Unit (PMU)
  3. =====================================================
  4. There are no performance counters inside the DRAM controller, so performance
  5. signals are brought out to the edge of the controller where a set of 4 x 32 bit
  6. counters is implemented. This is controlled by the CSV modes programed in counter
  7. control register which causes a large number of PERF signals to be generated.
  8. Selection of the value for each counter is done via the config registers. There
  9. is one register for each counter. Counter 0 is special in that it always counts
  10. “time” and when expired causes a lock on itself and the other counters and an
  11. interrupt is raised. If any other counter overflows, it continues counting, and
  12. no interrupt is raised.
  13. The "format" directory describes format of the config (event ID) and config1
  14. (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
  15. devices/imx8_ddr0/format/. The "events" directory describes the events types
  16. hardware supported that can be used with perf tool, see /sys/bus/event_source/
  17. devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented
  18. in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
  19. .. code-block:: bash
  20. perf stat -a -e imx8_ddr0/cycles/ cmd
  21. perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
  22. AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
  23. to count reading or writing matches filter setting. Filter setting is various
  24. from different DRAM controller implementations, which is distinguished by quirks
  25. in the driver. You also can dump info from userspace, filter in "caps" directory
  26. indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
  27. whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
  28. value 1 for supported.
  29. * With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0).
  30. Filter is defined with two configuration parts:
  31. --AXI_ID defines AxID matching value.
  32. --AXI_MASKING defines which bits of AxID are meaningful for the matching.
  33. - 0: corresponding bit is masked.
  34. - 1: corresponding bit is not masked, i.e. used to do the matching.
  35. AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
  36. When non-masked bits are matching corresponding AXI_ID bits then counter is
  37. incremented. Perf counter is incremented if::
  38. AxID && AXI_MASKING == AXI_ID && AXI_MASKING
  39. This filter doesn't support filter different AXI ID for axid-read and axid-write
  40. event at the same time as this filter is shared between counters.
  41. .. code-block:: bash
  42. perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
  43. perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd
  44. .. note::
  45. axi_mask is inverted in userspace(i.e. set bits are bits to mask), and
  46. it will be reverted in driver automatically. so that the user can just specify
  47. axi_id to monitor a specific id, rather than having to specify axi_mask.
  48. .. code-block:: bash
  49. perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
  50. * With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1).
  51. This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits
  52. counting the number of bytes (as opposed to the number of bursts) from DDR
  53. read and write transactions concurrently with another set of data counters.