pcieaer-howto.rst 11 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. .. include:: <isonum.txt>
  3. ===========================================================
  4. The PCI Express Advanced Error Reporting Driver Guide HOWTO
  5. ===========================================================
  6. :Authors: - T. Long Nguyen <tom.l.nguyen@intel.com>
  7. - Yanmin Zhang <yanmin.zhang@intel.com>
  8. :Copyright: |copy| 2006 Intel Corporation
  9. Overview
  10. ===========
  11. About this guide
  12. ----------------
  13. This guide describes the basics of the PCI Express Advanced Error
  14. Reporting (AER) driver and provides information on how to use it, as
  15. well as how to enable the drivers of endpoint devices to conform with
  16. PCI Express AER driver.
  17. What is the PCI Express AER Driver?
  18. -----------------------------------
  19. PCI Express error signaling can occur on the PCI Express link itself
  20. or on behalf of transactions initiated on the link. PCI Express
  21. defines two error reporting paradigms: the baseline capability and
  22. the Advanced Error Reporting capability. The baseline capability is
  23. required of all PCI Express components providing a minimum defined
  24. set of error reporting requirements. Advanced Error Reporting
  25. capability is implemented with a PCI Express advanced error reporting
  26. extended capability structure providing more robust error reporting.
  27. The PCI Express AER driver provides the infrastructure to support PCI
  28. Express Advanced Error Reporting capability. The PCI Express AER
  29. driver provides three basic functions:
  30. - Gathers the comprehensive error information if errors occurred.
  31. - Reports error to the users.
  32. - Performs error recovery actions.
  33. AER driver only attaches root ports which support PCI-Express AER
  34. capability.
  35. User Guide
  36. ==========
  37. Include the PCI Express AER Root Driver into the Linux Kernel
  38. -------------------------------------------------------------
  39. The PCI Express AER Root driver is a Root Port service driver attached
  40. to the PCI Express Port Bus driver. If a user wants to use it, the driver
  41. has to be compiled. Option CONFIG_PCIEAER supports this capability. It
  42. depends on CONFIG_PCIEPORTBUS, so pls. set CONFIG_PCIEPORTBUS=y and
  43. CONFIG_PCIEAER = y.
  44. Load PCI Express AER Root Driver
  45. --------------------------------
  46. Some systems have AER support in firmware. Enabling Linux AER support at
  47. the same time the firmware handles AER may result in unpredictable
  48. behavior. Therefore, Linux does not handle AER events unless the firmware
  49. grants AER control to the OS via the ACPI _OSC method. See the PCI FW 3.0
  50. Specification for details regarding _OSC usage.
  51. AER error output
  52. ----------------
  53. When a PCIe AER error is captured, an error message will be output to
  54. console. If it's a correctable error, it is output as a warning.
  55. Otherwise, it is printed as an error. So users could choose different
  56. log level to filter out correctable error messages.
  57. Below shows an example::
  58. 0000:50:00.0: PCIe Bus Error: severity=Uncorrected (Fatal), type=Transaction Layer, id=0500(Requester ID)
  59. 0000:50:00.0: device [8086:0329] error status/mask=00100000/00000000
  60. 0000:50:00.0: [20] Unsupported Request (First)
  61. 0000:50:00.0: TLP Header: 04000001 00200a03 05010000 00050100
  62. In the example, 'Requester ID' means the ID of the device who sends
  63. the error message to root port. Pls. refer to pci express specs for
  64. other fields.
  65. AER Statistics / Counters
  66. -------------------------
  67. When PCIe AER errors are captured, the counters / statistics are also exposed
  68. in the form of sysfs attributes which are documented at
  69. Documentation/ABI/testing/sysfs-bus-pci-devices-aer_stats
  70. Developer Guide
  71. ===============
  72. To enable AER aware support requires a software driver to configure
  73. the AER capability structure within its device and to provide callbacks.
  74. To support AER better, developers need understand how AER does work
  75. firstly.
  76. PCI Express errors are classified into two types: correctable errors
  77. and uncorrectable errors. This classification is based on the impacts
  78. of those errors, which may result in degraded performance or function
  79. failure.
  80. Correctable errors pose no impacts on the functionality of the
  81. interface. The PCI Express protocol can recover without any software
  82. intervention or any loss of data. These errors are detected and
  83. corrected by hardware. Unlike correctable errors, uncorrectable
  84. errors impact functionality of the interface. Uncorrectable errors
  85. can cause a particular transaction or a particular PCI Express link
  86. to be unreliable. Depending on those error conditions, uncorrectable
  87. errors are further classified into non-fatal errors and fatal errors.
  88. Non-fatal errors cause the particular transaction to be unreliable,
  89. but the PCI Express link itself is fully functional. Fatal errors, on
  90. the other hand, cause the link to be unreliable.
  91. When AER is enabled, a PCI Express device will automatically send an
  92. error message to the PCIe root port above it when the device captures
  93. an error. The Root Port, upon receiving an error reporting message,
  94. internally processes and logs the error message in its PCI Express
  95. capability structure. Error information being logged includes storing
  96. the error reporting agent's requestor ID into the Error Source
  97. Identification Registers and setting the error bits of the Root Error
  98. Status Register accordingly. If AER error reporting is enabled in Root
  99. Error Command Register, the Root Port generates an interrupt if an
  100. error is detected.
  101. Note that the errors as described above are related to the PCI Express
  102. hierarchy and links. These errors do not include any device specific
  103. errors because device specific errors will still get sent directly to
  104. the device driver.
  105. Configure the AER capability structure
  106. --------------------------------------
  107. AER aware drivers of PCI Express component need change the device
  108. control registers to enable AER. They also could change AER registers,
  109. including mask and severity registers. Helper function
  110. pci_enable_pcie_error_reporting could be used to enable AER. See
  111. section 3.3.
  112. Provide callbacks
  113. -----------------
  114. callback reset_link to reset pci express link
  115. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  116. This callback is used to reset the pci express physical link when a
  117. fatal error happens. The root port aer service driver provides a
  118. default reset_link function, but different upstream ports might
  119. have different specifications to reset pci express link, so all
  120. upstream ports should provide their own reset_link functions.
  121. Section 3.2.2.2 provides more detailed info on when to call
  122. reset_link.
  123. PCI error-recovery callbacks
  124. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  125. The PCI Express AER Root driver uses error callbacks to coordinate
  126. with downstream device drivers associated with a hierarchy in question
  127. when performing error recovery actions.
  128. Data struct pci_driver has a pointer, err_handler, to point to
  129. pci_error_handlers who consists of a couple of callback function
  130. pointers. AER driver follows the rules defined in
  131. pci-error-recovery.txt except pci express specific parts (e.g.
  132. reset_link). Pls. refer to pci-error-recovery.txt for detailed
  133. definitions of the callbacks.
  134. Below sections specify when to call the error callback functions.
  135. Correctable errors
  136. ~~~~~~~~~~~~~~~~~~
  137. Correctable errors pose no impacts on the functionality of
  138. the interface. The PCI Express protocol can recover without any
  139. software intervention or any loss of data. These errors do not
  140. require any recovery actions. The AER driver clears the device's
  141. correctable error status register accordingly and logs these errors.
  142. Non-correctable (non-fatal and fatal) errors
  143. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  144. If an error message indicates a non-fatal error, performing link reset
  145. at upstream is not required. The AER driver calls error_detected(dev,
  146. pci_channel_io_normal) to all drivers associated within a hierarchy in
  147. question. for example::
  148. EndPoint<==>DownstreamPort B<==>UpstreamPort A<==>RootPort
  149. If Upstream port A captures an AER error, the hierarchy consists of
  150. Downstream port B and EndPoint.
  151. A driver may return PCI_ERS_RESULT_CAN_RECOVER,
  152. PCI_ERS_RESULT_DISCONNECT, or PCI_ERS_RESULT_NEED_RESET, depending on
  153. whether it can recover or the AER driver calls mmio_enabled as next.
  154. If an error message indicates a fatal error, kernel will broadcast
  155. error_detected(dev, pci_channel_io_frozen) to all drivers within
  156. a hierarchy in question. Then, performing link reset at upstream is
  157. necessary. As different kinds of devices might use different approaches
  158. to reset link, AER port service driver is required to provide the
  159. function to reset link via callback parameter of pcie_do_recovery()
  160. function. If reset_link is not NULL, recovery function will use it
  161. to reset the link. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER
  162. and reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
  163. to mmio_enabled.
  164. helper functions
  165. ----------------
  166. ::
  167. int pci_enable_pcie_error_reporting(struct pci_dev *dev);
  168. pci_enable_pcie_error_reporting enables the device to send error
  169. messages to root port when an error is detected. Note that devices
  170. don't enable the error reporting by default, so device drivers need
  171. call this function to enable it.
  172. ::
  173. int pci_disable_pcie_error_reporting(struct pci_dev *dev);
  174. pci_disable_pcie_error_reporting disables the device to send error
  175. messages to root port when an error is detected.
  176. ::
  177. int pci_aer_clear_nonfatal_status(struct pci_dev *dev);`
  178. pci_aer_clear_nonfatal_status clears non-fatal errors in the uncorrectable
  179. error status register.
  180. Frequent Asked Questions
  181. ------------------------
  182. Q:
  183. What happens if a PCI Express device driver does not provide an
  184. error recovery handler (pci_driver->err_handler is equal to NULL)?
  185. A:
  186. The devices attached with the driver won't be recovered. If the
  187. error is fatal, kernel will print out warning messages. Please refer
  188. to section 3 for more information.
  189. Q:
  190. What happens if an upstream port service driver does not provide
  191. callback reset_link?
  192. A:
  193. Fatal error recovery will fail if the errors are reported by the
  194. upstream ports who are attached by the service driver.
  195. Q:
  196. How does this infrastructure deal with driver that is not PCI
  197. Express aware?
  198. A:
  199. This infrastructure calls the error callback functions of the
  200. driver when an error happens. But if the driver is not aware of
  201. PCI Express, the device might not report its own errors to root
  202. port.
  203. Q:
  204. What modifications will that driver need to make it compatible
  205. with the PCI Express AER Root driver?
  206. A:
  207. It could call the helper functions to enable AER in devices and
  208. cleanup uncorrectable status register. Pls. refer to section 3.3.
  209. Software error injection
  210. ========================
  211. Debugging PCIe AER error recovery code is quite difficult because it
  212. is hard to trigger real hardware errors. Software based error
  213. injection can be used to fake various kinds of PCIe errors.
  214. First you should enable PCIe AER software error injection in kernel
  215. configuration, that is, following item should be in your .config.
  216. CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m
  217. After reboot with new kernel or insert the module, a device file named
  218. /dev/aer_inject should be created.
  219. Then, you need a user space tool named aer-inject, which can be gotten
  220. from:
  221. https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
  222. More information about aer-inject can be found in the document comes
  223. with its source code.