pci.rst 23 KB

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  1. .. SPDX-License-Identifier: GPL-2.0
  2. ==============================
  3. How To Write Linux PCI Drivers
  4. ==============================
  5. :Authors: - Martin Mares <mj@ucw.cz>
  6. - Grant Grundler <grundler@parisc-linux.org>
  7. The world of PCI is vast and full of (mostly unpleasant) surprises.
  8. Since each CPU architecture implements different chip-sets and PCI devices
  9. have different requirements (erm, "features"), the result is the PCI support
  10. in the Linux kernel is not as trivial as one would wish. This short paper
  11. tries to introduce all potential driver authors to Linux APIs for
  12. PCI device drivers.
  13. A more complete resource is the third edition of "Linux Device Drivers"
  14. by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
  15. LDD3 is available for free (under Creative Commons License) from:
  16. https://lwn.net/Kernel/LDD3/.
  17. However, keep in mind that all documents are subject to "bit rot".
  18. Refer to the source code if things are not working as described here.
  19. Please send questions/comments/patches about Linux PCI API to the
  20. "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
  21. Structure of PCI drivers
  22. ========================
  23. PCI drivers "discover" PCI devices in a system via pci_register_driver().
  24. Actually, it's the other way around. When the PCI generic code discovers
  25. a new device, the driver with a matching "description" will be notified.
  26. Details on this below.
  27. pci_register_driver() leaves most of the probing for devices to
  28. the PCI layer and supports online insertion/removal of devices [thus
  29. supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
  30. pci_register_driver() call requires passing in a table of function
  31. pointers and thus dictates the high level structure of a driver.
  32. Once the driver knows about a PCI device and takes ownership, the
  33. driver generally needs to perform the following initialization:
  34. - Enable the device
  35. - Request MMIO/IOP resources
  36. - Set the DMA mask size (for both coherent and streaming DMA)
  37. - Allocate and initialize shared control data (pci_allocate_coherent())
  38. - Access device configuration space (if needed)
  39. - Register IRQ handler (request_irq())
  40. - Initialize non-PCI (i.e. LAN/SCSI/etc parts of the chip)
  41. - Enable DMA/processing engines
  42. When done using the device, and perhaps the module needs to be unloaded,
  43. the driver needs to take the follow steps:
  44. - Disable the device from generating IRQs
  45. - Release the IRQ (free_irq())
  46. - Stop all DMA activity
  47. - Release DMA buffers (both streaming and coherent)
  48. - Unregister from other subsystems (e.g. scsi or netdev)
  49. - Release MMIO/IOP resources
  50. - Disable the device
  51. Most of these topics are covered in the following sections.
  52. For the rest look at LDD3 or <linux/pci.h> .
  53. If the PCI subsystem is not configured (CONFIG_PCI is not set), most of
  54. the PCI functions described below are defined as inline functions either
  55. completely empty or just returning an appropriate error codes to avoid
  56. lots of ifdefs in the drivers.
  57. pci_register_driver() call
  58. ==========================
  59. PCI device drivers call ``pci_register_driver()`` during their
  60. initialization with a pointer to a structure describing the driver
  61. (``struct pci_driver``):
  62. .. kernel-doc:: include/linux/pci.h
  63. :functions: pci_driver
  64. The ID table is an array of ``struct pci_device_id`` entries ending with an
  65. all-zero entry. Definitions with static const are generally preferred.
  66. .. kernel-doc:: include/linux/mod_devicetable.h
  67. :functions: pci_device_id
  68. Most drivers only need ``PCI_DEVICE()`` or ``PCI_DEVICE_CLASS()`` to set up
  69. a pci_device_id table.
  70. New PCI IDs may be added to a device driver pci_ids table at runtime
  71. as shown below::
  72. echo "vendor device subvendor subdevice class class_mask driver_data" > \
  73. /sys/bus/pci/drivers/{driver}/new_id
  74. All fields are passed in as hexadecimal values (no leading 0x).
  75. The vendor and device fields are mandatory, the others are optional. Users
  76. need pass only as many optional fields as necessary:
  77. - subvendor and subdevice fields default to PCI_ANY_ID (FFFFFFFF)
  78. - class and classmask fields default to 0
  79. - driver_data defaults to 0UL.
  80. Note that driver_data must match the value used by any of the pci_device_id
  81. entries defined in the driver. This makes the driver_data field mandatory
  82. if all the pci_device_id entries have a non-zero driver_data value.
  83. Once added, the driver probe routine will be invoked for any unclaimed
  84. PCI devices listed in its (newly updated) pci_ids list.
  85. When the driver exits, it just calls pci_unregister_driver() and the PCI layer
  86. automatically calls the remove hook for all devices handled by the driver.
  87. "Attributes" for driver functions/data
  88. --------------------------------------
  89. Please mark the initialization and cleanup functions where appropriate
  90. (the corresponding macros are defined in <linux/init.h>):
  91. ====== =================================================
  92. __init Initialization code. Thrown away after the driver
  93. initializes.
  94. __exit Exit code. Ignored for non-modular drivers.
  95. ====== =================================================
  96. Tips on when/where to use the above attributes:
  97. - The module_init()/module_exit() functions (and all
  98. initialization functions called _only_ from these)
  99. should be marked __init/__exit.
  100. - Do not mark the struct pci_driver.
  101. - Do NOT mark a function if you are not sure which mark to use.
  102. Better to not mark the function than mark the function wrong.
  103. How to find PCI devices manually
  104. ================================
  105. PCI drivers should have a really good reason for not using the
  106. pci_register_driver() interface to search for PCI devices.
  107. The main reason PCI devices are controlled by multiple drivers
  108. is because one PCI device implements several different HW services.
  109. E.g. combined serial/parallel port/floppy controller.
  110. A manual search may be performed using the following constructs:
  111. Searching by vendor and device ID::
  112. struct pci_dev *dev = NULL;
  113. while (dev = pci_get_device(VENDOR_ID, DEVICE_ID, dev))
  114. configure_device(dev);
  115. Searching by class ID (iterate in a similar way)::
  116. pci_get_class(CLASS_ID, dev)
  117. Searching by both vendor/device and subsystem vendor/device ID::
  118. pci_get_subsys(VENDOR_ID,DEVICE_ID, SUBSYS_VENDOR_ID, SUBSYS_DEVICE_ID, dev).
  119. You can use the constant PCI_ANY_ID as a wildcard replacement for
  120. VENDOR_ID or DEVICE_ID. This allows searching for any device from a
  121. specific vendor, for example.
  122. These functions are hotplug-safe. They increment the reference count on
  123. the pci_dev that they return. You must eventually (possibly at module unload)
  124. decrement the reference count on these devices by calling pci_dev_put().
  125. Device Initialization Steps
  126. ===========================
  127. As noted in the introduction, most PCI drivers need the following steps
  128. for device initialization:
  129. - Enable the device
  130. - Request MMIO/IOP resources
  131. - Set the DMA mask size (for both coherent and streaming DMA)
  132. - Allocate and initialize shared control data (pci_allocate_coherent())
  133. - Access device configuration space (if needed)
  134. - Register IRQ handler (request_irq())
  135. - Initialize non-PCI (i.e. LAN/SCSI/etc parts of the chip)
  136. - Enable DMA/processing engines.
  137. The driver can access PCI config space registers at any time.
  138. (Well, almost. When running BIST, config space can go away...but
  139. that will just result in a PCI Bus Master Abort and config reads
  140. will return garbage).
  141. Enable the PCI device
  142. ---------------------
  143. Before touching any device registers, the driver needs to enable
  144. the PCI device by calling pci_enable_device(). This will:
  145. - wake up the device if it was in suspended state,
  146. - allocate I/O and memory regions of the device (if BIOS did not),
  147. - allocate an IRQ (if BIOS did not).
  148. .. note::
  149. pci_enable_device() can fail! Check the return value.
  150. .. warning::
  151. OS BUG: we don't check resource allocations before enabling those
  152. resources. The sequence would make more sense if we called
  153. pci_request_resources() before calling pci_enable_device().
  154. Currently, the device drivers can't detect the bug when two
  155. devices have been allocated the same range. This is not a common
  156. problem and unlikely to get fixed soon.
  157. This has been discussed before but not changed as of 2.6.19:
  158. https://lore.kernel.org/r/20060302180025.GC28895@flint.arm.linux.org.uk/
  159. pci_set_master() will enable DMA by setting the bus master bit
  160. in the PCI_COMMAND register. It also fixes the latency timer value if
  161. it's set to something bogus by the BIOS. pci_clear_master() will
  162. disable DMA by clearing the bus master bit.
  163. If the PCI device can use the PCI Memory-Write-Invalidate transaction,
  164. call pci_set_mwi(). This enables the PCI_COMMAND bit for Mem-Wr-Inval
  165. and also ensures that the cache line size register is set correctly.
  166. Check the return value of pci_set_mwi() as not all architectures
  167. or chip-sets may support Memory-Write-Invalidate. Alternatively,
  168. if Mem-Wr-Inval would be nice to have but is not required, call
  169. pci_try_set_mwi() to have the system do its best effort at enabling
  170. Mem-Wr-Inval.
  171. Request MMIO/IOP resources
  172. --------------------------
  173. Memory (MMIO), and I/O port addresses should NOT be read directly
  174. from the PCI device config space. Use the values in the pci_dev structure
  175. as the PCI "bus address" might have been remapped to a "host physical"
  176. address by the arch/chip-set specific kernel support.
  177. See Documentation/driver-api/io-mapping.rst for how to access device registers
  178. or device memory.
  179. The device driver needs to call pci_request_region() to verify
  180. no other device is already using the same address resource.
  181. Conversely, drivers should call pci_release_region() AFTER
  182. calling pci_disable_device().
  183. The idea is to prevent two devices colliding on the same address range.
  184. .. tip::
  185. See OS BUG comment above. Currently (2.6.19), The driver can only
  186. determine MMIO and IO Port resource availability _after_ calling
  187. pci_enable_device().
  188. Generic flavors of pci_request_region() are request_mem_region()
  189. (for MMIO ranges) and request_region() (for IO Port ranges).
  190. Use these for address resources that are not described by "normal" PCI
  191. BARs.
  192. Also see pci_request_selected_regions() below.
  193. Set the DMA mask size
  194. ---------------------
  195. .. note::
  196. If anything below doesn't make sense, please refer to
  197. :doc:`/core-api/dma-api`. This section is just a reminder that
  198. drivers need to indicate DMA capabilities of the device and is not
  199. an authoritative source for DMA interfaces.
  200. While all drivers should explicitly indicate the DMA capability
  201. (e.g. 32 or 64 bit) of the PCI bus master, devices with more than
  202. 32-bit bus master capability for streaming data need the driver
  203. to "register" this capability by calling pci_set_dma_mask() with
  204. appropriate parameters. In general this allows more efficient DMA
  205. on systems where System RAM exists above 4G _physical_ address.
  206. Drivers for all PCI-X and PCIe compliant devices must call
  207. pci_set_dma_mask() as they are 64-bit DMA devices.
  208. Similarly, drivers must also "register" this capability if the device
  209. can directly address "consistent memory" in System RAM above 4G physical
  210. address by calling pci_set_consistent_dma_mask().
  211. Again, this includes drivers for all PCI-X and PCIe compliant devices.
  212. Many 64-bit "PCI" devices (before PCI-X) and some PCI-X devices are
  213. 64-bit DMA capable for payload ("streaming") data but not control
  214. ("consistent") data.
  215. Setup shared control data
  216. -------------------------
  217. Once the DMA masks are set, the driver can allocate "consistent" (a.k.a. shared)
  218. memory. See :doc:`/core-api/dma-api` for a full description of
  219. the DMA APIs. This section is just a reminder that it needs to be done
  220. before enabling DMA on the device.
  221. Initialize device registers
  222. ---------------------------
  223. Some drivers will need specific "capability" fields programmed
  224. or other "vendor specific" register initialized or reset.
  225. E.g. clearing pending interrupts.
  226. Register IRQ handler
  227. --------------------
  228. While calling request_irq() is the last step described here,
  229. this is often just another intermediate step to initialize a device.
  230. This step can often be deferred until the device is opened for use.
  231. All interrupt handlers for IRQ lines should be registered with IRQF_SHARED
  232. and use the devid to map IRQs to devices (remember that all PCI IRQ lines
  233. can be shared).
  234. request_irq() will associate an interrupt handler and device handle
  235. with an interrupt number. Historically interrupt numbers represent
  236. IRQ lines which run from the PCI device to the Interrupt controller.
  237. With MSI and MSI-X (more below) the interrupt number is a CPU "vector".
  238. request_irq() also enables the interrupt. Make sure the device is
  239. quiesced and does not have any interrupts pending before registering
  240. the interrupt handler.
  241. MSI and MSI-X are PCI capabilities. Both are "Message Signaled Interrupts"
  242. which deliver interrupts to the CPU via a DMA write to a Local APIC.
  243. The fundamental difference between MSI and MSI-X is how multiple
  244. "vectors" get allocated. MSI requires contiguous blocks of vectors
  245. while MSI-X can allocate several individual ones.
  246. MSI capability can be enabled by calling pci_alloc_irq_vectors() with the
  247. PCI_IRQ_MSI and/or PCI_IRQ_MSIX flags before calling request_irq(). This
  248. causes the PCI support to program CPU vector data into the PCI device
  249. capability registers. Many architectures, chip-sets, or BIOSes do NOT
  250. support MSI or MSI-X and a call to pci_alloc_irq_vectors with just
  251. the PCI_IRQ_MSI and PCI_IRQ_MSIX flags will fail, so try to always
  252. specify PCI_IRQ_LEGACY as well.
  253. Drivers that have different interrupt handlers for MSI/MSI-X and
  254. legacy INTx should chose the right one based on the msi_enabled
  255. and msix_enabled flags in the pci_dev structure after calling
  256. pci_alloc_irq_vectors.
  257. There are (at least) two really good reasons for using MSI:
  258. 1) MSI is an exclusive interrupt vector by definition.
  259. This means the interrupt handler doesn't have to verify
  260. its device caused the interrupt.
  261. 2) MSI avoids DMA/IRQ race conditions. DMA to host memory is guaranteed
  262. to be visible to the host CPU(s) when the MSI is delivered. This
  263. is important for both data coherency and avoiding stale control data.
  264. This guarantee allows the driver to omit MMIO reads to flush
  265. the DMA stream.
  266. See drivers/infiniband/hw/mthca/ or drivers/net/tg3.c for examples
  267. of MSI/MSI-X usage.
  268. PCI device shutdown
  269. ===================
  270. When a PCI device driver is being unloaded, most of the following
  271. steps need to be performed:
  272. - Disable the device from generating IRQs
  273. - Release the IRQ (free_irq())
  274. - Stop all DMA activity
  275. - Release DMA buffers (both streaming and consistent)
  276. - Unregister from other subsystems (e.g. scsi or netdev)
  277. - Disable device from responding to MMIO/IO Port addresses
  278. - Release MMIO/IO Port resource(s)
  279. Stop IRQs on the device
  280. -----------------------
  281. How to do this is chip/device specific. If it's not done, it opens
  282. the possibility of a "screaming interrupt" if (and only if)
  283. the IRQ is shared with another device.
  284. When the shared IRQ handler is "unhooked", the remaining devices
  285. using the same IRQ line will still need the IRQ enabled. Thus if the
  286. "unhooked" device asserts IRQ line, the system will respond assuming
  287. it was one of the remaining devices asserted the IRQ line. Since none
  288. of the other devices will handle the IRQ, the system will "hang" until
  289. it decides the IRQ isn't going to get handled and masks the IRQ (100,000
  290. iterations later). Once the shared IRQ is masked, the remaining devices
  291. will stop functioning properly. Not a nice situation.
  292. This is another reason to use MSI or MSI-X if it's available.
  293. MSI and MSI-X are defined to be exclusive interrupts and thus
  294. are not susceptible to the "screaming interrupt" problem.
  295. Release the IRQ
  296. ---------------
  297. Once the device is quiesced (no more IRQs), one can call free_irq().
  298. This function will return control once any pending IRQs are handled,
  299. "unhook" the drivers IRQ handler from that IRQ, and finally release
  300. the IRQ if no one else is using it.
  301. Stop all DMA activity
  302. ---------------------
  303. It's extremely important to stop all DMA operations BEFORE attempting
  304. to deallocate DMA control data. Failure to do so can result in memory
  305. corruption, hangs, and on some chip-sets a hard crash.
  306. Stopping DMA after stopping the IRQs can avoid races where the
  307. IRQ handler might restart DMA engines.
  308. While this step sounds obvious and trivial, several "mature" drivers
  309. didn't get this step right in the past.
  310. Release DMA buffers
  311. -------------------
  312. Once DMA is stopped, clean up streaming DMA first.
  313. I.e. unmap data buffers and return buffers to "upstream"
  314. owners if there is one.
  315. Then clean up "consistent" buffers which contain the control data.
  316. See :doc:`/core-api/dma-api` for details on unmapping interfaces.
  317. Unregister from other subsystems
  318. --------------------------------
  319. Most low level PCI device drivers support some other subsystem
  320. like USB, ALSA, SCSI, NetDev, Infiniband, etc. Make sure your
  321. driver isn't losing resources from that other subsystem.
  322. If this happens, typically the symptom is an Oops (panic) when
  323. the subsystem attempts to call into a driver that has been unloaded.
  324. Disable Device from responding to MMIO/IO Port addresses
  325. --------------------------------------------------------
  326. io_unmap() MMIO or IO Port resources and then call pci_disable_device().
  327. This is the symmetric opposite of pci_enable_device().
  328. Do not access device registers after calling pci_disable_device().
  329. Release MMIO/IO Port Resource(s)
  330. --------------------------------
  331. Call pci_release_region() to mark the MMIO or IO Port range as available.
  332. Failure to do so usually results in the inability to reload the driver.
  333. How to access PCI config space
  334. ==============================
  335. You can use `pci_(read|write)_config_(byte|word|dword)` to access the config
  336. space of a device represented by `struct pci_dev *`. All these functions return
  337. 0 when successful or an error code (`PCIBIOS_...`) which can be translated to a
  338. text string by pcibios_strerror. Most drivers expect that accesses to valid PCI
  339. devices don't fail.
  340. If you don't have a struct pci_dev available, you can call
  341. `pci_bus_(read|write)_config_(byte|word|dword)` to access a given device
  342. and function on that bus.
  343. If you access fields in the standard portion of the config header, please
  344. use symbolic names of locations and bits declared in <linux/pci.h>.
  345. If you need to access Extended PCI Capability registers, just call
  346. pci_find_capability() for the particular capability and it will find the
  347. corresponding register block for you.
  348. Other interesting functions
  349. ===========================
  350. ============================= ================================================
  351. pci_get_domain_bus_and_slot() Find pci_dev corresponding to given domain,
  352. bus and slot and number. If the device is
  353. found, its reference count is increased.
  354. pci_set_power_state() Set PCI Power Management state (0=D0 ... 3=D3)
  355. pci_find_capability() Find specified capability in device's capability
  356. list.
  357. pci_resource_start() Returns bus start address for a given PCI region
  358. pci_resource_end() Returns bus end address for a given PCI region
  359. pci_resource_len() Returns the byte length of a PCI region
  360. pci_set_drvdata() Set private driver data pointer for a pci_dev
  361. pci_get_drvdata() Return private driver data pointer for a pci_dev
  362. pci_set_mwi() Enable Memory-Write-Invalidate transactions.
  363. pci_clear_mwi() Disable Memory-Write-Invalidate transactions.
  364. ============================= ================================================
  365. Miscellaneous hints
  366. ===================
  367. When displaying PCI device names to the user (for example when a driver wants
  368. to tell the user what card has it found), please use pci_name(pci_dev).
  369. Always refer to the PCI devices by a pointer to the pci_dev structure.
  370. All PCI layer functions use this identification and it's the only
  371. reasonable one. Don't use bus/slot/function numbers except for very
  372. special purposes -- on systems with multiple primary buses their semantics
  373. can be pretty complex.
  374. Don't try to turn on Fast Back to Back writes in your driver. All devices
  375. on the bus need to be capable of doing it, so this is something which needs
  376. to be handled by platform and generic code, not individual drivers.
  377. Vendor and device identifications
  378. =================================
  379. Do not add new device or vendor IDs to include/linux/pci_ids.h unless they
  380. are shared across multiple drivers. You can add private definitions in
  381. your driver if they're helpful, or just use plain hex constants.
  382. The device IDs are arbitrary hex numbers (vendor controlled) and normally used
  383. only in a single location, the pci_device_id table.
  384. Please DO submit new vendor/device IDs to https://pci-ids.ucw.cz/.
  385. There's a mirror of the pci.ids file at https://github.com/pciutils/pciids.
  386. Obsolete functions
  387. ==================
  388. There are several functions which you might come across when trying to
  389. port an old driver to the new PCI interface. They are no longer present
  390. in the kernel as they aren't compatible with hotplug or PCI domains or
  391. having sane locking.
  392. ================= ===========================================
  393. pci_find_device() Superseded by pci_get_device()
  394. pci_find_subsys() Superseded by pci_get_subsys()
  395. pci_find_slot() Superseded by pci_get_domain_bus_and_slot()
  396. pci_get_slot() Superseded by pci_get_domain_bus_and_slot()
  397. ================= ===========================================
  398. The alternative is the traditional PCI device driver that walks PCI
  399. device lists. This is still possible but discouraged.
  400. MMIO Space and "Write Posting"
  401. ==============================
  402. Converting a driver from using I/O Port space to using MMIO space
  403. often requires some additional changes. Specifically, "write posting"
  404. needs to be handled. Many drivers (e.g. tg3, acenic, sym53c8xx_2)
  405. already do this. I/O Port space guarantees write transactions reach the PCI
  406. device before the CPU can continue. Writes to MMIO space allow the CPU
  407. to continue before the transaction reaches the PCI device. HW weenies
  408. call this "Write Posting" because the write completion is "posted" to
  409. the CPU before the transaction has reached its destination.
  410. Thus, timing sensitive code should add readl() where the CPU is
  411. expected to wait before doing other work. The classic "bit banging"
  412. sequence works fine for I/O Port space::
  413. for (i = 8; --i; val >>= 1) {
  414. outb(val & 1, ioport_reg); /* write bit */
  415. udelay(10);
  416. }
  417. The same sequence for MMIO space should be::
  418. for (i = 8; --i; val >>= 1) {
  419. writeb(val & 1, mmio_reg); /* write bit */
  420. readb(safe_mmio_reg); /* flush posted write */
  421. udelay(10);
  422. }
  423. It is important that "safe_mmio_reg" not have any side effects that
  424. interferes with the correct operation of the device.
  425. Another case to watch out for is when resetting a PCI device. Use PCI
  426. Configuration space reads to flush the writel(). This will gracefully
  427. handle the PCI master abort on all platforms if the PCI device is
  428. expected to not respond to a readl(). Most x86 platforms will allow
  429. MMIO reads to master abort (a.k.a. "Soft Fail") and return garbage
  430. (e.g. ~0). But many RISC platforms will crash (a.k.a."Hard Fail").