sysfs-bus-coresight-devices-stm 2.2 KB

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  1. What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source
  2. Date: April 2016
  3. KernelVersion: 4.7
  4. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  5. Description: (RW) Enable/disable tracing on this specific trace macrocell.
  6. Enabling the trace macrocell implies it has been configured
  7. properly and a sink has been identified for it. The path
  8. of coresight components linking the source to the sink is
  9. configured and managed automatically by the coresight framework.
  10. What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
  11. Date: April 2016
  12. KernelVersion: 4.7
  13. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  14. Description: (RW) Provides access to the HW event enable register, used in
  15. conjunction with HW event bank select register.
  16. What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
  17. Date: April 2016
  18. KernelVersion: 4.7
  19. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  20. Description: (RW) Gives access to the HW event block select register
  21. (STMHEBSR) in order to configure up to 256 channels. Used in
  22. conjunction with "hwevent_enable" register as described above.
  23. What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable
  24. Date: April 2016
  25. KernelVersion: 4.7
  26. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  27. Description: (RW) Provides access to the stimulus port enable register
  28. (STMSPER). Used in conjunction with "port_select" described
  29. below.
  30. What: /sys/bus/coresight/devices/<memory_map>.stm/port_select
  31. Date: April 2016
  32. KernelVersion: 4.7
  33. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  34. Description: (RW) Used to determine which bank of stimulus port bit in
  35. register STMSPER (see above) apply to.
  36. What: /sys/bus/coresight/devices/<memory_map>.stm/status
  37. Date: April 2016
  38. KernelVersion: 4.7
  39. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  40. Description: (Read) List various control and status registers. The specific
  41. layout and content is driver specific.
  42. What: /sys/bus/coresight/devices/<memory_map>.stm/traceid
  43. Date: April 2016
  44. KernelVersion: 4.7
  45. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  46. Description: (RW) Holds the trace ID that will appear in the trace stream
  47. coming from this trace entity.