sysfs-bus-coresight-devices-etb10 3.2 KB

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  1. What: /sys/bus/coresight/devices/<memory_map>.etb/enable_sink
  2. Date: November 2014
  3. KernelVersion: 3.19
  4. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  5. Description: (RW) Add/remove a sink from a trace path. There can be multiple
  6. source for a single sink.
  7. ex::
  8. echo 1 > /sys/bus/coresight/devices/20010000.etb/enable_sink
  9. What: /sys/bus/coresight/devices/<memory_map>.etb/trigger_cntr
  10. Date: November 2014
  11. KernelVersion: 3.19
  12. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  13. Description: (RW) Disables write access to the Trace RAM by stopping the
  14. formatter after a defined number of words have been stored
  15. following the trigger event. The number of 32-bit words written
  16. into the Trace RAM following the trigger event is equal to the
  17. value stored in this register+1 (from ARM ETB-TRM).
  18. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rdp
  19. Date: March 2016
  20. KernelVersion: 4.7
  21. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  22. Description: (Read) Defines the depth, in words, of the trace RAM in powers of
  23. 2. The value is read directly from HW register RDP, 0x004.
  24. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/sts
  25. Date: March 2016
  26. KernelVersion: 4.7
  27. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  28. Description: (Read) Shows the value held by the ETB status register. The value
  29. is read directly from HW register STS, 0x00C.
  30. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rrp
  31. Date: March 2016
  32. KernelVersion: 4.7
  33. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  34. Description: (Read) Shows the value held by the ETB RAM Read Pointer register
  35. that is used to read entries from the Trace RAM over the APB
  36. interface. The value is read directly from HW register RRP,
  37. 0x014.
  38. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/rwp
  39. Date: March 2016
  40. KernelVersion: 4.7
  41. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  42. Description: (Read) Shows the value held by the ETB RAM Write Pointer register
  43. that is used to sets the write pointer to write entries from
  44. the CoreSight bus into the Trace RAM. The value is read directly
  45. from HW register RWP, 0x018.
  46. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/trg
  47. Date: March 2016
  48. KernelVersion: 4.7
  49. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  50. Description: (Read) Similar to "trigger_cntr" above except that this value is
  51. read directly from HW register TRG, 0x01C.
  52. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ctl
  53. Date: March 2016
  54. KernelVersion: 4.7
  55. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  56. Description: (Read) Shows the value held by the ETB Control register. The value
  57. is read directly from HW register CTL, 0x020.
  58. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffsr
  59. Date: March 2016
  60. KernelVersion: 4.7
  61. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  62. Description: (Read) Shows the value held by the ETB Formatter and Flush Status
  63. register. The value is read directly from HW register FFSR,
  64. 0x300.
  65. What: /sys/bus/coresight/devices/<memory_map>.etb/mgmt/ffcr
  66. Date: March 2016
  67. KernelVersion: 4.7
  68. Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
  69. Description: (Read) Shows the value held by the ETB Formatter and Flush Control
  70. register. The value is read directly from HW register FFCR,
  71. 0x304.