intel_hdmi_lpe_audio.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
  4. *
  5. * Copyright (C) 2016 Intel Corp
  6. * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
  7. * Ramesh Babu K V <ramesh.babu@intel.com>
  8. * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
  9. * Jerome Anand <jerome.anand@intel.com>
  10. * Aravind Siddappaji <aravindx.siddappaji@intel.com>
  11. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  12. *
  13. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  14. */
  15. #ifndef __INTEL_HDMI_LPE_AUDIO_H
  16. #define __INTEL_HDMI_LPE_AUDIO_H
  17. #define HAD_MIN_CHANNEL 2
  18. #define HAD_MAX_CHANNEL 8
  19. #define HAD_NUM_OF_RING_BUFS 4
  20. /* max 20bit address, aligned to 64 */
  21. #define HAD_MAX_BUFFER ((1024 * 1024 - 1) & ~0x3f)
  22. #define HAD_DEFAULT_BUFFER (600 * 1024) /* default prealloc size */
  23. #define HAD_MAX_PERIODS 256 /* arbitrary, but should suffice */
  24. #define HAD_MIN_PERIODS 1
  25. #define HAD_MAX_PERIOD_BYTES ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)
  26. #define HAD_MIN_PERIOD_BYTES 1024 /* might be smaller */
  27. #define HAD_FIFO_SIZE 0 /* fifo not being used */
  28. #define MAX_SPEAKERS 8
  29. #define AUD_SAMPLE_RATE_32 32000
  30. #define AUD_SAMPLE_RATE_44_1 44100
  31. #define AUD_SAMPLE_RATE_48 48000
  32. #define AUD_SAMPLE_RATE_88_2 88200
  33. #define AUD_SAMPLE_RATE_96 96000
  34. #define AUD_SAMPLE_RATE_176_4 176400
  35. #define AUD_SAMPLE_RATE_192 192000
  36. #define HAD_MIN_RATE AUD_SAMPLE_RATE_32
  37. #define HAD_MAX_RATE AUD_SAMPLE_RATE_192
  38. #define DIS_SAMPLE_RATE_25_2 25200
  39. #define DIS_SAMPLE_RATE_27 27000
  40. #define DIS_SAMPLE_RATE_54 54000
  41. #define DIS_SAMPLE_RATE_74_25 74250
  42. #define DIS_SAMPLE_RATE_148_5 148500
  43. #define HAD_REG_WIDTH 0x08
  44. #define HAD_MAX_DIP_WORDS 16
  45. /* DP Link Rates */
  46. #define DP_2_7_GHZ 270000
  47. #define DP_1_62_GHZ 162000
  48. /* Maud Values */
  49. #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988
  50. #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740
  51. #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982
  52. #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480
  53. #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965
  54. #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961
  55. #define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930
  56. #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314
  57. #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567
  58. #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971
  59. #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134
  60. #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942
  61. #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268
  62. #define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884
  63. /* Naud Value */
  64. #define DP_NAUD_VAL 32768
  65. /* HDMI Controller register offsets - audio domain common */
  66. /* Base address for below regs = 0x65000 */
  67. enum hdmi_ctrl_reg_offset_common {
  68. AUDIO_HDMI_CONFIG_A = 0x000,
  69. AUDIO_HDMI_CONFIG_B = 0x800,
  70. AUDIO_HDMI_CONFIG_C = 0x900,
  71. };
  72. /* HDMI controller register offsets */
  73. enum hdmi_ctrl_reg_offset {
  74. AUD_CONFIG = 0x0,
  75. AUD_CH_STATUS_0 = 0x08,
  76. AUD_CH_STATUS_1 = 0x0C,
  77. AUD_HDMI_CTS = 0x10,
  78. AUD_N_ENABLE = 0x14,
  79. AUD_SAMPLE_RATE = 0x18,
  80. AUD_BUF_CONFIG = 0x20,
  81. AUD_BUF_CH_SWAP = 0x24,
  82. AUD_BUF_A_ADDR = 0x40,
  83. AUD_BUF_A_LENGTH = 0x44,
  84. AUD_BUF_B_ADDR = 0x48,
  85. AUD_BUF_B_LENGTH = 0x4c,
  86. AUD_BUF_C_ADDR = 0x50,
  87. AUD_BUF_C_LENGTH = 0x54,
  88. AUD_BUF_D_ADDR = 0x58,
  89. AUD_BUF_D_LENGTH = 0x5c,
  90. AUD_CNTL_ST = 0x60,
  91. AUD_HDMI_STATUS = 0x64, /* v2 */
  92. AUD_HDMIW_INFOFR = 0x68, /* v2 */
  93. };
  94. /* Audio configuration */
  95. union aud_cfg {
  96. struct {
  97. u32 aud_en:1;
  98. u32 layout:1; /* LAYOUT[01], see below */
  99. u32 fmt:2;
  100. u32 num_ch:3;
  101. u32 set:1;
  102. u32 flat:1;
  103. u32 val_bit:1;
  104. u32 user_bit:1;
  105. u32 underrun:1; /* 0: send null packets,
  106. * 1: send silence stream
  107. */
  108. u32 packet_mode:1; /* 0: 32bit container, 1: 16bit */
  109. u32 left_align:1; /* 0: MSB bits 0-23, 1: bits 8-31 */
  110. u32 bogus_sample:1; /* bogus sample for odd channels */
  111. u32 dp_modei:1; /* 0: HDMI, 1: DP */
  112. u32 rsvd:16;
  113. } regx;
  114. u32 regval;
  115. };
  116. #define AUD_CONFIG_VALID_BIT (1 << 9)
  117. #define AUD_CONFIG_DP_MODE (1 << 15)
  118. #define AUD_CONFIG_CH_MASK 0x70
  119. #define LAYOUT0 0 /* interleaved stereo */
  120. #define LAYOUT1 1 /* for channels > 2 */
  121. /* Audio Channel Status 0 Attributes */
  122. union aud_ch_status_0 {
  123. struct {
  124. u32 ch_status:1;
  125. u32 lpcm_id:1;
  126. u32 cp_info:1;
  127. u32 format:3;
  128. u32 mode:2;
  129. u32 ctg_code:8;
  130. u32 src_num:4;
  131. u32 ch_num:4;
  132. u32 samp_freq:4; /* CH_STATUS_MAP_XXX */
  133. u32 clk_acc:2;
  134. u32 rsvd:2;
  135. } regx;
  136. u32 regval;
  137. };
  138. /* samp_freq values - Sampling rate as per IEC60958 Ver 3 */
  139. #define CH_STATUS_MAP_32KHZ 0x3
  140. #define CH_STATUS_MAP_44KHZ 0x0
  141. #define CH_STATUS_MAP_48KHZ 0x2
  142. #define CH_STATUS_MAP_88KHZ 0x8
  143. #define CH_STATUS_MAP_96KHZ 0xA
  144. #define CH_STATUS_MAP_176KHZ 0xC
  145. #define CH_STATUS_MAP_192KHZ 0xE
  146. /* Audio Channel Status 1 Attributes */
  147. union aud_ch_status_1 {
  148. struct {
  149. u32 max_wrd_len:1;
  150. u32 wrd_len:3;
  151. u32 rsvd:28;
  152. } regx;
  153. u32 regval;
  154. };
  155. #define MAX_SMPL_WIDTH_20 0x0
  156. #define MAX_SMPL_WIDTH_24 0x1
  157. #define SMPL_WIDTH_16BITS 0x1
  158. #define SMPL_WIDTH_24BITS 0x5
  159. /* CTS register */
  160. union aud_hdmi_cts {
  161. struct {
  162. u32 cts_val:24;
  163. u32 en_cts_prog:1;
  164. u32 rsvd:7;
  165. } regx;
  166. u32 regval;
  167. };
  168. /* N register */
  169. union aud_hdmi_n_enable {
  170. struct {
  171. u32 n_val:24;
  172. u32 en_n_prog:1;
  173. u32 rsvd:7;
  174. } regx;
  175. u32 regval;
  176. };
  177. /* Audio Buffer configurations */
  178. union aud_buf_config {
  179. struct {
  180. u32 audio_fifo_watermark:8;
  181. u32 dma_fifo_watermark:3;
  182. u32 rsvd0:5;
  183. u32 aud_delay:8;
  184. u32 rsvd1:8;
  185. } regx;
  186. u32 regval;
  187. };
  188. #define FIFO_THRESHOLD 0xFE
  189. #define DMA_FIFO_THRESHOLD 0x7
  190. /* Audio Sample Swapping offset */
  191. union aud_buf_ch_swap {
  192. struct {
  193. u32 first_0:3;
  194. u32 second_0:3;
  195. u32 first_1:3;
  196. u32 second_1:3;
  197. u32 first_2:3;
  198. u32 second_2:3;
  199. u32 first_3:3;
  200. u32 second_3:3;
  201. u32 rsvd:8;
  202. } regx;
  203. u32 regval;
  204. };
  205. #define SWAP_LFE_CENTER 0x00fac4c8 /* octal 76543210 */
  206. /* Address for Audio Buffer */
  207. union aud_buf_addr {
  208. struct {
  209. u32 valid:1;
  210. u32 intr_en:1;
  211. u32 rsvd:4;
  212. u32 addr:26;
  213. } regx;
  214. u32 regval;
  215. };
  216. #define AUD_BUF_VALID (1U << 0)
  217. #define AUD_BUF_INTR_EN (1U << 1)
  218. /* Length of Audio Buffer */
  219. union aud_buf_len {
  220. struct {
  221. u32 buf_len:20;
  222. u32 rsvd:12;
  223. } regx;
  224. u32 regval;
  225. };
  226. /* Audio Control State Register offset */
  227. union aud_ctrl_st {
  228. struct {
  229. u32 ram_addr:4;
  230. u32 eld_ack:1;
  231. u32 eld_addr:4;
  232. u32 eld_buf_size:5;
  233. u32 eld_valid:1;
  234. u32 cp_ready:1;
  235. u32 dip_freq:2;
  236. u32 dip_idx:3;
  237. u32 dip_en_sta:4;
  238. u32 rsvd:7;
  239. } regx;
  240. u32 regval;
  241. };
  242. /* Audio HDMI Widget Data Island Packet offset */
  243. union aud_info_frame1 {
  244. struct {
  245. u32 pkt_type:8;
  246. u32 ver_num:8;
  247. u32 len:5;
  248. u32 rsvd:11;
  249. } regx;
  250. u32 regval;
  251. };
  252. #define HDMI_INFO_FRAME_WORD1 0x000a0184
  253. #define DP_INFO_FRAME_WORD1 0x00441b84
  254. /* DIP frame 2 */
  255. union aud_info_frame2 {
  256. struct {
  257. u32 chksum:8;
  258. u32 chnl_cnt:3;
  259. u32 rsvd0:1;
  260. u32 coding_type:4;
  261. u32 smpl_size:2;
  262. u32 smpl_freq:3;
  263. u32 rsvd1:3;
  264. u32 format:8;
  265. } regx;
  266. u32 regval;
  267. };
  268. /* DIP frame 3 */
  269. union aud_info_frame3 {
  270. struct {
  271. u32 chnl_alloc:8;
  272. u32 rsvd0:3;
  273. u32 lsv:4;
  274. u32 dm_inh:1;
  275. u32 rsvd1:16;
  276. } regx;
  277. u32 regval;
  278. };
  279. #define VALID_DIP_WORDS 3
  280. /* AUD_HDMI_STATUS bits */
  281. #define HDMI_AUDIO_UNDERRUN (1U << 31)
  282. #define HDMI_AUDIO_BUFFER_DONE (1U << 29)
  283. /* AUD_HDMI_STATUS register mask */
  284. #define AUD_HDMI_STATUS_MASK_UNDERRUN 0xC0000000
  285. #define AUD_HDMI_STATUS_MASK_SRDBG 0x00000002
  286. #define AUD_HDMI_STATUSG_MASK_FUNCRST 0x00000001
  287. #endif