intel_hdmi_audio.c 51 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * intel_hdmi_audio.c - Intel HDMI audio driver
  4. *
  5. * Copyright (C) 2016 Intel Corp
  6. * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
  7. * Ramesh Babu K V <ramesh.babu@intel.com>
  8. * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
  9. * Jerome Anand <jerome.anand@intel.com>
  10. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11. *
  12. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  13. * ALSA driver for Intel HDMI audio
  14. */
  15. #include <linux/types.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/io.h>
  18. #include <linux/slab.h>
  19. #include <linux/module.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/delay.h>
  24. #include <sound/core.h>
  25. #include <sound/asoundef.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/initval.h>
  29. #include <sound/control.h>
  30. #include <sound/jack.h>
  31. #include <drm/drm_edid.h>
  32. #include <drm/intel_lpe_audio.h>
  33. #include "intel_hdmi_audio.h"
  34. #define for_each_pipe(card_ctx, pipe) \
  35. for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
  36. #define for_each_port(card_ctx, port) \
  37. for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
  38. /*standard module options for ALSA. This module supports only one card*/
  39. static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
  40. static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
  41. static bool single_port;
  42. module_param_named(index, hdmi_card_index, int, 0444);
  43. MODULE_PARM_DESC(index,
  44. "Index value for INTEL Intel HDMI Audio controller.");
  45. module_param_named(id, hdmi_card_id, charp, 0444);
  46. MODULE_PARM_DESC(id,
  47. "ID string for INTEL Intel HDMI Audio controller.");
  48. module_param(single_port, bool, 0444);
  49. MODULE_PARM_DESC(single_port,
  50. "Single-port mode (for compatibility)");
  51. /*
  52. * ELD SA bits in the CEA Speaker Allocation data block
  53. */
  54. static const int eld_speaker_allocation_bits[] = {
  55. [0] = FL | FR,
  56. [1] = LFE,
  57. [2] = FC,
  58. [3] = RL | RR,
  59. [4] = RC,
  60. [5] = FLC | FRC,
  61. [6] = RLC | RRC,
  62. /* the following are not defined in ELD yet */
  63. [7] = 0,
  64. };
  65. /*
  66. * This is an ordered list!
  67. *
  68. * The preceding ones have better chances to be selected by
  69. * hdmi_channel_allocation().
  70. */
  71. static struct cea_channel_speaker_allocation channel_allocations[] = {
  72. /* channel: 7 6 5 4 3 2 1 0 */
  73. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  74. /* 2.1 */
  75. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  76. /* Dolby Surround */
  77. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  78. /* surround40 */
  79. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  80. /* surround41 */
  81. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  82. /* surround50 */
  83. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  84. /* surround51 */
  85. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  86. /* 6.1 */
  87. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  88. /* surround71 */
  89. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  90. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  91. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  92. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  93. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  94. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  95. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  96. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  97. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  98. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  99. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  100. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  101. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  102. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  103. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  104. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  105. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  106. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  107. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  108. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  109. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  110. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  111. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  112. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  113. };
  114. static const struct channel_map_table map_tables[] = {
  115. { SNDRV_CHMAP_FL, 0x00, FL },
  116. { SNDRV_CHMAP_FR, 0x01, FR },
  117. { SNDRV_CHMAP_RL, 0x04, RL },
  118. { SNDRV_CHMAP_RR, 0x05, RR },
  119. { SNDRV_CHMAP_LFE, 0x02, LFE },
  120. { SNDRV_CHMAP_FC, 0x03, FC },
  121. { SNDRV_CHMAP_RLC, 0x06, RLC },
  122. { SNDRV_CHMAP_RRC, 0x07, RRC },
  123. {} /* terminator */
  124. };
  125. /* hardware capability structure */
  126. static const struct snd_pcm_hardware had_pcm_hardware = {
  127. .info = (SNDRV_PCM_INFO_INTERLEAVED |
  128. SNDRV_PCM_INFO_MMAP |
  129. SNDRV_PCM_INFO_MMAP_VALID |
  130. SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  131. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  132. SNDRV_PCM_FMTBIT_S24_LE |
  133. SNDRV_PCM_FMTBIT_S32_LE),
  134. .rates = SNDRV_PCM_RATE_32000 |
  135. SNDRV_PCM_RATE_44100 |
  136. SNDRV_PCM_RATE_48000 |
  137. SNDRV_PCM_RATE_88200 |
  138. SNDRV_PCM_RATE_96000 |
  139. SNDRV_PCM_RATE_176400 |
  140. SNDRV_PCM_RATE_192000,
  141. .rate_min = HAD_MIN_RATE,
  142. .rate_max = HAD_MAX_RATE,
  143. .channels_min = HAD_MIN_CHANNEL,
  144. .channels_max = HAD_MAX_CHANNEL,
  145. .buffer_bytes_max = HAD_MAX_BUFFER,
  146. .period_bytes_min = HAD_MIN_PERIOD_BYTES,
  147. .period_bytes_max = HAD_MAX_PERIOD_BYTES,
  148. .periods_min = HAD_MIN_PERIODS,
  149. .periods_max = HAD_MAX_PERIODS,
  150. .fifo_size = HAD_FIFO_SIZE,
  151. };
  152. /* Get the active PCM substream;
  153. * Call had_substream_put() for unreferecing.
  154. * Don't call this inside had_spinlock, as it takes by itself
  155. */
  156. static struct snd_pcm_substream *
  157. had_substream_get(struct snd_intelhad *intelhaddata)
  158. {
  159. struct snd_pcm_substream *substream;
  160. unsigned long flags;
  161. spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
  162. substream = intelhaddata->stream_info.substream;
  163. if (substream)
  164. intelhaddata->stream_info.substream_refcount++;
  165. spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
  166. return substream;
  167. }
  168. /* Unref the active PCM substream;
  169. * Don't call this inside had_spinlock, as it takes by itself
  170. */
  171. static void had_substream_put(struct snd_intelhad *intelhaddata)
  172. {
  173. unsigned long flags;
  174. spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
  175. intelhaddata->stream_info.substream_refcount--;
  176. spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
  177. }
  178. static u32 had_config_offset(int pipe)
  179. {
  180. switch (pipe) {
  181. default:
  182. case 0:
  183. return AUDIO_HDMI_CONFIG_A;
  184. case 1:
  185. return AUDIO_HDMI_CONFIG_B;
  186. case 2:
  187. return AUDIO_HDMI_CONFIG_C;
  188. }
  189. }
  190. /* Register access functions */
  191. static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
  192. int pipe, u32 reg)
  193. {
  194. return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
  195. }
  196. static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
  197. int pipe, u32 reg, u32 val)
  198. {
  199. iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
  200. }
  201. static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
  202. {
  203. if (!ctx->connected)
  204. *val = 0;
  205. else
  206. *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
  207. }
  208. static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
  209. {
  210. if (ctx->connected)
  211. had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
  212. }
  213. /*
  214. * enable / disable audio configuration
  215. *
  216. * The normal read/modify should not directly be used on VLV2 for
  217. * updating AUD_CONFIG register.
  218. * This is because:
  219. * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
  220. * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
  221. * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
  222. * register. This field should be 1xy binary for configuration with 6 or
  223. * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
  224. * causes the "channels" field to be updated as 0xy binary resulting in
  225. * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
  226. * appropriate value when doing read-modify of AUD_CONFIG register.
  227. */
  228. static void had_enable_audio(struct snd_intelhad *intelhaddata,
  229. bool enable)
  230. {
  231. /* update the cached value */
  232. intelhaddata->aud_config.regx.aud_en = enable;
  233. had_write_register(intelhaddata, AUD_CONFIG,
  234. intelhaddata->aud_config.regval);
  235. }
  236. /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
  237. static void had_ack_irqs(struct snd_intelhad *ctx)
  238. {
  239. u32 status_reg;
  240. if (!ctx->connected)
  241. return;
  242. had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
  243. status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
  244. had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
  245. had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
  246. }
  247. /* Reset buffer pointers */
  248. static void had_reset_audio(struct snd_intelhad *intelhaddata)
  249. {
  250. had_write_register(intelhaddata, AUD_HDMI_STATUS,
  251. AUD_HDMI_STATUSG_MASK_FUNCRST);
  252. had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
  253. }
  254. /*
  255. * initialize audio channel status registers
  256. * This function is called in the prepare callback
  257. */
  258. static int had_prog_status_reg(struct snd_pcm_substream *substream,
  259. struct snd_intelhad *intelhaddata)
  260. {
  261. union aud_ch_status_0 ch_stat0 = {.regval = 0};
  262. union aud_ch_status_1 ch_stat1 = {.regval = 0};
  263. ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
  264. IEC958_AES0_NONAUDIO) >> 1;
  265. ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
  266. IEC958_AES3_CON_CLOCK) >> 4;
  267. switch (substream->runtime->rate) {
  268. case AUD_SAMPLE_RATE_32:
  269. ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
  270. break;
  271. case AUD_SAMPLE_RATE_44_1:
  272. ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
  273. break;
  274. case AUD_SAMPLE_RATE_48:
  275. ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
  276. break;
  277. case AUD_SAMPLE_RATE_88_2:
  278. ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
  279. break;
  280. case AUD_SAMPLE_RATE_96:
  281. ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
  282. break;
  283. case AUD_SAMPLE_RATE_176_4:
  284. ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
  285. break;
  286. case AUD_SAMPLE_RATE_192:
  287. ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
  288. break;
  289. default:
  290. /* control should never come here */
  291. return -EINVAL;
  292. }
  293. had_write_register(intelhaddata,
  294. AUD_CH_STATUS_0, ch_stat0.regval);
  295. switch (substream->runtime->format) {
  296. case SNDRV_PCM_FORMAT_S16_LE:
  297. ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
  298. ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
  299. break;
  300. case SNDRV_PCM_FORMAT_S24_LE:
  301. case SNDRV_PCM_FORMAT_S32_LE:
  302. ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
  303. ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
  304. break;
  305. default:
  306. return -EINVAL;
  307. }
  308. had_write_register(intelhaddata,
  309. AUD_CH_STATUS_1, ch_stat1.regval);
  310. return 0;
  311. }
  312. /*
  313. * function to initialize audio
  314. * registers and buffer confgiuration registers
  315. * This function is called in the prepare callback
  316. */
  317. static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
  318. struct snd_intelhad *intelhaddata)
  319. {
  320. union aud_cfg cfg_val = {.regval = 0};
  321. union aud_buf_config buf_cfg = {.regval = 0};
  322. u8 channels;
  323. had_prog_status_reg(substream, intelhaddata);
  324. buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
  325. buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
  326. buf_cfg.regx.aud_delay = 0;
  327. had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
  328. channels = substream->runtime->channels;
  329. cfg_val.regx.num_ch = channels - 2;
  330. if (channels <= 2)
  331. cfg_val.regx.layout = LAYOUT0;
  332. else
  333. cfg_val.regx.layout = LAYOUT1;
  334. if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
  335. cfg_val.regx.packet_mode = 1;
  336. if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
  337. cfg_val.regx.left_align = 1;
  338. cfg_val.regx.val_bit = 1;
  339. /* fix up the DP bits */
  340. if (intelhaddata->dp_output) {
  341. cfg_val.regx.dp_modei = 1;
  342. cfg_val.regx.set = 1;
  343. }
  344. had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
  345. intelhaddata->aud_config = cfg_val;
  346. return 0;
  347. }
  348. /*
  349. * Compute derived values in channel_allocations[].
  350. */
  351. static void init_channel_allocations(void)
  352. {
  353. int i, j;
  354. struct cea_channel_speaker_allocation *p;
  355. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  356. p = channel_allocations + i;
  357. p->channels = 0;
  358. p->spk_mask = 0;
  359. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  360. if (p->speakers[j]) {
  361. p->channels++;
  362. p->spk_mask |= p->speakers[j];
  363. }
  364. }
  365. }
  366. /*
  367. * The transformation takes two steps:
  368. *
  369. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  370. * spk_mask => (channel_allocations[]) => ai->CA
  371. *
  372. * TODO: it could select the wrong CA from multiple candidates.
  373. */
  374. static int had_channel_allocation(struct snd_intelhad *intelhaddata,
  375. int channels)
  376. {
  377. int i;
  378. int ca = 0;
  379. int spk_mask = 0;
  380. /*
  381. * CA defaults to 0 for basic stereo audio
  382. */
  383. if (channels <= 2)
  384. return 0;
  385. /*
  386. * expand ELD's speaker allocation mask
  387. *
  388. * ELD tells the speaker mask in a compact(paired) form,
  389. * expand ELD's notions to match the ones used by Audio InfoFrame.
  390. */
  391. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  392. if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
  393. spk_mask |= eld_speaker_allocation_bits[i];
  394. }
  395. /* search for the first working match in the CA table */
  396. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  397. if (channels == channel_allocations[i].channels &&
  398. (spk_mask & channel_allocations[i].spk_mask) ==
  399. channel_allocations[i].spk_mask) {
  400. ca = channel_allocations[i].ca_index;
  401. break;
  402. }
  403. }
  404. dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
  405. return ca;
  406. }
  407. /* from speaker bit mask to ALSA API channel position */
  408. static int spk_to_chmap(int spk)
  409. {
  410. const struct channel_map_table *t = map_tables;
  411. for (; t->map; t++) {
  412. if (t->spk_mask == spk)
  413. return t->map;
  414. }
  415. return 0;
  416. }
  417. static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
  418. {
  419. int i, c;
  420. int spk_mask = 0;
  421. struct snd_pcm_chmap_elem *chmap;
  422. u8 eld_high, eld_high_mask = 0xF0;
  423. u8 high_msb;
  424. kfree(intelhaddata->chmap->chmap);
  425. intelhaddata->chmap->chmap = NULL;
  426. chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
  427. if (!chmap)
  428. return;
  429. dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
  430. intelhaddata->eld[DRM_ELD_SPEAKER]);
  431. /* WA: Fix the max channel supported to 8 */
  432. /*
  433. * Sink may support more than 8 channels, if eld_high has more than
  434. * one bit set. SOC supports max 8 channels.
  435. * Refer eld_speaker_allocation_bits, for sink speaker allocation
  436. */
  437. /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
  438. eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
  439. if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
  440. /* eld_high & (eld_high-1): if more than 1 bit set */
  441. /* 0x1F: 7 channels */
  442. for (i = 1; i < 4; i++) {
  443. high_msb = eld_high & (0x80 >> i);
  444. if (high_msb) {
  445. intelhaddata->eld[DRM_ELD_SPEAKER] &=
  446. high_msb | 0xF;
  447. break;
  448. }
  449. }
  450. }
  451. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  452. if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
  453. spk_mask |= eld_speaker_allocation_bits[i];
  454. }
  455. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  456. if (spk_mask == channel_allocations[i].spk_mask) {
  457. for (c = 0; c < channel_allocations[i].channels; c++) {
  458. chmap->map[c] = spk_to_chmap(
  459. channel_allocations[i].speakers[
  460. (MAX_SPEAKERS - 1) - c]);
  461. }
  462. chmap->channels = channel_allocations[i].channels;
  463. intelhaddata->chmap->chmap = chmap;
  464. break;
  465. }
  466. }
  467. if (i >= ARRAY_SIZE(channel_allocations))
  468. kfree(chmap);
  469. }
  470. /*
  471. * ALSA API channel-map control callbacks
  472. */
  473. static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
  474. struct snd_ctl_elem_info *uinfo)
  475. {
  476. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  477. uinfo->count = HAD_MAX_CHANNEL;
  478. uinfo->value.integer.min = 0;
  479. uinfo->value.integer.max = SNDRV_CHMAP_LAST;
  480. return 0;
  481. }
  482. static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
  483. struct snd_ctl_elem_value *ucontrol)
  484. {
  485. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  486. struct snd_intelhad *intelhaddata = info->private_data;
  487. int i;
  488. const struct snd_pcm_chmap_elem *chmap;
  489. memset(ucontrol->value.integer.value, 0,
  490. sizeof(long) * HAD_MAX_CHANNEL);
  491. mutex_lock(&intelhaddata->mutex);
  492. if (!intelhaddata->chmap->chmap) {
  493. mutex_unlock(&intelhaddata->mutex);
  494. return 0;
  495. }
  496. chmap = intelhaddata->chmap->chmap;
  497. for (i = 0; i < chmap->channels; i++)
  498. ucontrol->value.integer.value[i] = chmap->map[i];
  499. mutex_unlock(&intelhaddata->mutex);
  500. return 0;
  501. }
  502. static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
  503. struct snd_pcm *pcm)
  504. {
  505. int err;
  506. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  507. NULL, 0, (unsigned long)intelhaddata,
  508. &intelhaddata->chmap);
  509. if (err < 0)
  510. return err;
  511. intelhaddata->chmap->private_data = intelhaddata;
  512. intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
  513. intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
  514. intelhaddata->chmap->chmap = NULL;
  515. return 0;
  516. }
  517. /*
  518. * Initialize Data Island Packets registers
  519. * This function is called in the prepare callback
  520. */
  521. static void had_prog_dip(struct snd_pcm_substream *substream,
  522. struct snd_intelhad *intelhaddata)
  523. {
  524. int i;
  525. union aud_ctrl_st ctrl_state = {.regval = 0};
  526. union aud_info_frame2 frame2 = {.regval = 0};
  527. union aud_info_frame3 frame3 = {.regval = 0};
  528. u8 checksum = 0;
  529. u32 info_frame;
  530. int channels;
  531. int ca;
  532. channels = substream->runtime->channels;
  533. had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
  534. ca = had_channel_allocation(intelhaddata, channels);
  535. if (intelhaddata->dp_output) {
  536. info_frame = DP_INFO_FRAME_WORD1;
  537. frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
  538. } else {
  539. info_frame = HDMI_INFO_FRAME_WORD1;
  540. frame2.regx.chnl_cnt = substream->runtime->channels - 1;
  541. frame3.regx.chnl_alloc = ca;
  542. /* Calculte the byte wide checksum for all valid DIP words */
  543. for (i = 0; i < BYTES_PER_WORD; i++)
  544. checksum += (info_frame >> (i * 8)) & 0xff;
  545. for (i = 0; i < BYTES_PER_WORD; i++)
  546. checksum += (frame2.regval >> (i * 8)) & 0xff;
  547. for (i = 0; i < BYTES_PER_WORD; i++)
  548. checksum += (frame3.regval >> (i * 8)) & 0xff;
  549. frame2.regx.chksum = -(checksum);
  550. }
  551. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
  552. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
  553. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
  554. /* program remaining DIP words with zero */
  555. for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
  556. had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
  557. ctrl_state.regx.dip_freq = 1;
  558. ctrl_state.regx.dip_en_sta = 1;
  559. had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
  560. }
  561. static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
  562. {
  563. u32 maud_val;
  564. /* Select maud according to DP 1.2 spec */
  565. if (link_rate == DP_2_7_GHZ) {
  566. switch (aud_samp_freq) {
  567. case AUD_SAMPLE_RATE_32:
  568. maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
  569. break;
  570. case AUD_SAMPLE_RATE_44_1:
  571. maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
  572. break;
  573. case AUD_SAMPLE_RATE_48:
  574. maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
  575. break;
  576. case AUD_SAMPLE_RATE_88_2:
  577. maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
  578. break;
  579. case AUD_SAMPLE_RATE_96:
  580. maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
  581. break;
  582. case AUD_SAMPLE_RATE_176_4:
  583. maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
  584. break;
  585. case HAD_MAX_RATE:
  586. maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
  587. break;
  588. default:
  589. maud_val = -EINVAL;
  590. break;
  591. }
  592. } else if (link_rate == DP_1_62_GHZ) {
  593. switch (aud_samp_freq) {
  594. case AUD_SAMPLE_RATE_32:
  595. maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
  596. break;
  597. case AUD_SAMPLE_RATE_44_1:
  598. maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
  599. break;
  600. case AUD_SAMPLE_RATE_48:
  601. maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
  602. break;
  603. case AUD_SAMPLE_RATE_88_2:
  604. maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
  605. break;
  606. case AUD_SAMPLE_RATE_96:
  607. maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
  608. break;
  609. case AUD_SAMPLE_RATE_176_4:
  610. maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
  611. break;
  612. case HAD_MAX_RATE:
  613. maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
  614. break;
  615. default:
  616. maud_val = -EINVAL;
  617. break;
  618. }
  619. } else
  620. maud_val = -EINVAL;
  621. return maud_val;
  622. }
  623. /*
  624. * Program HDMI audio CTS value
  625. *
  626. * @aud_samp_freq: sampling frequency of audio data
  627. * @tmds: sampling frequency of the display data
  628. * @link_rate: DP link rate
  629. * @n_param: N value, depends on aud_samp_freq
  630. * @intelhaddata: substream private data
  631. *
  632. * Program CTS register based on the audio and display sampling frequency
  633. */
  634. static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
  635. u32 n_param, struct snd_intelhad *intelhaddata)
  636. {
  637. u32 cts_val;
  638. u64 dividend, divisor;
  639. if (intelhaddata->dp_output) {
  640. /* Substitute cts_val with Maud according to DP 1.2 spec*/
  641. cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
  642. } else {
  643. /* Calculate CTS according to HDMI 1.3a spec*/
  644. dividend = (u64)tmds * n_param*1000;
  645. divisor = 128 * aud_samp_freq;
  646. cts_val = div64_u64(dividend, divisor);
  647. }
  648. dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
  649. tmds, n_param, cts_val);
  650. had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
  651. }
  652. static int had_calculate_n_value(u32 aud_samp_freq)
  653. {
  654. int n_val;
  655. /* Select N according to HDMI 1.3a spec*/
  656. switch (aud_samp_freq) {
  657. case AUD_SAMPLE_RATE_32:
  658. n_val = 4096;
  659. break;
  660. case AUD_SAMPLE_RATE_44_1:
  661. n_val = 6272;
  662. break;
  663. case AUD_SAMPLE_RATE_48:
  664. n_val = 6144;
  665. break;
  666. case AUD_SAMPLE_RATE_88_2:
  667. n_val = 12544;
  668. break;
  669. case AUD_SAMPLE_RATE_96:
  670. n_val = 12288;
  671. break;
  672. case AUD_SAMPLE_RATE_176_4:
  673. n_val = 25088;
  674. break;
  675. case HAD_MAX_RATE:
  676. n_val = 24576;
  677. break;
  678. default:
  679. n_val = -EINVAL;
  680. break;
  681. }
  682. return n_val;
  683. }
  684. /*
  685. * Program HDMI audio N value
  686. *
  687. * @aud_samp_freq: sampling frequency of audio data
  688. * @n_param: N value, depends on aud_samp_freq
  689. * @intelhaddata: substream private data
  690. *
  691. * This function is called in the prepare callback.
  692. * It programs based on the audio and display sampling frequency
  693. */
  694. static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
  695. struct snd_intelhad *intelhaddata)
  696. {
  697. int n_val;
  698. if (intelhaddata->dp_output) {
  699. /*
  700. * According to DP specs, Maud and Naud values hold
  701. * a relationship, which is stated as:
  702. * Maud/Naud = 512 * fs / f_LS_Clk
  703. * where, fs is the sampling frequency of the audio stream
  704. * and Naud is 32768 for Async clock.
  705. */
  706. n_val = DP_NAUD_VAL;
  707. } else
  708. n_val = had_calculate_n_value(aud_samp_freq);
  709. if (n_val < 0)
  710. return n_val;
  711. had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
  712. *n_param = n_val;
  713. return 0;
  714. }
  715. /*
  716. * PCM ring buffer handling
  717. *
  718. * The hardware provides a ring buffer with the fixed 4 buffer descriptors
  719. * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping
  720. * moves at each period elapsed. The below illustrates how it works:
  721. *
  722. * At time=0
  723. * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
  724. * BD | 0 | 1 | 2 | 3 |
  725. *
  726. * At time=1 (period elapsed)
  727. * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
  728. * BD | 1 | 2 | 3 | 0 |
  729. *
  730. * At time=2 (second period elapsed)
  731. * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
  732. * BD | 2 | 3 | 0 | 1 |
  733. *
  734. * The bd_head field points to the index of the BD to be read. It's also the
  735. * position to be filled at next. The pcm_head and the pcm_filled fields
  736. * point to the indices of the current position and of the next position to
  737. * be filled, respectively. For PCM buffer there are both _head and _filled
  738. * because they may be difference when nperiods > 4. For example, in the
  739. * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
  740. *
  741. * pcm_head (=1) --v v-- pcm_filled (=5)
  742. * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
  743. * BD | 1 | 2 | 3 | 0 |
  744. * bd_head (=1) --^ ^-- next to fill (= bd_head)
  745. *
  746. * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
  747. * the hardware skips those BDs in the loop.
  748. *
  749. * An exceptional setup is the case with nperiods=1. Since we have to update
  750. * BDs after finishing one BD processing, we'd need at least two BDs, where
  751. * both BDs point to the same content, the same address, the same size of the
  752. * whole PCM buffer.
  753. */
  754. #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
  755. #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
  756. /* Set up a buffer descriptor at the "filled" position */
  757. static void had_prog_bd(struct snd_pcm_substream *substream,
  758. struct snd_intelhad *intelhaddata)
  759. {
  760. int idx = intelhaddata->bd_head;
  761. int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
  762. u32 addr = substream->runtime->dma_addr + ofs;
  763. addr |= AUD_BUF_VALID;
  764. if (!substream->runtime->no_period_wakeup)
  765. addr |= AUD_BUF_INTR_EN;
  766. had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
  767. had_write_register(intelhaddata, AUD_BUF_LEN(idx),
  768. intelhaddata->period_bytes);
  769. /* advance the indices to the next */
  770. intelhaddata->bd_head++;
  771. intelhaddata->bd_head %= intelhaddata->num_bds;
  772. intelhaddata->pcmbuf_filled++;
  773. intelhaddata->pcmbuf_filled %= substream->runtime->periods;
  774. }
  775. /* invalidate a buffer descriptor with the given index */
  776. static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
  777. int idx)
  778. {
  779. had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
  780. had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
  781. }
  782. /* Initial programming of ring buffer */
  783. static void had_init_ringbuf(struct snd_pcm_substream *substream,
  784. struct snd_intelhad *intelhaddata)
  785. {
  786. struct snd_pcm_runtime *runtime = substream->runtime;
  787. int i, num_periods;
  788. num_periods = runtime->periods;
  789. intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
  790. /* set the minimum 2 BDs for num_periods=1 */
  791. intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
  792. intelhaddata->period_bytes =
  793. frames_to_bytes(runtime, runtime->period_size);
  794. WARN_ON(intelhaddata->period_bytes & 0x3f);
  795. intelhaddata->bd_head = 0;
  796. intelhaddata->pcmbuf_head = 0;
  797. intelhaddata->pcmbuf_filled = 0;
  798. for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
  799. if (i < intelhaddata->num_bds)
  800. had_prog_bd(substream, intelhaddata);
  801. else /* invalidate the rest */
  802. had_invalidate_bd(intelhaddata, i);
  803. }
  804. intelhaddata->bd_head = 0; /* reset at head again before starting */
  805. }
  806. /* process a bd, advance to the next */
  807. static void had_advance_ringbuf(struct snd_pcm_substream *substream,
  808. struct snd_intelhad *intelhaddata)
  809. {
  810. int num_periods = substream->runtime->periods;
  811. /* reprogram the next buffer */
  812. had_prog_bd(substream, intelhaddata);
  813. /* proceed to next */
  814. intelhaddata->pcmbuf_head++;
  815. intelhaddata->pcmbuf_head %= num_periods;
  816. }
  817. /* process the current BD(s);
  818. * returns the current PCM buffer byte position, or -EPIPE for underrun.
  819. */
  820. static int had_process_ringbuf(struct snd_pcm_substream *substream,
  821. struct snd_intelhad *intelhaddata)
  822. {
  823. int len, processed;
  824. unsigned long flags;
  825. processed = 0;
  826. spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
  827. for (;;) {
  828. /* get the remaining bytes on the buffer */
  829. had_read_register(intelhaddata,
  830. AUD_BUF_LEN(intelhaddata->bd_head),
  831. &len);
  832. if (len < 0 || len > intelhaddata->period_bytes) {
  833. dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
  834. len);
  835. len = -EPIPE;
  836. goto out;
  837. }
  838. if (len > 0) /* OK, this is the current buffer */
  839. break;
  840. /* len=0 => already empty, check the next buffer */
  841. if (++processed >= intelhaddata->num_bds) {
  842. len = -EPIPE; /* all empty? - report underrun */
  843. goto out;
  844. }
  845. had_advance_ringbuf(substream, intelhaddata);
  846. }
  847. len = intelhaddata->period_bytes - len;
  848. len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
  849. out:
  850. spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
  851. return len;
  852. }
  853. /* called from irq handler */
  854. static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
  855. {
  856. struct snd_pcm_substream *substream;
  857. substream = had_substream_get(intelhaddata);
  858. if (!substream)
  859. return; /* no stream? - bail out */
  860. if (!intelhaddata->connected) {
  861. snd_pcm_stop_xrun(substream);
  862. goto out; /* disconnected? - bail out */
  863. }
  864. /* process or stop the stream */
  865. if (had_process_ringbuf(substream, intelhaddata) < 0)
  866. snd_pcm_stop_xrun(substream);
  867. else
  868. snd_pcm_period_elapsed(substream);
  869. out:
  870. had_substream_put(intelhaddata);
  871. }
  872. /*
  873. * The interrupt status 'sticky' bits might not be cleared by
  874. * setting '1' to that bit once...
  875. */
  876. static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
  877. {
  878. int i;
  879. u32 val;
  880. for (i = 0; i < 100; i++) {
  881. /* clear bit30, 31 AUD_HDMI_STATUS */
  882. had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
  883. if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
  884. return;
  885. udelay(100);
  886. cond_resched();
  887. had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
  888. }
  889. dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
  890. }
  891. /* Perform some reset procedure but only when need_reset is set;
  892. * this is called from prepare or hw_free callbacks once after trigger STOP
  893. * or underrun has been processed in order to settle down the h/w state.
  894. */
  895. static void had_do_reset(struct snd_intelhad *intelhaddata)
  896. {
  897. if (!intelhaddata->need_reset || !intelhaddata->connected)
  898. return;
  899. /* Reset buffer pointers */
  900. had_reset_audio(intelhaddata);
  901. wait_clear_underrun_bit(intelhaddata);
  902. intelhaddata->need_reset = false;
  903. }
  904. /* called from irq handler */
  905. static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
  906. {
  907. struct snd_pcm_substream *substream;
  908. /* Report UNDERRUN error to above layers */
  909. substream = had_substream_get(intelhaddata);
  910. if (substream) {
  911. snd_pcm_stop_xrun(substream);
  912. had_substream_put(intelhaddata);
  913. }
  914. intelhaddata->need_reset = true;
  915. }
  916. /*
  917. * ALSA PCM open callback
  918. */
  919. static int had_pcm_open(struct snd_pcm_substream *substream)
  920. {
  921. struct snd_intelhad *intelhaddata;
  922. struct snd_pcm_runtime *runtime;
  923. int retval;
  924. intelhaddata = snd_pcm_substream_chip(substream);
  925. runtime = substream->runtime;
  926. pm_runtime_get_sync(intelhaddata->dev);
  927. /* set the runtime hw parameter with local snd_pcm_hardware struct */
  928. runtime->hw = had_pcm_hardware;
  929. retval = snd_pcm_hw_constraint_integer(runtime,
  930. SNDRV_PCM_HW_PARAM_PERIODS);
  931. if (retval < 0)
  932. goto error;
  933. /* Make sure, that the period size is always aligned
  934. * 64byte boundary
  935. */
  936. retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
  937. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
  938. if (retval < 0)
  939. goto error;
  940. retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  941. if (retval < 0)
  942. goto error;
  943. /* expose PCM substream */
  944. spin_lock_irq(&intelhaddata->had_spinlock);
  945. intelhaddata->stream_info.substream = substream;
  946. intelhaddata->stream_info.substream_refcount++;
  947. spin_unlock_irq(&intelhaddata->had_spinlock);
  948. return retval;
  949. error:
  950. pm_runtime_mark_last_busy(intelhaddata->dev);
  951. pm_runtime_put_autosuspend(intelhaddata->dev);
  952. return retval;
  953. }
  954. /*
  955. * ALSA PCM close callback
  956. */
  957. static int had_pcm_close(struct snd_pcm_substream *substream)
  958. {
  959. struct snd_intelhad *intelhaddata;
  960. intelhaddata = snd_pcm_substream_chip(substream);
  961. /* unreference and sync with the pending PCM accesses */
  962. spin_lock_irq(&intelhaddata->had_spinlock);
  963. intelhaddata->stream_info.substream = NULL;
  964. intelhaddata->stream_info.substream_refcount--;
  965. while (intelhaddata->stream_info.substream_refcount > 0) {
  966. spin_unlock_irq(&intelhaddata->had_spinlock);
  967. cpu_relax();
  968. spin_lock_irq(&intelhaddata->had_spinlock);
  969. }
  970. spin_unlock_irq(&intelhaddata->had_spinlock);
  971. pm_runtime_mark_last_busy(intelhaddata->dev);
  972. pm_runtime_put_autosuspend(intelhaddata->dev);
  973. return 0;
  974. }
  975. /*
  976. * ALSA PCM hw_params callback
  977. */
  978. static int had_pcm_hw_params(struct snd_pcm_substream *substream,
  979. struct snd_pcm_hw_params *hw_params)
  980. {
  981. struct snd_intelhad *intelhaddata;
  982. int buf_size;
  983. intelhaddata = snd_pcm_substream_chip(substream);
  984. buf_size = params_buffer_bytes(hw_params);
  985. dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
  986. __func__, buf_size);
  987. return 0;
  988. }
  989. /*
  990. * ALSA PCM hw_free callback
  991. */
  992. static int had_pcm_hw_free(struct snd_pcm_substream *substream)
  993. {
  994. struct snd_intelhad *intelhaddata;
  995. intelhaddata = snd_pcm_substream_chip(substream);
  996. had_do_reset(intelhaddata);
  997. return 0;
  998. }
  999. /*
  1000. * ALSA PCM trigger callback
  1001. */
  1002. static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  1003. {
  1004. int retval = 0;
  1005. struct snd_intelhad *intelhaddata;
  1006. intelhaddata = snd_pcm_substream_chip(substream);
  1007. spin_lock(&intelhaddata->had_spinlock);
  1008. switch (cmd) {
  1009. case SNDRV_PCM_TRIGGER_START:
  1010. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1011. case SNDRV_PCM_TRIGGER_RESUME:
  1012. /* Enable Audio */
  1013. had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
  1014. had_enable_audio(intelhaddata, true);
  1015. break;
  1016. case SNDRV_PCM_TRIGGER_STOP:
  1017. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1018. /* Disable Audio */
  1019. had_enable_audio(intelhaddata, false);
  1020. intelhaddata->need_reset = true;
  1021. break;
  1022. default:
  1023. retval = -EINVAL;
  1024. }
  1025. spin_unlock(&intelhaddata->had_spinlock);
  1026. return retval;
  1027. }
  1028. /*
  1029. * ALSA PCM prepare callback
  1030. */
  1031. static int had_pcm_prepare(struct snd_pcm_substream *substream)
  1032. {
  1033. int retval;
  1034. u32 disp_samp_freq, n_param;
  1035. u32 link_rate = 0;
  1036. struct snd_intelhad *intelhaddata;
  1037. struct snd_pcm_runtime *runtime;
  1038. intelhaddata = snd_pcm_substream_chip(substream);
  1039. runtime = substream->runtime;
  1040. dev_dbg(intelhaddata->dev, "period_size=%d\n",
  1041. (int)frames_to_bytes(runtime, runtime->period_size));
  1042. dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
  1043. dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
  1044. (int)snd_pcm_lib_buffer_bytes(substream));
  1045. dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
  1046. dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
  1047. had_do_reset(intelhaddata);
  1048. /* Get N value in KHz */
  1049. disp_samp_freq = intelhaddata->tmds_clock_speed;
  1050. retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
  1051. if (retval) {
  1052. dev_err(intelhaddata->dev,
  1053. "programming N value failed %#x\n", retval);
  1054. goto prep_end;
  1055. }
  1056. if (intelhaddata->dp_output)
  1057. link_rate = intelhaddata->link_rate;
  1058. had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
  1059. n_param, intelhaddata);
  1060. had_prog_dip(substream, intelhaddata);
  1061. retval = had_init_audio_ctrl(substream, intelhaddata);
  1062. /* Prog buffer address */
  1063. had_init_ringbuf(substream, intelhaddata);
  1064. /*
  1065. * Program channel mapping in following order:
  1066. * FL, FR, C, LFE, RL, RR
  1067. */
  1068. had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
  1069. prep_end:
  1070. return retval;
  1071. }
  1072. /*
  1073. * ALSA PCM pointer callback
  1074. */
  1075. static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
  1076. {
  1077. struct snd_intelhad *intelhaddata;
  1078. int len;
  1079. intelhaddata = snd_pcm_substream_chip(substream);
  1080. if (!intelhaddata->connected)
  1081. return SNDRV_PCM_POS_XRUN;
  1082. len = had_process_ringbuf(substream, intelhaddata);
  1083. if (len < 0)
  1084. return SNDRV_PCM_POS_XRUN;
  1085. len = bytes_to_frames(substream->runtime, len);
  1086. /* wrapping may happen when periods=1 */
  1087. len %= substream->runtime->buffer_size;
  1088. return len;
  1089. }
  1090. /*
  1091. * ALSA PCM mmap callback
  1092. */
  1093. static int had_pcm_mmap(struct snd_pcm_substream *substream,
  1094. struct vm_area_struct *vma)
  1095. {
  1096. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  1097. return remap_pfn_range(vma, vma->vm_start,
  1098. substream->runtime->dma_addr >> PAGE_SHIFT,
  1099. vma->vm_end - vma->vm_start, vma->vm_page_prot);
  1100. }
  1101. /*
  1102. * ALSA PCM ops
  1103. */
  1104. static const struct snd_pcm_ops had_pcm_ops = {
  1105. .open = had_pcm_open,
  1106. .close = had_pcm_close,
  1107. .hw_params = had_pcm_hw_params,
  1108. .hw_free = had_pcm_hw_free,
  1109. .prepare = had_pcm_prepare,
  1110. .trigger = had_pcm_trigger,
  1111. .pointer = had_pcm_pointer,
  1112. .mmap = had_pcm_mmap,
  1113. };
  1114. /* process mode change of the running stream; called in mutex */
  1115. static int had_process_mode_change(struct snd_intelhad *intelhaddata)
  1116. {
  1117. struct snd_pcm_substream *substream;
  1118. int retval = 0;
  1119. u32 disp_samp_freq, n_param;
  1120. u32 link_rate = 0;
  1121. substream = had_substream_get(intelhaddata);
  1122. if (!substream)
  1123. return 0;
  1124. /* Disable Audio */
  1125. had_enable_audio(intelhaddata, false);
  1126. /* Update CTS value */
  1127. disp_samp_freq = intelhaddata->tmds_clock_speed;
  1128. retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
  1129. if (retval) {
  1130. dev_err(intelhaddata->dev,
  1131. "programming N value failed %#x\n", retval);
  1132. goto out;
  1133. }
  1134. if (intelhaddata->dp_output)
  1135. link_rate = intelhaddata->link_rate;
  1136. had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
  1137. n_param, intelhaddata);
  1138. /* Enable Audio */
  1139. had_enable_audio(intelhaddata, true);
  1140. out:
  1141. had_substream_put(intelhaddata);
  1142. return retval;
  1143. }
  1144. /* process hot plug, called from wq with mutex locked */
  1145. static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
  1146. {
  1147. struct snd_pcm_substream *substream;
  1148. spin_lock_irq(&intelhaddata->had_spinlock);
  1149. if (intelhaddata->connected) {
  1150. dev_dbg(intelhaddata->dev, "Device already connected\n");
  1151. spin_unlock_irq(&intelhaddata->had_spinlock);
  1152. return;
  1153. }
  1154. /* Disable Audio */
  1155. had_enable_audio(intelhaddata, false);
  1156. intelhaddata->connected = true;
  1157. dev_dbg(intelhaddata->dev,
  1158. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
  1159. __func__, __LINE__);
  1160. spin_unlock_irq(&intelhaddata->had_spinlock);
  1161. had_build_channel_allocation_map(intelhaddata);
  1162. /* Report to above ALSA layer */
  1163. substream = had_substream_get(intelhaddata);
  1164. if (substream) {
  1165. snd_pcm_stop_xrun(substream);
  1166. had_substream_put(intelhaddata);
  1167. }
  1168. snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
  1169. }
  1170. /* process hot unplug, called from wq with mutex locked */
  1171. static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
  1172. {
  1173. struct snd_pcm_substream *substream;
  1174. spin_lock_irq(&intelhaddata->had_spinlock);
  1175. if (!intelhaddata->connected) {
  1176. dev_dbg(intelhaddata->dev, "Device already disconnected\n");
  1177. spin_unlock_irq(&intelhaddata->had_spinlock);
  1178. return;
  1179. }
  1180. /* Disable Audio */
  1181. had_enable_audio(intelhaddata, false);
  1182. intelhaddata->connected = false;
  1183. dev_dbg(intelhaddata->dev,
  1184. "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
  1185. __func__, __LINE__);
  1186. spin_unlock_irq(&intelhaddata->had_spinlock);
  1187. kfree(intelhaddata->chmap->chmap);
  1188. intelhaddata->chmap->chmap = NULL;
  1189. /* Report to above ALSA layer */
  1190. substream = had_substream_get(intelhaddata);
  1191. if (substream) {
  1192. snd_pcm_stop_xrun(substream);
  1193. had_substream_put(intelhaddata);
  1194. }
  1195. snd_jack_report(intelhaddata->jack, 0);
  1196. }
  1197. /*
  1198. * ALSA iec958 and ELD controls
  1199. */
  1200. static int had_iec958_info(struct snd_kcontrol *kcontrol,
  1201. struct snd_ctl_elem_info *uinfo)
  1202. {
  1203. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1204. uinfo->count = 1;
  1205. return 0;
  1206. }
  1207. static int had_iec958_get(struct snd_kcontrol *kcontrol,
  1208. struct snd_ctl_elem_value *ucontrol)
  1209. {
  1210. struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
  1211. mutex_lock(&intelhaddata->mutex);
  1212. ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
  1213. ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
  1214. ucontrol->value.iec958.status[2] =
  1215. (intelhaddata->aes_bits >> 16) & 0xff;
  1216. ucontrol->value.iec958.status[3] =
  1217. (intelhaddata->aes_bits >> 24) & 0xff;
  1218. mutex_unlock(&intelhaddata->mutex);
  1219. return 0;
  1220. }
  1221. static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
  1222. struct snd_ctl_elem_value *ucontrol)
  1223. {
  1224. ucontrol->value.iec958.status[0] = 0xff;
  1225. ucontrol->value.iec958.status[1] = 0xff;
  1226. ucontrol->value.iec958.status[2] = 0xff;
  1227. ucontrol->value.iec958.status[3] = 0xff;
  1228. return 0;
  1229. }
  1230. static int had_iec958_put(struct snd_kcontrol *kcontrol,
  1231. struct snd_ctl_elem_value *ucontrol)
  1232. {
  1233. unsigned int val;
  1234. struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
  1235. int changed = 0;
  1236. val = (ucontrol->value.iec958.status[0] << 0) |
  1237. (ucontrol->value.iec958.status[1] << 8) |
  1238. (ucontrol->value.iec958.status[2] << 16) |
  1239. (ucontrol->value.iec958.status[3] << 24);
  1240. mutex_lock(&intelhaddata->mutex);
  1241. if (intelhaddata->aes_bits != val) {
  1242. intelhaddata->aes_bits = val;
  1243. changed = 1;
  1244. }
  1245. mutex_unlock(&intelhaddata->mutex);
  1246. return changed;
  1247. }
  1248. static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
  1249. struct snd_ctl_elem_info *uinfo)
  1250. {
  1251. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1252. uinfo->count = HDMI_MAX_ELD_BYTES;
  1253. return 0;
  1254. }
  1255. static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
  1256. struct snd_ctl_elem_value *ucontrol)
  1257. {
  1258. struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
  1259. mutex_lock(&intelhaddata->mutex);
  1260. memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
  1261. HDMI_MAX_ELD_BYTES);
  1262. mutex_unlock(&intelhaddata->mutex);
  1263. return 0;
  1264. }
  1265. static const struct snd_kcontrol_new had_controls[] = {
  1266. {
  1267. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1268. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1269. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
  1270. .info = had_iec958_info, /* shared */
  1271. .get = had_iec958_mask_get,
  1272. },
  1273. {
  1274. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1275. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1276. .info = had_iec958_info,
  1277. .get = had_iec958_get,
  1278. .put = had_iec958_put,
  1279. },
  1280. {
  1281. .access = (SNDRV_CTL_ELEM_ACCESS_READ |
  1282. SNDRV_CTL_ELEM_ACCESS_VOLATILE),
  1283. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1284. .name = "ELD",
  1285. .info = had_ctl_eld_info,
  1286. .get = had_ctl_eld_get,
  1287. },
  1288. };
  1289. /*
  1290. * audio interrupt handler
  1291. */
  1292. static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
  1293. {
  1294. struct snd_intelhad_card *card_ctx = dev_id;
  1295. u32 audio_stat[3] = {};
  1296. int pipe, port;
  1297. for_each_pipe(card_ctx, pipe) {
  1298. /* use raw register access to ack IRQs even while disconnected */
  1299. audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
  1300. AUD_HDMI_STATUS) &
  1301. (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
  1302. if (audio_stat[pipe])
  1303. had_write_register_raw(card_ctx, pipe,
  1304. AUD_HDMI_STATUS, audio_stat[pipe]);
  1305. }
  1306. for_each_port(card_ctx, port) {
  1307. struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
  1308. int pipe = ctx->pipe;
  1309. if (pipe < 0)
  1310. continue;
  1311. if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
  1312. had_process_buffer_done(ctx);
  1313. if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
  1314. had_process_buffer_underrun(ctx);
  1315. }
  1316. return IRQ_HANDLED;
  1317. }
  1318. /*
  1319. * monitor plug/unplug notification from i915; just kick off the work
  1320. */
  1321. static void notify_audio_lpe(struct platform_device *pdev, int port)
  1322. {
  1323. struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
  1324. struct snd_intelhad *ctx;
  1325. ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
  1326. if (single_port)
  1327. ctx->port = port;
  1328. schedule_work(&ctx->hdmi_audio_wq);
  1329. }
  1330. /* the work to handle monitor hot plug/unplug */
  1331. static void had_audio_wq(struct work_struct *work)
  1332. {
  1333. struct snd_intelhad *ctx =
  1334. container_of(work, struct snd_intelhad, hdmi_audio_wq);
  1335. struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
  1336. struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
  1337. pm_runtime_get_sync(ctx->dev);
  1338. mutex_lock(&ctx->mutex);
  1339. if (ppdata->pipe < 0) {
  1340. dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
  1341. __func__, ctx->port);
  1342. memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
  1343. ctx->dp_output = false;
  1344. ctx->tmds_clock_speed = 0;
  1345. ctx->link_rate = 0;
  1346. /* Shut down the stream */
  1347. had_process_hot_unplug(ctx);
  1348. ctx->pipe = -1;
  1349. } else {
  1350. dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
  1351. __func__, ctx->port, ppdata->ls_clock);
  1352. memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
  1353. ctx->dp_output = ppdata->dp_output;
  1354. if (ctx->dp_output) {
  1355. ctx->tmds_clock_speed = 0;
  1356. ctx->link_rate = ppdata->ls_clock;
  1357. } else {
  1358. ctx->tmds_clock_speed = ppdata->ls_clock;
  1359. ctx->link_rate = 0;
  1360. }
  1361. /*
  1362. * Shut down the stream before we change
  1363. * the pipe assignment for this pcm device
  1364. */
  1365. had_process_hot_plug(ctx);
  1366. ctx->pipe = ppdata->pipe;
  1367. /* Restart the stream if necessary */
  1368. had_process_mode_change(ctx);
  1369. }
  1370. mutex_unlock(&ctx->mutex);
  1371. pm_runtime_mark_last_busy(ctx->dev);
  1372. pm_runtime_put_autosuspend(ctx->dev);
  1373. }
  1374. /*
  1375. * Jack interface
  1376. */
  1377. static int had_create_jack(struct snd_intelhad *ctx,
  1378. struct snd_pcm *pcm)
  1379. {
  1380. char hdmi_str[32];
  1381. int err;
  1382. snprintf(hdmi_str, sizeof(hdmi_str),
  1383. "HDMI/DP,pcm=%d", pcm->device);
  1384. err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
  1385. SND_JACK_AVOUT, &ctx->jack,
  1386. true, false);
  1387. if (err < 0)
  1388. return err;
  1389. ctx->jack->private_data = ctx;
  1390. return 0;
  1391. }
  1392. /*
  1393. * PM callbacks
  1394. */
  1395. static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
  1396. {
  1397. struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
  1398. snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
  1399. return 0;
  1400. }
  1401. static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
  1402. {
  1403. struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
  1404. pm_runtime_mark_last_busy(dev);
  1405. snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
  1406. return 0;
  1407. }
  1408. /* release resources */
  1409. static void hdmi_lpe_audio_free(struct snd_card *card)
  1410. {
  1411. struct snd_intelhad_card *card_ctx = card->private_data;
  1412. struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
  1413. int port;
  1414. spin_lock_irq(&pdata->lpe_audio_slock);
  1415. pdata->notify_audio_lpe = NULL;
  1416. spin_unlock_irq(&pdata->lpe_audio_slock);
  1417. for_each_port(card_ctx, port) {
  1418. struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
  1419. cancel_work_sync(&ctx->hdmi_audio_wq);
  1420. }
  1421. if (card_ctx->mmio_start)
  1422. iounmap(card_ctx->mmio_start);
  1423. if (card_ctx->irq >= 0)
  1424. free_irq(card_ctx->irq, card_ctx);
  1425. }
  1426. /*
  1427. * hdmi_lpe_audio_probe - start bridge with i915
  1428. *
  1429. * This function is called when the i915 driver creates the
  1430. * hdmi-lpe-audio platform device.
  1431. */
  1432. static int hdmi_lpe_audio_probe(struct platform_device *pdev)
  1433. {
  1434. struct snd_card *card;
  1435. struct snd_intelhad_card *card_ctx;
  1436. struct snd_intelhad *ctx;
  1437. struct snd_pcm *pcm;
  1438. struct intel_hdmi_lpe_audio_pdata *pdata;
  1439. int irq;
  1440. struct resource *res_mmio;
  1441. int port, ret;
  1442. pdata = pdev->dev.platform_data;
  1443. if (!pdata) {
  1444. dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
  1445. return -EINVAL;
  1446. }
  1447. /* get resources */
  1448. irq = platform_get_irq(pdev, 0);
  1449. if (irq < 0)
  1450. return irq;
  1451. res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1452. if (!res_mmio) {
  1453. dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
  1454. return -ENXIO;
  1455. }
  1456. /* create a card instance with ALSA framework */
  1457. ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
  1458. THIS_MODULE, sizeof(*card_ctx), &card);
  1459. if (ret)
  1460. return ret;
  1461. card_ctx = card->private_data;
  1462. card_ctx->dev = &pdev->dev;
  1463. card_ctx->card = card;
  1464. strcpy(card->driver, INTEL_HAD);
  1465. strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
  1466. strcpy(card->longname, "Intel HDMI/DP LPE Audio");
  1467. card_ctx->irq = -1;
  1468. card->private_free = hdmi_lpe_audio_free;
  1469. platform_set_drvdata(pdev, card_ctx);
  1470. card_ctx->num_pipes = pdata->num_pipes;
  1471. card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
  1472. for_each_port(card_ctx, port) {
  1473. ctx = &card_ctx->pcm_ctx[port];
  1474. ctx->card_ctx = card_ctx;
  1475. ctx->dev = card_ctx->dev;
  1476. ctx->port = single_port ? -1 : port;
  1477. ctx->pipe = -1;
  1478. spin_lock_init(&ctx->had_spinlock);
  1479. mutex_init(&ctx->mutex);
  1480. INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
  1481. }
  1482. dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
  1483. __func__, (unsigned int)res_mmio->start,
  1484. (unsigned int)res_mmio->end);
  1485. card_ctx->mmio_start = ioremap(res_mmio->start,
  1486. (size_t)(resource_size(res_mmio)));
  1487. if (!card_ctx->mmio_start) {
  1488. dev_err(&pdev->dev, "Could not get ioremap\n");
  1489. ret = -EACCES;
  1490. goto err;
  1491. }
  1492. /* setup interrupt handler */
  1493. ret = request_irq(irq, display_pipe_interrupt_handler, 0,
  1494. pdev->name, card_ctx);
  1495. if (ret < 0) {
  1496. dev_err(&pdev->dev, "request_irq failed\n");
  1497. goto err;
  1498. }
  1499. card_ctx->irq = irq;
  1500. /* only 32bit addressable */
  1501. dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  1502. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  1503. init_channel_allocations();
  1504. card_ctx->num_pipes = pdata->num_pipes;
  1505. card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
  1506. for_each_port(card_ctx, port) {
  1507. int i;
  1508. ctx = &card_ctx->pcm_ctx[port];
  1509. ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
  1510. MAX_CAP_STREAMS, &pcm);
  1511. if (ret)
  1512. goto err;
  1513. /* setup private data which can be retrieved when required */
  1514. pcm->private_data = ctx;
  1515. pcm->info_flags = 0;
  1516. strlcpy(pcm->name, card->shortname, strlen(card->shortname));
  1517. /* setup the ops for playabck */
  1518. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
  1519. /* allocate dma pages;
  1520. * try to allocate 600k buffer as default which is large enough
  1521. */
  1522. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_UC,
  1523. card->dev, HAD_DEFAULT_BUFFER,
  1524. HAD_MAX_BUFFER);
  1525. /* create controls */
  1526. for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
  1527. struct snd_kcontrol *kctl;
  1528. kctl = snd_ctl_new1(&had_controls[i], ctx);
  1529. if (!kctl) {
  1530. ret = -ENOMEM;
  1531. goto err;
  1532. }
  1533. kctl->id.device = pcm->device;
  1534. ret = snd_ctl_add(card, kctl);
  1535. if (ret < 0)
  1536. goto err;
  1537. }
  1538. /* Register channel map controls */
  1539. ret = had_register_chmap_ctls(ctx, pcm);
  1540. if (ret < 0)
  1541. goto err;
  1542. ret = had_create_jack(ctx, pcm);
  1543. if (ret < 0)
  1544. goto err;
  1545. }
  1546. ret = snd_card_register(card);
  1547. if (ret)
  1548. goto err;
  1549. spin_lock_irq(&pdata->lpe_audio_slock);
  1550. pdata->notify_audio_lpe = notify_audio_lpe;
  1551. spin_unlock_irq(&pdata->lpe_audio_slock);
  1552. pm_runtime_use_autosuspend(&pdev->dev);
  1553. pm_runtime_mark_last_busy(&pdev->dev);
  1554. dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
  1555. for_each_port(card_ctx, port) {
  1556. struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
  1557. schedule_work(&ctx->hdmi_audio_wq);
  1558. }
  1559. return 0;
  1560. err:
  1561. snd_card_free(card);
  1562. return ret;
  1563. }
  1564. /*
  1565. * hdmi_lpe_audio_remove - stop bridge with i915
  1566. *
  1567. * This function is called when the platform device is destroyed.
  1568. */
  1569. static int hdmi_lpe_audio_remove(struct platform_device *pdev)
  1570. {
  1571. struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
  1572. snd_card_free(card_ctx->card);
  1573. return 0;
  1574. }
  1575. static const struct dev_pm_ops hdmi_lpe_audio_pm = {
  1576. SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
  1577. };
  1578. static struct platform_driver hdmi_lpe_audio_driver = {
  1579. .driver = {
  1580. .name = "hdmi-lpe-audio",
  1581. .pm = &hdmi_lpe_audio_pm,
  1582. },
  1583. .probe = hdmi_lpe_audio_probe,
  1584. .remove = hdmi_lpe_audio_remove,
  1585. };
  1586. module_platform_driver(hdmi_lpe_audio_driver);
  1587. MODULE_ALIAS("platform:hdmi_lpe_audio");
  1588. MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
  1589. MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
  1590. MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
  1591. MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
  1592. MODULE_DESCRIPTION("Intel HDMI Audio driver");
  1593. MODULE_LICENSE("GPL v2");
  1594. MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");