cs4231.c 56 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for CS4231 sound chips found on Sparcs.
  4. * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  5. *
  6. * Based entirely upon drivers/sbus/audio/cs4231.c which is:
  7. * Copyright (C) 1996, 1997, 1998 Derrick J Brashear (shadow@andrew.cmu.edu)
  8. * and also sound/isa/cs423x/cs4231_lib.c which is:
  9. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/irq.h>
  18. #include <linux/io.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/info.h>
  24. #include <sound/control.h>
  25. #include <sound/timer.h>
  26. #include <sound/initval.h>
  27. #include <sound/pcm_params.h>
  28. #ifdef CONFIG_SBUS
  29. #define SBUS_SUPPORT
  30. #endif
  31. #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
  32. #define EBUS_SUPPORT
  33. #include <linux/pci.h>
  34. #include <asm/ebus_dma.h>
  35. #endif
  36. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  37. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  38. /* Enable this card */
  39. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  40. module_param_array(index, int, NULL, 0444);
  41. MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard.");
  42. module_param_array(id, charp, NULL, 0444);
  43. MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard.");
  44. module_param_array(enable, bool, NULL, 0444);
  45. MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard.");
  46. MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller");
  47. MODULE_DESCRIPTION("Sun CS4231");
  48. MODULE_LICENSE("GPL");
  49. MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}");
  50. #ifdef SBUS_SUPPORT
  51. struct sbus_dma_info {
  52. spinlock_t lock; /* DMA access lock */
  53. int dir;
  54. void __iomem *regs;
  55. };
  56. #endif
  57. struct snd_cs4231;
  58. struct cs4231_dma_control {
  59. void (*prepare)(struct cs4231_dma_control *dma_cont,
  60. int dir);
  61. void (*enable)(struct cs4231_dma_control *dma_cont, int on);
  62. int (*request)(struct cs4231_dma_control *dma_cont,
  63. dma_addr_t bus_addr, size_t len);
  64. unsigned int (*address)(struct cs4231_dma_control *dma_cont);
  65. #ifdef EBUS_SUPPORT
  66. struct ebus_dma_info ebus_info;
  67. #endif
  68. #ifdef SBUS_SUPPORT
  69. struct sbus_dma_info sbus_info;
  70. #endif
  71. };
  72. struct snd_cs4231 {
  73. spinlock_t lock; /* registers access lock */
  74. void __iomem *port;
  75. struct cs4231_dma_control p_dma;
  76. struct cs4231_dma_control c_dma;
  77. u32 flags;
  78. #define CS4231_FLAG_EBUS 0x00000001
  79. #define CS4231_FLAG_PLAYBACK 0x00000002
  80. #define CS4231_FLAG_CAPTURE 0x00000004
  81. struct snd_card *card;
  82. struct snd_pcm *pcm;
  83. struct snd_pcm_substream *playback_substream;
  84. unsigned int p_periods_sent;
  85. struct snd_pcm_substream *capture_substream;
  86. unsigned int c_periods_sent;
  87. struct snd_timer *timer;
  88. unsigned short mode;
  89. #define CS4231_MODE_NONE 0x0000
  90. #define CS4231_MODE_PLAY 0x0001
  91. #define CS4231_MODE_RECORD 0x0002
  92. #define CS4231_MODE_TIMER 0x0004
  93. #define CS4231_MODE_OPEN (CS4231_MODE_PLAY | CS4231_MODE_RECORD | \
  94. CS4231_MODE_TIMER)
  95. unsigned char image[32]; /* registers image */
  96. int mce_bit;
  97. int calibrate_mute;
  98. struct mutex mce_mutex; /* mutex for mce register */
  99. struct mutex open_mutex; /* mutex for ALSA open/close */
  100. struct platform_device *op;
  101. unsigned int irq[2];
  102. unsigned int regs_size;
  103. struct snd_cs4231 *next;
  104. };
  105. /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for
  106. * now.... -DaveM
  107. */
  108. /* IO ports */
  109. #include <sound/cs4231-regs.h>
  110. /* XXX offsets are different than PC ISA chips... */
  111. #define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
  112. /* SBUS DMA register defines. */
  113. #define APCCSR 0x10UL /* APC DMA CSR */
  114. #define APCCVA 0x20UL /* APC Capture DMA Address */
  115. #define APCCC 0x24UL /* APC Capture Count */
  116. #define APCCNVA 0x28UL /* APC Capture DMA Next Address */
  117. #define APCCNC 0x2cUL /* APC Capture Next Count */
  118. #define APCPVA 0x30UL /* APC Play DMA Address */
  119. #define APCPC 0x34UL /* APC Play Count */
  120. #define APCPNVA 0x38UL /* APC Play DMA Next Address */
  121. #define APCPNC 0x3cUL /* APC Play Next Count */
  122. /* Defines for SBUS DMA-routines */
  123. #define APCVA 0x0UL /* APC DMA Address */
  124. #define APCC 0x4UL /* APC Count */
  125. #define APCNVA 0x8UL /* APC DMA Next Address */
  126. #define APCNC 0xcUL /* APC Next Count */
  127. #define APC_PLAY 0x30UL /* Play registers start at 0x30 */
  128. #define APC_RECORD 0x20UL /* Record registers start at 0x20 */
  129. /* APCCSR bits */
  130. #define APC_INT_PENDING 0x800000 /* Interrupt Pending */
  131. #define APC_PLAY_INT 0x400000 /* Playback interrupt */
  132. #define APC_CAPT_INT 0x200000 /* Capture interrupt */
  133. #define APC_GENL_INT 0x100000 /* General interrupt */
  134. #define APC_XINT_ENA 0x80000 /* General ext int. enable */
  135. #define APC_XINT_PLAY 0x40000 /* Playback ext intr */
  136. #define APC_XINT_CAPT 0x20000 /* Capture ext intr */
  137. #define APC_XINT_GENL 0x10000 /* Error ext intr */
  138. #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
  139. #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
  140. #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
  141. #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
  142. #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
  143. #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
  144. #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
  145. #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
  146. #define APC_PPAUSE 0x80 /* Pause the play DMA */
  147. #define APC_CPAUSE 0x40 /* Pause the capture DMA */
  148. #define APC_CDC_RESET 0x20 /* CODEC RESET */
  149. #define APC_PDMA_READY 0x08 /* Play DMA Go */
  150. #define APC_CDMA_READY 0x04 /* Capture DMA Go */
  151. #define APC_CHIP_RESET 0x01 /* Reset the chip */
  152. /* EBUS DMA register offsets */
  153. #define EBDMA_CSR 0x00UL /* Control/Status */
  154. #define EBDMA_ADDR 0x04UL /* DMA Address */
  155. #define EBDMA_COUNT 0x08UL /* DMA Count */
  156. /*
  157. * Some variables
  158. */
  159. static const unsigned char freq_bits[14] = {
  160. /* 5510 */ 0x00 | CS4231_XTAL2,
  161. /* 6620 */ 0x0E | CS4231_XTAL2,
  162. /* 8000 */ 0x00 | CS4231_XTAL1,
  163. /* 9600 */ 0x0E | CS4231_XTAL1,
  164. /* 11025 */ 0x02 | CS4231_XTAL2,
  165. /* 16000 */ 0x02 | CS4231_XTAL1,
  166. /* 18900 */ 0x04 | CS4231_XTAL2,
  167. /* 22050 */ 0x06 | CS4231_XTAL2,
  168. /* 27042 */ 0x04 | CS4231_XTAL1,
  169. /* 32000 */ 0x06 | CS4231_XTAL1,
  170. /* 33075 */ 0x0C | CS4231_XTAL2,
  171. /* 37800 */ 0x08 | CS4231_XTAL2,
  172. /* 44100 */ 0x0A | CS4231_XTAL2,
  173. /* 48000 */ 0x0C | CS4231_XTAL1
  174. };
  175. static const unsigned int rates[14] = {
  176. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  177. 27042, 32000, 33075, 37800, 44100, 48000
  178. };
  179. static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  180. .count = ARRAY_SIZE(rates),
  181. .list = rates,
  182. };
  183. static int snd_cs4231_xrate(struct snd_pcm_runtime *runtime)
  184. {
  185. return snd_pcm_hw_constraint_list(runtime, 0,
  186. SNDRV_PCM_HW_PARAM_RATE,
  187. &hw_constraints_rates);
  188. }
  189. static const unsigned char snd_cs4231_original_image[32] =
  190. {
  191. 0x00, /* 00/00 - lic */
  192. 0x00, /* 01/01 - ric */
  193. 0x9f, /* 02/02 - la1ic */
  194. 0x9f, /* 03/03 - ra1ic */
  195. 0x9f, /* 04/04 - la2ic */
  196. 0x9f, /* 05/05 - ra2ic */
  197. 0xbf, /* 06/06 - loc */
  198. 0xbf, /* 07/07 - roc */
  199. 0x20, /* 08/08 - pdfr */
  200. CS4231_AUTOCALIB, /* 09/09 - ic */
  201. 0x00, /* 0a/10 - pc */
  202. 0x00, /* 0b/11 - ti */
  203. CS4231_MODE2, /* 0c/12 - mi */
  204. 0x00, /* 0d/13 - lbc */
  205. 0x00, /* 0e/14 - pbru */
  206. 0x00, /* 0f/15 - pbrl */
  207. 0x80, /* 10/16 - afei */
  208. 0x01, /* 11/17 - afeii */
  209. 0x9f, /* 12/18 - llic */
  210. 0x9f, /* 13/19 - rlic */
  211. 0x00, /* 14/20 - tlb */
  212. 0x00, /* 15/21 - thb */
  213. 0x00, /* 16/22 - la3mic/reserved */
  214. 0x00, /* 17/23 - ra3mic/reserved */
  215. 0x00, /* 18/24 - afs */
  216. 0x00, /* 19/25 - lamoc/version */
  217. 0x00, /* 1a/26 - mioc */
  218. 0x00, /* 1b/27 - ramoc/reserved */
  219. 0x20, /* 1c/28 - cdfr */
  220. 0x00, /* 1d/29 - res4 */
  221. 0x00, /* 1e/30 - cbru */
  222. 0x00, /* 1f/31 - cbrl */
  223. };
  224. static u8 __cs4231_readb(struct snd_cs4231 *cp, void __iomem *reg_addr)
  225. {
  226. if (cp->flags & CS4231_FLAG_EBUS)
  227. return readb(reg_addr);
  228. else
  229. return sbus_readb(reg_addr);
  230. }
  231. static void __cs4231_writeb(struct snd_cs4231 *cp, u8 val,
  232. void __iomem *reg_addr)
  233. {
  234. if (cp->flags & CS4231_FLAG_EBUS)
  235. return writeb(val, reg_addr);
  236. else
  237. return sbus_writeb(val, reg_addr);
  238. }
  239. /*
  240. * Basic I/O functions
  241. */
  242. static void snd_cs4231_ready(struct snd_cs4231 *chip)
  243. {
  244. int timeout;
  245. for (timeout = 250; timeout > 0; timeout--) {
  246. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  247. if ((val & CS4231_INIT) == 0)
  248. break;
  249. udelay(100);
  250. }
  251. }
  252. static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
  253. unsigned char value)
  254. {
  255. snd_cs4231_ready(chip);
  256. #ifdef CONFIG_SND_DEBUG
  257. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  258. snd_printdd("out: auto calibration time out - reg = 0x%x, "
  259. "value = 0x%x\n",
  260. reg, value);
  261. #endif
  262. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  263. wmb();
  264. __cs4231_writeb(chip, value, CS4231U(chip, REG));
  265. mb();
  266. }
  267. static inline void snd_cs4231_outm(struct snd_cs4231 *chip, unsigned char reg,
  268. unsigned char mask, unsigned char value)
  269. {
  270. unsigned char tmp = (chip->image[reg] & mask) | value;
  271. chip->image[reg] = tmp;
  272. if (!chip->calibrate_mute)
  273. snd_cs4231_dout(chip, reg, tmp);
  274. }
  275. static void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg,
  276. unsigned char value)
  277. {
  278. snd_cs4231_dout(chip, reg, value);
  279. chip->image[reg] = value;
  280. mb();
  281. }
  282. static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
  283. {
  284. snd_cs4231_ready(chip);
  285. #ifdef CONFIG_SND_DEBUG
  286. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  287. snd_printdd("in: auto calibration time out - reg = 0x%x\n",
  288. reg);
  289. #endif
  290. __cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
  291. mb();
  292. return __cs4231_readb(chip, CS4231U(chip, REG));
  293. }
  294. /*
  295. * CS4231 detection / MCE routines
  296. */
  297. static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
  298. {
  299. int timeout;
  300. /* looks like this sequence is proper for CS4231A chip (GUS MAX) */
  301. for (timeout = 5; timeout > 0; timeout--)
  302. __cs4231_readb(chip, CS4231U(chip, REGSEL));
  303. /* end of cleanup sequence */
  304. for (timeout = 500; timeout > 0; timeout--) {
  305. int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  306. if ((val & CS4231_INIT) == 0)
  307. break;
  308. msleep(1);
  309. }
  310. }
  311. static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
  312. {
  313. unsigned long flags;
  314. int timeout;
  315. spin_lock_irqsave(&chip->lock, flags);
  316. snd_cs4231_ready(chip);
  317. #ifdef CONFIG_SND_DEBUG
  318. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  319. snd_printdd("mce_up - auto calibration time out (0)\n");
  320. #endif
  321. chip->mce_bit |= CS4231_MCE;
  322. timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  323. if (timeout == 0x80)
  324. snd_printdd("mce_up [%p]: serious init problem - "
  325. "codec still busy\n",
  326. chip->port);
  327. if (!(timeout & CS4231_MCE))
  328. __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
  329. CS4231U(chip, REGSEL));
  330. spin_unlock_irqrestore(&chip->lock, flags);
  331. }
  332. static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
  333. {
  334. unsigned long flags, timeout;
  335. int reg;
  336. snd_cs4231_busy_wait(chip);
  337. spin_lock_irqsave(&chip->lock, flags);
  338. #ifdef CONFIG_SND_DEBUG
  339. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  340. snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
  341. CS4231U(chip, REGSEL));
  342. #endif
  343. chip->mce_bit &= ~CS4231_MCE;
  344. reg = __cs4231_readb(chip, CS4231U(chip, REGSEL));
  345. __cs4231_writeb(chip, chip->mce_bit | (reg & 0x1f),
  346. CS4231U(chip, REGSEL));
  347. if (reg == 0x80)
  348. snd_printdd("mce_down [%p]: serious init problem "
  349. "- codec still busy\n", chip->port);
  350. if ((reg & CS4231_MCE) == 0) {
  351. spin_unlock_irqrestore(&chip->lock, flags);
  352. return;
  353. }
  354. /*
  355. * Wait for auto-calibration (AC) process to finish, i.e. ACI to go low.
  356. */
  357. timeout = jiffies + msecs_to_jiffies(250);
  358. do {
  359. spin_unlock_irqrestore(&chip->lock, flags);
  360. msleep(1);
  361. spin_lock_irqsave(&chip->lock, flags);
  362. reg = snd_cs4231_in(chip, CS4231_TEST_INIT);
  363. reg &= CS4231_CALIB_IN_PROGRESS;
  364. } while (reg && time_before(jiffies, timeout));
  365. spin_unlock_irqrestore(&chip->lock, flags);
  366. if (reg)
  367. snd_printk(KERN_ERR
  368. "mce_down - auto calibration time out (2)\n");
  369. }
  370. static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont,
  371. struct snd_pcm_substream *substream,
  372. unsigned int *periods_sent)
  373. {
  374. struct snd_pcm_runtime *runtime = substream->runtime;
  375. while (1) {
  376. unsigned int period_size = snd_pcm_lib_period_bytes(substream);
  377. unsigned int offset = period_size * (*periods_sent);
  378. if (WARN_ON(period_size >= (1 << 24)))
  379. return;
  380. if (dma_cont->request(dma_cont,
  381. runtime->dma_addr + offset, period_size))
  382. return;
  383. (*periods_sent) = ((*periods_sent) + 1) % runtime->periods;
  384. }
  385. }
  386. static void cs4231_dma_trigger(struct snd_pcm_substream *substream,
  387. unsigned int what, int on)
  388. {
  389. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  390. struct cs4231_dma_control *dma_cont;
  391. if (what & CS4231_PLAYBACK_ENABLE) {
  392. dma_cont = &chip->p_dma;
  393. if (on) {
  394. dma_cont->prepare(dma_cont, 0);
  395. dma_cont->enable(dma_cont, 1);
  396. snd_cs4231_advance_dma(dma_cont,
  397. chip->playback_substream,
  398. &chip->p_periods_sent);
  399. } else {
  400. dma_cont->enable(dma_cont, 0);
  401. }
  402. }
  403. if (what & CS4231_RECORD_ENABLE) {
  404. dma_cont = &chip->c_dma;
  405. if (on) {
  406. dma_cont->prepare(dma_cont, 1);
  407. dma_cont->enable(dma_cont, 1);
  408. snd_cs4231_advance_dma(dma_cont,
  409. chip->capture_substream,
  410. &chip->c_periods_sent);
  411. } else {
  412. dma_cont->enable(dma_cont, 0);
  413. }
  414. }
  415. }
  416. static int snd_cs4231_trigger(struct snd_pcm_substream *substream, int cmd)
  417. {
  418. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  419. int result = 0;
  420. switch (cmd) {
  421. case SNDRV_PCM_TRIGGER_START:
  422. case SNDRV_PCM_TRIGGER_STOP:
  423. {
  424. unsigned int what = 0;
  425. struct snd_pcm_substream *s;
  426. unsigned long flags;
  427. snd_pcm_group_for_each_entry(s, substream) {
  428. if (s == chip->playback_substream) {
  429. what |= CS4231_PLAYBACK_ENABLE;
  430. snd_pcm_trigger_done(s, substream);
  431. } else if (s == chip->capture_substream) {
  432. what |= CS4231_RECORD_ENABLE;
  433. snd_pcm_trigger_done(s, substream);
  434. }
  435. }
  436. spin_lock_irqsave(&chip->lock, flags);
  437. if (cmd == SNDRV_PCM_TRIGGER_START) {
  438. cs4231_dma_trigger(substream, what, 1);
  439. chip->image[CS4231_IFACE_CTRL] |= what;
  440. } else {
  441. cs4231_dma_trigger(substream, what, 0);
  442. chip->image[CS4231_IFACE_CTRL] &= ~what;
  443. }
  444. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  445. chip->image[CS4231_IFACE_CTRL]);
  446. spin_unlock_irqrestore(&chip->lock, flags);
  447. break;
  448. }
  449. default:
  450. result = -EINVAL;
  451. break;
  452. }
  453. return result;
  454. }
  455. /*
  456. * CODEC I/O
  457. */
  458. static unsigned char snd_cs4231_get_rate(unsigned int rate)
  459. {
  460. int i;
  461. for (i = 0; i < 14; i++)
  462. if (rate == rates[i])
  463. return freq_bits[i];
  464. return freq_bits[13];
  465. }
  466. static unsigned char snd_cs4231_get_format(struct snd_cs4231 *chip, int format,
  467. int channels)
  468. {
  469. unsigned char rformat;
  470. rformat = CS4231_LINEAR_8;
  471. switch (format) {
  472. case SNDRV_PCM_FORMAT_MU_LAW:
  473. rformat = CS4231_ULAW_8;
  474. break;
  475. case SNDRV_PCM_FORMAT_A_LAW:
  476. rformat = CS4231_ALAW_8;
  477. break;
  478. case SNDRV_PCM_FORMAT_S16_LE:
  479. rformat = CS4231_LINEAR_16;
  480. break;
  481. case SNDRV_PCM_FORMAT_S16_BE:
  482. rformat = CS4231_LINEAR_16_BIG;
  483. break;
  484. case SNDRV_PCM_FORMAT_IMA_ADPCM:
  485. rformat = CS4231_ADPCM_16;
  486. break;
  487. }
  488. if (channels > 1)
  489. rformat |= CS4231_STEREO;
  490. return rformat;
  491. }
  492. static void snd_cs4231_calibrate_mute(struct snd_cs4231 *chip, int mute)
  493. {
  494. unsigned long flags;
  495. mute = mute ? 1 : 0;
  496. spin_lock_irqsave(&chip->lock, flags);
  497. if (chip->calibrate_mute == mute) {
  498. spin_unlock_irqrestore(&chip->lock, flags);
  499. return;
  500. }
  501. if (!mute) {
  502. snd_cs4231_dout(chip, CS4231_LEFT_INPUT,
  503. chip->image[CS4231_LEFT_INPUT]);
  504. snd_cs4231_dout(chip, CS4231_RIGHT_INPUT,
  505. chip->image[CS4231_RIGHT_INPUT]);
  506. snd_cs4231_dout(chip, CS4231_LOOPBACK,
  507. chip->image[CS4231_LOOPBACK]);
  508. }
  509. snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT,
  510. mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]);
  511. snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT,
  512. mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]);
  513. snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT,
  514. mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]);
  515. snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT,
  516. mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]);
  517. snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT,
  518. mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]);
  519. snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT,
  520. mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]);
  521. snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN,
  522. mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]);
  523. snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN,
  524. mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]);
  525. snd_cs4231_dout(chip, CS4231_MONO_CTRL,
  526. mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
  527. chip->calibrate_mute = mute;
  528. spin_unlock_irqrestore(&chip->lock, flags);
  529. }
  530. static void snd_cs4231_playback_format(struct snd_cs4231 *chip,
  531. struct snd_pcm_hw_params *params,
  532. unsigned char pdfr)
  533. {
  534. unsigned long flags;
  535. mutex_lock(&chip->mce_mutex);
  536. snd_cs4231_calibrate_mute(chip, 1);
  537. snd_cs4231_mce_up(chip);
  538. spin_lock_irqsave(&chip->lock, flags);
  539. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  540. (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ?
  541. (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) :
  542. pdfr);
  543. spin_unlock_irqrestore(&chip->lock, flags);
  544. snd_cs4231_mce_down(chip);
  545. snd_cs4231_calibrate_mute(chip, 0);
  546. mutex_unlock(&chip->mce_mutex);
  547. }
  548. static void snd_cs4231_capture_format(struct snd_cs4231 *chip,
  549. struct snd_pcm_hw_params *params,
  550. unsigned char cdfr)
  551. {
  552. unsigned long flags;
  553. mutex_lock(&chip->mce_mutex);
  554. snd_cs4231_calibrate_mute(chip, 1);
  555. snd_cs4231_mce_up(chip);
  556. spin_lock_irqsave(&chip->lock, flags);
  557. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
  558. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  559. ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) |
  560. (cdfr & 0x0f));
  561. spin_unlock_irqrestore(&chip->lock, flags);
  562. snd_cs4231_mce_down(chip);
  563. snd_cs4231_mce_up(chip);
  564. spin_lock_irqsave(&chip->lock, flags);
  565. }
  566. snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr);
  567. spin_unlock_irqrestore(&chip->lock, flags);
  568. snd_cs4231_mce_down(chip);
  569. snd_cs4231_calibrate_mute(chip, 0);
  570. mutex_unlock(&chip->mce_mutex);
  571. }
  572. /*
  573. * Timer interface
  574. */
  575. static unsigned long snd_cs4231_timer_resolution(struct snd_timer *timer)
  576. {
  577. struct snd_cs4231 *chip = snd_timer_chip(timer);
  578. return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
  579. }
  580. static int snd_cs4231_timer_start(struct snd_timer *timer)
  581. {
  582. unsigned long flags;
  583. unsigned int ticks;
  584. struct snd_cs4231 *chip = snd_timer_chip(timer);
  585. spin_lock_irqsave(&chip->lock, flags);
  586. ticks = timer->sticks;
  587. if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
  588. (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
  589. (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
  590. snd_cs4231_out(chip, CS4231_TIMER_HIGH,
  591. chip->image[CS4231_TIMER_HIGH] =
  592. (unsigned char) (ticks >> 8));
  593. snd_cs4231_out(chip, CS4231_TIMER_LOW,
  594. chip->image[CS4231_TIMER_LOW] =
  595. (unsigned char) ticks);
  596. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  597. chip->image[CS4231_ALT_FEATURE_1] |
  598. CS4231_TIMER_ENABLE);
  599. }
  600. spin_unlock_irqrestore(&chip->lock, flags);
  601. return 0;
  602. }
  603. static int snd_cs4231_timer_stop(struct snd_timer *timer)
  604. {
  605. unsigned long flags;
  606. struct snd_cs4231 *chip = snd_timer_chip(timer);
  607. spin_lock_irqsave(&chip->lock, flags);
  608. chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
  609. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  610. chip->image[CS4231_ALT_FEATURE_1]);
  611. spin_unlock_irqrestore(&chip->lock, flags);
  612. return 0;
  613. }
  614. static void snd_cs4231_init(struct snd_cs4231 *chip)
  615. {
  616. unsigned long flags;
  617. snd_cs4231_mce_down(chip);
  618. #ifdef SNDRV_DEBUG_MCE
  619. snd_printdd("init: (1)\n");
  620. #endif
  621. snd_cs4231_mce_up(chip);
  622. spin_lock_irqsave(&chip->lock, flags);
  623. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  624. CS4231_PLAYBACK_PIO |
  625. CS4231_RECORD_ENABLE |
  626. CS4231_RECORD_PIO |
  627. CS4231_CALIB_MODE);
  628. chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
  629. snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
  630. spin_unlock_irqrestore(&chip->lock, flags);
  631. snd_cs4231_mce_down(chip);
  632. #ifdef SNDRV_DEBUG_MCE
  633. snd_printdd("init: (2)\n");
  634. #endif
  635. snd_cs4231_mce_up(chip);
  636. spin_lock_irqsave(&chip->lock, flags);
  637. snd_cs4231_out(chip, CS4231_ALT_FEATURE_1,
  638. chip->image[CS4231_ALT_FEATURE_1]);
  639. spin_unlock_irqrestore(&chip->lock, flags);
  640. snd_cs4231_mce_down(chip);
  641. #ifdef SNDRV_DEBUG_MCE
  642. snd_printdd("init: (3) - afei = 0x%x\n",
  643. chip->image[CS4231_ALT_FEATURE_1]);
  644. #endif
  645. spin_lock_irqsave(&chip->lock, flags);
  646. snd_cs4231_out(chip, CS4231_ALT_FEATURE_2,
  647. chip->image[CS4231_ALT_FEATURE_2]);
  648. spin_unlock_irqrestore(&chip->lock, flags);
  649. snd_cs4231_mce_up(chip);
  650. spin_lock_irqsave(&chip->lock, flags);
  651. snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT,
  652. chip->image[CS4231_PLAYBK_FORMAT]);
  653. spin_unlock_irqrestore(&chip->lock, flags);
  654. snd_cs4231_mce_down(chip);
  655. #ifdef SNDRV_DEBUG_MCE
  656. snd_printdd("init: (4)\n");
  657. #endif
  658. snd_cs4231_mce_up(chip);
  659. spin_lock_irqsave(&chip->lock, flags);
  660. snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]);
  661. spin_unlock_irqrestore(&chip->lock, flags);
  662. snd_cs4231_mce_down(chip);
  663. #ifdef SNDRV_DEBUG_MCE
  664. snd_printdd("init: (5)\n");
  665. #endif
  666. }
  667. static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
  668. {
  669. unsigned long flags;
  670. mutex_lock(&chip->open_mutex);
  671. if ((chip->mode & mode)) {
  672. mutex_unlock(&chip->open_mutex);
  673. return -EAGAIN;
  674. }
  675. if (chip->mode & CS4231_MODE_OPEN) {
  676. chip->mode |= mode;
  677. mutex_unlock(&chip->open_mutex);
  678. return 0;
  679. }
  680. /* ok. now enable and ack CODEC IRQ */
  681. spin_lock_irqsave(&chip->lock, flags);
  682. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  683. CS4231_RECORD_IRQ |
  684. CS4231_TIMER_IRQ);
  685. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  686. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  687. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  688. snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
  689. CS4231_RECORD_IRQ |
  690. CS4231_TIMER_IRQ);
  691. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  692. spin_unlock_irqrestore(&chip->lock, flags);
  693. chip->mode = mode;
  694. mutex_unlock(&chip->open_mutex);
  695. return 0;
  696. }
  697. static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
  698. {
  699. unsigned long flags;
  700. mutex_lock(&chip->open_mutex);
  701. chip->mode &= ~mode;
  702. if (chip->mode & CS4231_MODE_OPEN) {
  703. mutex_unlock(&chip->open_mutex);
  704. return;
  705. }
  706. snd_cs4231_calibrate_mute(chip, 1);
  707. /* disable IRQ */
  708. spin_lock_irqsave(&chip->lock, flags);
  709. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  710. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  711. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  712. /* now disable record & playback */
  713. if (chip->image[CS4231_IFACE_CTRL] &
  714. (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  715. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
  716. spin_unlock_irqrestore(&chip->lock, flags);
  717. snd_cs4231_mce_up(chip);
  718. spin_lock_irqsave(&chip->lock, flags);
  719. chip->image[CS4231_IFACE_CTRL] &=
  720. ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
  721. CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
  722. snd_cs4231_out(chip, CS4231_IFACE_CTRL,
  723. chip->image[CS4231_IFACE_CTRL]);
  724. spin_unlock_irqrestore(&chip->lock, flags);
  725. snd_cs4231_mce_down(chip);
  726. spin_lock_irqsave(&chip->lock, flags);
  727. }
  728. /* clear IRQ again */
  729. snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
  730. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  731. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
  732. spin_unlock_irqrestore(&chip->lock, flags);
  733. snd_cs4231_calibrate_mute(chip, 0);
  734. chip->mode = 0;
  735. mutex_unlock(&chip->open_mutex);
  736. }
  737. /*
  738. * timer open/close
  739. */
  740. static int snd_cs4231_timer_open(struct snd_timer *timer)
  741. {
  742. struct snd_cs4231 *chip = snd_timer_chip(timer);
  743. snd_cs4231_open(chip, CS4231_MODE_TIMER);
  744. return 0;
  745. }
  746. static int snd_cs4231_timer_close(struct snd_timer *timer)
  747. {
  748. struct snd_cs4231 *chip = snd_timer_chip(timer);
  749. snd_cs4231_close(chip, CS4231_MODE_TIMER);
  750. return 0;
  751. }
  752. static const struct snd_timer_hardware snd_cs4231_timer_table = {
  753. .flags = SNDRV_TIMER_HW_AUTO,
  754. .resolution = 9945,
  755. .ticks = 65535,
  756. .open = snd_cs4231_timer_open,
  757. .close = snd_cs4231_timer_close,
  758. .c_resolution = snd_cs4231_timer_resolution,
  759. .start = snd_cs4231_timer_start,
  760. .stop = snd_cs4231_timer_stop,
  761. };
  762. /*
  763. * ok.. exported functions..
  764. */
  765. static int snd_cs4231_playback_hw_params(struct snd_pcm_substream *substream,
  766. struct snd_pcm_hw_params *hw_params)
  767. {
  768. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  769. unsigned char new_pdfr;
  770. new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  771. params_channels(hw_params)) |
  772. snd_cs4231_get_rate(params_rate(hw_params));
  773. snd_cs4231_playback_format(chip, hw_params, new_pdfr);
  774. return 0;
  775. }
  776. static int snd_cs4231_playback_prepare(struct snd_pcm_substream *substream)
  777. {
  778. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  779. struct snd_pcm_runtime *runtime = substream->runtime;
  780. unsigned long flags;
  781. int ret = 0;
  782. spin_lock_irqsave(&chip->lock, flags);
  783. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
  784. CS4231_PLAYBACK_PIO);
  785. if (WARN_ON(runtime->period_size > 0xffff + 1)) {
  786. ret = -EINVAL;
  787. goto out;
  788. }
  789. chip->p_periods_sent = 0;
  790. out:
  791. spin_unlock_irqrestore(&chip->lock, flags);
  792. return ret;
  793. }
  794. static int snd_cs4231_capture_hw_params(struct snd_pcm_substream *substream,
  795. struct snd_pcm_hw_params *hw_params)
  796. {
  797. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  798. unsigned char new_cdfr;
  799. new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params),
  800. params_channels(hw_params)) |
  801. snd_cs4231_get_rate(params_rate(hw_params));
  802. snd_cs4231_capture_format(chip, hw_params, new_cdfr);
  803. return 0;
  804. }
  805. static int snd_cs4231_capture_prepare(struct snd_pcm_substream *substream)
  806. {
  807. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  808. unsigned long flags;
  809. spin_lock_irqsave(&chip->lock, flags);
  810. chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE |
  811. CS4231_RECORD_PIO);
  812. chip->c_periods_sent = 0;
  813. spin_unlock_irqrestore(&chip->lock, flags);
  814. return 0;
  815. }
  816. static void snd_cs4231_overrange(struct snd_cs4231 *chip)
  817. {
  818. unsigned long flags;
  819. unsigned char res;
  820. spin_lock_irqsave(&chip->lock, flags);
  821. res = snd_cs4231_in(chip, CS4231_TEST_INIT);
  822. spin_unlock_irqrestore(&chip->lock, flags);
  823. /* detect overrange only above 0dB; may be user selectable? */
  824. if (res & (0x08 | 0x02))
  825. chip->capture_substream->runtime->overrange++;
  826. }
  827. static void snd_cs4231_play_callback(struct snd_cs4231 *chip)
  828. {
  829. if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) {
  830. snd_pcm_period_elapsed(chip->playback_substream);
  831. snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream,
  832. &chip->p_periods_sent);
  833. }
  834. }
  835. static void snd_cs4231_capture_callback(struct snd_cs4231 *chip)
  836. {
  837. if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) {
  838. snd_pcm_period_elapsed(chip->capture_substream);
  839. snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream,
  840. &chip->c_periods_sent);
  841. }
  842. }
  843. static snd_pcm_uframes_t snd_cs4231_playback_pointer(
  844. struct snd_pcm_substream *substream)
  845. {
  846. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  847. struct cs4231_dma_control *dma_cont = &chip->p_dma;
  848. size_t ptr;
  849. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
  850. return 0;
  851. ptr = dma_cont->address(dma_cont);
  852. if (ptr != 0)
  853. ptr -= substream->runtime->dma_addr;
  854. return bytes_to_frames(substream->runtime, ptr);
  855. }
  856. static snd_pcm_uframes_t snd_cs4231_capture_pointer(
  857. struct snd_pcm_substream *substream)
  858. {
  859. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  860. struct cs4231_dma_control *dma_cont = &chip->c_dma;
  861. size_t ptr;
  862. if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
  863. return 0;
  864. ptr = dma_cont->address(dma_cont);
  865. if (ptr != 0)
  866. ptr -= substream->runtime->dma_addr;
  867. return bytes_to_frames(substream->runtime, ptr);
  868. }
  869. static int snd_cs4231_probe(struct snd_cs4231 *chip)
  870. {
  871. unsigned long flags;
  872. int i;
  873. int id = 0;
  874. int vers = 0;
  875. unsigned char *ptr;
  876. for (i = 0; i < 50; i++) {
  877. mb();
  878. if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
  879. msleep(2);
  880. else {
  881. spin_lock_irqsave(&chip->lock, flags);
  882. snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2);
  883. id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f;
  884. vers = snd_cs4231_in(chip, CS4231_VERSION);
  885. spin_unlock_irqrestore(&chip->lock, flags);
  886. if (id == 0x0a)
  887. break; /* this is valid value */
  888. }
  889. }
  890. snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id);
  891. if (id != 0x0a)
  892. return -ENODEV; /* no valid device found */
  893. spin_lock_irqsave(&chip->lock, flags);
  894. /* clear any pendings IRQ */
  895. __cs4231_readb(chip, CS4231U(chip, STATUS));
  896. __cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
  897. mb();
  898. spin_unlock_irqrestore(&chip->lock, flags);
  899. chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
  900. chip->image[CS4231_IFACE_CTRL] =
  901. chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA;
  902. chip->image[CS4231_ALT_FEATURE_1] = 0x80;
  903. chip->image[CS4231_ALT_FEATURE_2] = 0x01;
  904. if (vers & 0x20)
  905. chip->image[CS4231_ALT_FEATURE_2] |= 0x02;
  906. ptr = (unsigned char *) &chip->image;
  907. snd_cs4231_mce_down(chip);
  908. spin_lock_irqsave(&chip->lock, flags);
  909. for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */
  910. snd_cs4231_out(chip, i, *ptr++);
  911. spin_unlock_irqrestore(&chip->lock, flags);
  912. snd_cs4231_mce_up(chip);
  913. snd_cs4231_mce_down(chip);
  914. mdelay(2);
  915. return 0; /* all things are ok.. */
  916. }
  917. static const struct snd_pcm_hardware snd_cs4231_playback = {
  918. .info = SNDRV_PCM_INFO_MMAP |
  919. SNDRV_PCM_INFO_INTERLEAVED |
  920. SNDRV_PCM_INFO_MMAP_VALID |
  921. SNDRV_PCM_INFO_SYNC_START,
  922. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  923. SNDRV_PCM_FMTBIT_A_LAW |
  924. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  925. SNDRV_PCM_FMTBIT_U8 |
  926. SNDRV_PCM_FMTBIT_S16_LE |
  927. SNDRV_PCM_FMTBIT_S16_BE,
  928. .rates = SNDRV_PCM_RATE_KNOT |
  929. SNDRV_PCM_RATE_8000_48000,
  930. .rate_min = 5510,
  931. .rate_max = 48000,
  932. .channels_min = 1,
  933. .channels_max = 2,
  934. .buffer_bytes_max = 32 * 1024,
  935. .period_bytes_min = 64,
  936. .period_bytes_max = 32 * 1024,
  937. .periods_min = 1,
  938. .periods_max = 1024,
  939. };
  940. static const struct snd_pcm_hardware snd_cs4231_capture = {
  941. .info = SNDRV_PCM_INFO_MMAP |
  942. SNDRV_PCM_INFO_INTERLEAVED |
  943. SNDRV_PCM_INFO_MMAP_VALID |
  944. SNDRV_PCM_INFO_SYNC_START,
  945. .formats = SNDRV_PCM_FMTBIT_MU_LAW |
  946. SNDRV_PCM_FMTBIT_A_LAW |
  947. SNDRV_PCM_FMTBIT_IMA_ADPCM |
  948. SNDRV_PCM_FMTBIT_U8 |
  949. SNDRV_PCM_FMTBIT_S16_LE |
  950. SNDRV_PCM_FMTBIT_S16_BE,
  951. .rates = SNDRV_PCM_RATE_KNOT |
  952. SNDRV_PCM_RATE_8000_48000,
  953. .rate_min = 5510,
  954. .rate_max = 48000,
  955. .channels_min = 1,
  956. .channels_max = 2,
  957. .buffer_bytes_max = 32 * 1024,
  958. .period_bytes_min = 64,
  959. .period_bytes_max = 32 * 1024,
  960. .periods_min = 1,
  961. .periods_max = 1024,
  962. };
  963. static int snd_cs4231_playback_open(struct snd_pcm_substream *substream)
  964. {
  965. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  966. struct snd_pcm_runtime *runtime = substream->runtime;
  967. int err;
  968. runtime->hw = snd_cs4231_playback;
  969. err = snd_cs4231_open(chip, CS4231_MODE_PLAY);
  970. if (err < 0)
  971. return err;
  972. chip->playback_substream = substream;
  973. chip->p_periods_sent = 0;
  974. snd_pcm_set_sync(substream);
  975. snd_cs4231_xrate(runtime);
  976. return 0;
  977. }
  978. static int snd_cs4231_capture_open(struct snd_pcm_substream *substream)
  979. {
  980. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  981. struct snd_pcm_runtime *runtime = substream->runtime;
  982. int err;
  983. runtime->hw = snd_cs4231_capture;
  984. err = snd_cs4231_open(chip, CS4231_MODE_RECORD);
  985. if (err < 0)
  986. return err;
  987. chip->capture_substream = substream;
  988. chip->c_periods_sent = 0;
  989. snd_pcm_set_sync(substream);
  990. snd_cs4231_xrate(runtime);
  991. return 0;
  992. }
  993. static int snd_cs4231_playback_close(struct snd_pcm_substream *substream)
  994. {
  995. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  996. snd_cs4231_close(chip, CS4231_MODE_PLAY);
  997. chip->playback_substream = NULL;
  998. return 0;
  999. }
  1000. static int snd_cs4231_capture_close(struct snd_pcm_substream *substream)
  1001. {
  1002. struct snd_cs4231 *chip = snd_pcm_substream_chip(substream);
  1003. snd_cs4231_close(chip, CS4231_MODE_RECORD);
  1004. chip->capture_substream = NULL;
  1005. return 0;
  1006. }
  1007. /* XXX We can do some power-management, in particular on EBUS using
  1008. * XXX the audio AUXIO register...
  1009. */
  1010. static const struct snd_pcm_ops snd_cs4231_playback_ops = {
  1011. .open = snd_cs4231_playback_open,
  1012. .close = snd_cs4231_playback_close,
  1013. .hw_params = snd_cs4231_playback_hw_params,
  1014. .prepare = snd_cs4231_playback_prepare,
  1015. .trigger = snd_cs4231_trigger,
  1016. .pointer = snd_cs4231_playback_pointer,
  1017. };
  1018. static const struct snd_pcm_ops snd_cs4231_capture_ops = {
  1019. .open = snd_cs4231_capture_open,
  1020. .close = snd_cs4231_capture_close,
  1021. .hw_params = snd_cs4231_capture_hw_params,
  1022. .prepare = snd_cs4231_capture_prepare,
  1023. .trigger = snd_cs4231_trigger,
  1024. .pointer = snd_cs4231_capture_pointer,
  1025. };
  1026. static int snd_cs4231_pcm(struct snd_card *card)
  1027. {
  1028. struct snd_cs4231 *chip = card->private_data;
  1029. struct snd_pcm *pcm;
  1030. int err;
  1031. err = snd_pcm_new(card, "CS4231", 0, 1, 1, &pcm);
  1032. if (err < 0)
  1033. return err;
  1034. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1035. &snd_cs4231_playback_ops);
  1036. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1037. &snd_cs4231_capture_ops);
  1038. /* global setup */
  1039. pcm->private_data = chip;
  1040. pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1041. strcpy(pcm->name, "CS4231");
  1042. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
  1043. &chip->op->dev, 64 * 1024, 128 * 1024);
  1044. chip->pcm = pcm;
  1045. return 0;
  1046. }
  1047. static int snd_cs4231_timer(struct snd_card *card)
  1048. {
  1049. struct snd_cs4231 *chip = card->private_data;
  1050. struct snd_timer *timer;
  1051. struct snd_timer_id tid;
  1052. int err;
  1053. /* Timer initialization */
  1054. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1055. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1056. tid.card = card->number;
  1057. tid.device = 0;
  1058. tid.subdevice = 0;
  1059. err = snd_timer_new(card, "CS4231", &tid, &timer);
  1060. if (err < 0)
  1061. return err;
  1062. strcpy(timer->name, "CS4231");
  1063. timer->private_data = chip;
  1064. timer->hw = snd_cs4231_timer_table;
  1065. chip->timer = timer;
  1066. return 0;
  1067. }
  1068. /*
  1069. * MIXER part
  1070. */
  1071. static int snd_cs4231_info_mux(struct snd_kcontrol *kcontrol,
  1072. struct snd_ctl_elem_info *uinfo)
  1073. {
  1074. static const char * const texts[4] = {
  1075. "Line", "CD", "Mic", "Mix"
  1076. };
  1077. return snd_ctl_enum_info(uinfo, 2, 4, texts);
  1078. }
  1079. static int snd_cs4231_get_mux(struct snd_kcontrol *kcontrol,
  1080. struct snd_ctl_elem_value *ucontrol)
  1081. {
  1082. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1083. unsigned long flags;
  1084. spin_lock_irqsave(&chip->lock, flags);
  1085. ucontrol->value.enumerated.item[0] =
  1086. (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1087. ucontrol->value.enumerated.item[1] =
  1088. (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
  1089. spin_unlock_irqrestore(&chip->lock, flags);
  1090. return 0;
  1091. }
  1092. static int snd_cs4231_put_mux(struct snd_kcontrol *kcontrol,
  1093. struct snd_ctl_elem_value *ucontrol)
  1094. {
  1095. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1096. unsigned long flags;
  1097. unsigned short left, right;
  1098. int change;
  1099. if (ucontrol->value.enumerated.item[0] > 3 ||
  1100. ucontrol->value.enumerated.item[1] > 3)
  1101. return -EINVAL;
  1102. left = ucontrol->value.enumerated.item[0] << 6;
  1103. right = ucontrol->value.enumerated.item[1] << 6;
  1104. spin_lock_irqsave(&chip->lock, flags);
  1105. left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
  1106. right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
  1107. change = left != chip->image[CS4231_LEFT_INPUT] ||
  1108. right != chip->image[CS4231_RIGHT_INPUT];
  1109. snd_cs4231_out(chip, CS4231_LEFT_INPUT, left);
  1110. snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right);
  1111. spin_unlock_irqrestore(&chip->lock, flags);
  1112. return change;
  1113. }
  1114. static int snd_cs4231_info_single(struct snd_kcontrol *kcontrol,
  1115. struct snd_ctl_elem_info *uinfo)
  1116. {
  1117. int mask = (kcontrol->private_value >> 16) & 0xff;
  1118. uinfo->type = (mask == 1) ?
  1119. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1120. uinfo->count = 1;
  1121. uinfo->value.integer.min = 0;
  1122. uinfo->value.integer.max = mask;
  1123. return 0;
  1124. }
  1125. static int snd_cs4231_get_single(struct snd_kcontrol *kcontrol,
  1126. struct snd_ctl_elem_value *ucontrol)
  1127. {
  1128. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1129. unsigned long flags;
  1130. int reg = kcontrol->private_value & 0xff;
  1131. int shift = (kcontrol->private_value >> 8) & 0xff;
  1132. int mask = (kcontrol->private_value >> 16) & 0xff;
  1133. int invert = (kcontrol->private_value >> 24) & 0xff;
  1134. spin_lock_irqsave(&chip->lock, flags);
  1135. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  1136. spin_unlock_irqrestore(&chip->lock, flags);
  1137. if (invert)
  1138. ucontrol->value.integer.value[0] =
  1139. (mask - ucontrol->value.integer.value[0]);
  1140. return 0;
  1141. }
  1142. static int snd_cs4231_put_single(struct snd_kcontrol *kcontrol,
  1143. struct snd_ctl_elem_value *ucontrol)
  1144. {
  1145. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1146. unsigned long flags;
  1147. int reg = kcontrol->private_value & 0xff;
  1148. int shift = (kcontrol->private_value >> 8) & 0xff;
  1149. int mask = (kcontrol->private_value >> 16) & 0xff;
  1150. int invert = (kcontrol->private_value >> 24) & 0xff;
  1151. int change;
  1152. unsigned short val;
  1153. val = (ucontrol->value.integer.value[0] & mask);
  1154. if (invert)
  1155. val = mask - val;
  1156. val <<= shift;
  1157. spin_lock_irqsave(&chip->lock, flags);
  1158. val = (chip->image[reg] & ~(mask << shift)) | val;
  1159. change = val != chip->image[reg];
  1160. snd_cs4231_out(chip, reg, val);
  1161. spin_unlock_irqrestore(&chip->lock, flags);
  1162. return change;
  1163. }
  1164. static int snd_cs4231_info_double(struct snd_kcontrol *kcontrol,
  1165. struct snd_ctl_elem_info *uinfo)
  1166. {
  1167. int mask = (kcontrol->private_value >> 24) & 0xff;
  1168. uinfo->type = mask == 1 ?
  1169. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  1170. uinfo->count = 2;
  1171. uinfo->value.integer.min = 0;
  1172. uinfo->value.integer.max = mask;
  1173. return 0;
  1174. }
  1175. static int snd_cs4231_get_double(struct snd_kcontrol *kcontrol,
  1176. struct snd_ctl_elem_value *ucontrol)
  1177. {
  1178. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1179. unsigned long flags;
  1180. int left_reg = kcontrol->private_value & 0xff;
  1181. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1182. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1183. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1184. int mask = (kcontrol->private_value >> 24) & 0xff;
  1185. int invert = (kcontrol->private_value >> 22) & 1;
  1186. spin_lock_irqsave(&chip->lock, flags);
  1187. ucontrol->value.integer.value[0] =
  1188. (chip->image[left_reg] >> shift_left) & mask;
  1189. ucontrol->value.integer.value[1] =
  1190. (chip->image[right_reg] >> shift_right) & mask;
  1191. spin_unlock_irqrestore(&chip->lock, flags);
  1192. if (invert) {
  1193. ucontrol->value.integer.value[0] =
  1194. (mask - ucontrol->value.integer.value[0]);
  1195. ucontrol->value.integer.value[1] =
  1196. (mask - ucontrol->value.integer.value[1]);
  1197. }
  1198. return 0;
  1199. }
  1200. static int snd_cs4231_put_double(struct snd_kcontrol *kcontrol,
  1201. struct snd_ctl_elem_value *ucontrol)
  1202. {
  1203. struct snd_cs4231 *chip = snd_kcontrol_chip(kcontrol);
  1204. unsigned long flags;
  1205. int left_reg = kcontrol->private_value & 0xff;
  1206. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1207. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1208. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1209. int mask = (kcontrol->private_value >> 24) & 0xff;
  1210. int invert = (kcontrol->private_value >> 22) & 1;
  1211. int change;
  1212. unsigned short val1, val2;
  1213. val1 = ucontrol->value.integer.value[0] & mask;
  1214. val2 = ucontrol->value.integer.value[1] & mask;
  1215. if (invert) {
  1216. val1 = mask - val1;
  1217. val2 = mask - val2;
  1218. }
  1219. val1 <<= shift_left;
  1220. val2 <<= shift_right;
  1221. spin_lock_irqsave(&chip->lock, flags);
  1222. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1223. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1224. change = val1 != chip->image[left_reg];
  1225. change |= val2 != chip->image[right_reg];
  1226. snd_cs4231_out(chip, left_reg, val1);
  1227. snd_cs4231_out(chip, right_reg, val2);
  1228. spin_unlock_irqrestore(&chip->lock, flags);
  1229. return change;
  1230. }
  1231. #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
  1232. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1233. .info = snd_cs4231_info_single, \
  1234. .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
  1235. .private_value = (reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24) }
  1236. #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, \
  1237. shift_right, mask, invert) \
  1238. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), .index = (xindex), \
  1239. .info = snd_cs4231_info_double, \
  1240. .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
  1241. .private_value = (left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | \
  1242. ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22) }
  1243. static const struct snd_kcontrol_new snd_cs4231_controls[] = {
  1244. CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT,
  1245. CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
  1246. CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT,
  1247. CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
  1248. CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN,
  1249. CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
  1250. CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN,
  1251. CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
  1252. CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT,
  1253. CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1254. CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT,
  1255. CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1256. CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT,
  1257. CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1258. CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT,
  1259. CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1260. CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1),
  1261. CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1),
  1262. CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1),
  1263. CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0),
  1264. CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0,
  1265. 15, 0),
  1266. {
  1267. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1268. .name = "Capture Source",
  1269. .info = snd_cs4231_info_mux,
  1270. .get = snd_cs4231_get_mux,
  1271. .put = snd_cs4231_put_mux,
  1272. },
  1273. CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5,
  1274. 1, 0),
  1275. CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
  1276. CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1),
  1277. /* SPARC specific uses of XCTL{0,1} general purpose outputs. */
  1278. CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1),
  1279. CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1)
  1280. };
  1281. static int snd_cs4231_mixer(struct snd_card *card)
  1282. {
  1283. struct snd_cs4231 *chip = card->private_data;
  1284. int err, idx;
  1285. if (snd_BUG_ON(!chip || !chip->pcm))
  1286. return -EINVAL;
  1287. strcpy(card->mixername, chip->pcm->name);
  1288. for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) {
  1289. err = snd_ctl_add(card,
  1290. snd_ctl_new1(&snd_cs4231_controls[idx], chip));
  1291. if (err < 0)
  1292. return err;
  1293. }
  1294. return 0;
  1295. }
  1296. static int dev;
  1297. static int cs4231_attach_begin(struct platform_device *op,
  1298. struct snd_card **rcard)
  1299. {
  1300. struct snd_card *card;
  1301. struct snd_cs4231 *chip;
  1302. int err;
  1303. *rcard = NULL;
  1304. if (dev >= SNDRV_CARDS)
  1305. return -ENODEV;
  1306. if (!enable[dev]) {
  1307. dev++;
  1308. return -ENOENT;
  1309. }
  1310. err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
  1311. sizeof(struct snd_cs4231), &card);
  1312. if (err < 0)
  1313. return err;
  1314. strcpy(card->driver, "CS4231");
  1315. strcpy(card->shortname, "Sun CS4231");
  1316. chip = card->private_data;
  1317. chip->card = card;
  1318. *rcard = card;
  1319. return 0;
  1320. }
  1321. static int cs4231_attach_finish(struct snd_card *card)
  1322. {
  1323. struct snd_cs4231 *chip = card->private_data;
  1324. int err;
  1325. err = snd_cs4231_pcm(card);
  1326. if (err < 0)
  1327. goto out_err;
  1328. err = snd_cs4231_mixer(card);
  1329. if (err < 0)
  1330. goto out_err;
  1331. err = snd_cs4231_timer(card);
  1332. if (err < 0)
  1333. goto out_err;
  1334. err = snd_card_register(card);
  1335. if (err < 0)
  1336. goto out_err;
  1337. dev_set_drvdata(&chip->op->dev, chip);
  1338. dev++;
  1339. return 0;
  1340. out_err:
  1341. snd_card_free(card);
  1342. return err;
  1343. }
  1344. #ifdef SBUS_SUPPORT
  1345. static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
  1346. {
  1347. unsigned long flags;
  1348. unsigned char status;
  1349. u32 csr;
  1350. struct snd_cs4231 *chip = dev_id;
  1351. /*This is IRQ is not raised by the cs4231*/
  1352. if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
  1353. return IRQ_NONE;
  1354. /* ACK the APC interrupt. */
  1355. csr = sbus_readl(chip->port + APCCSR);
  1356. sbus_writel(csr, chip->port + APCCSR);
  1357. if ((csr & APC_PDMA_READY) &&
  1358. (csr & APC_PLAY_INT) &&
  1359. (csr & APC_XINT_PNVA) &&
  1360. !(csr & APC_XINT_EMPT))
  1361. snd_cs4231_play_callback(chip);
  1362. if ((csr & APC_CDMA_READY) &&
  1363. (csr & APC_CAPT_INT) &&
  1364. (csr & APC_XINT_CNVA) &&
  1365. !(csr & APC_XINT_EMPT))
  1366. snd_cs4231_capture_callback(chip);
  1367. status = snd_cs4231_in(chip, CS4231_IRQ_STATUS);
  1368. if (status & CS4231_TIMER_IRQ) {
  1369. if (chip->timer)
  1370. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1371. }
  1372. if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY))
  1373. snd_cs4231_overrange(chip);
  1374. /* ACK the CS4231 interrupt. */
  1375. spin_lock_irqsave(&chip->lock, flags);
  1376. snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0);
  1377. spin_unlock_irqrestore(&chip->lock, flags);
  1378. return IRQ_HANDLED;
  1379. }
  1380. /*
  1381. * SBUS DMA routines
  1382. */
  1383. static int sbus_dma_request(struct cs4231_dma_control *dma_cont,
  1384. dma_addr_t bus_addr, size_t len)
  1385. {
  1386. unsigned long flags;
  1387. u32 test, csr;
  1388. int err;
  1389. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1390. if (len >= (1 << 24))
  1391. return -EINVAL;
  1392. spin_lock_irqsave(&base->lock, flags);
  1393. csr = sbus_readl(base->regs + APCCSR);
  1394. err = -EINVAL;
  1395. test = APC_CDMA_READY;
  1396. if (base->dir == APC_PLAY)
  1397. test = APC_PDMA_READY;
  1398. if (!(csr & test))
  1399. goto out;
  1400. err = -EBUSY;
  1401. test = APC_XINT_CNVA;
  1402. if (base->dir == APC_PLAY)
  1403. test = APC_XINT_PNVA;
  1404. if (!(csr & test))
  1405. goto out;
  1406. err = 0;
  1407. sbus_writel(bus_addr, base->regs + base->dir + APCNVA);
  1408. sbus_writel(len, base->regs + base->dir + APCNC);
  1409. out:
  1410. spin_unlock_irqrestore(&base->lock, flags);
  1411. return err;
  1412. }
  1413. static void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d)
  1414. {
  1415. unsigned long flags;
  1416. u32 csr, test;
  1417. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1418. spin_lock_irqsave(&base->lock, flags);
  1419. csr = sbus_readl(base->regs + APCCSR);
  1420. test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA |
  1421. APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL |
  1422. APC_XINT_PENA;
  1423. if (base->dir == APC_RECORD)
  1424. test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA |
  1425. APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL;
  1426. csr |= test;
  1427. sbus_writel(csr, base->regs + APCCSR);
  1428. spin_unlock_irqrestore(&base->lock, flags);
  1429. }
  1430. static void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1431. {
  1432. unsigned long flags;
  1433. u32 csr, shift;
  1434. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1435. spin_lock_irqsave(&base->lock, flags);
  1436. if (!on) {
  1437. sbus_writel(0, base->regs + base->dir + APCNC);
  1438. sbus_writel(0, base->regs + base->dir + APCNVA);
  1439. if (base->dir == APC_PLAY) {
  1440. sbus_writel(0, base->regs + base->dir + APCC);
  1441. sbus_writel(0, base->regs + base->dir + APCVA);
  1442. }
  1443. udelay(1200);
  1444. }
  1445. csr = sbus_readl(base->regs + APCCSR);
  1446. shift = 0;
  1447. if (base->dir == APC_PLAY)
  1448. shift = 1;
  1449. if (on)
  1450. csr &= ~(APC_CPAUSE << shift);
  1451. else
  1452. csr |= (APC_CPAUSE << shift);
  1453. sbus_writel(csr, base->regs + APCCSR);
  1454. if (on)
  1455. csr |= (APC_CDMA_READY << shift);
  1456. else
  1457. csr &= ~(APC_CDMA_READY << shift);
  1458. sbus_writel(csr, base->regs + APCCSR);
  1459. spin_unlock_irqrestore(&base->lock, flags);
  1460. }
  1461. static unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont)
  1462. {
  1463. struct sbus_dma_info *base = &dma_cont->sbus_info;
  1464. return sbus_readl(base->regs + base->dir + APCVA);
  1465. }
  1466. /*
  1467. * Init and exit routines
  1468. */
  1469. static int snd_cs4231_sbus_free(struct snd_cs4231 *chip)
  1470. {
  1471. struct platform_device *op = chip->op;
  1472. if (chip->irq[0])
  1473. free_irq(chip->irq[0], chip);
  1474. if (chip->port)
  1475. of_iounmap(&op->resource[0], chip->port, chip->regs_size);
  1476. return 0;
  1477. }
  1478. static int snd_cs4231_sbus_dev_free(struct snd_device *device)
  1479. {
  1480. struct snd_cs4231 *cp = device->device_data;
  1481. return snd_cs4231_sbus_free(cp);
  1482. }
  1483. static const struct snd_device_ops snd_cs4231_sbus_dev_ops = {
  1484. .dev_free = snd_cs4231_sbus_dev_free,
  1485. };
  1486. static int snd_cs4231_sbus_create(struct snd_card *card,
  1487. struct platform_device *op,
  1488. int dev)
  1489. {
  1490. struct snd_cs4231 *chip = card->private_data;
  1491. int err;
  1492. spin_lock_init(&chip->lock);
  1493. spin_lock_init(&chip->c_dma.sbus_info.lock);
  1494. spin_lock_init(&chip->p_dma.sbus_info.lock);
  1495. mutex_init(&chip->mce_mutex);
  1496. mutex_init(&chip->open_mutex);
  1497. chip->op = op;
  1498. chip->regs_size = resource_size(&op->resource[0]);
  1499. memcpy(&chip->image, &snd_cs4231_original_image,
  1500. sizeof(snd_cs4231_original_image));
  1501. chip->port = of_ioremap(&op->resource[0], 0,
  1502. chip->regs_size, "cs4231");
  1503. if (!chip->port) {
  1504. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1505. return -EIO;
  1506. }
  1507. chip->c_dma.sbus_info.regs = chip->port;
  1508. chip->p_dma.sbus_info.regs = chip->port;
  1509. chip->c_dma.sbus_info.dir = APC_RECORD;
  1510. chip->p_dma.sbus_info.dir = APC_PLAY;
  1511. chip->p_dma.prepare = sbus_dma_prepare;
  1512. chip->p_dma.enable = sbus_dma_enable;
  1513. chip->p_dma.request = sbus_dma_request;
  1514. chip->p_dma.address = sbus_dma_addr;
  1515. chip->c_dma.prepare = sbus_dma_prepare;
  1516. chip->c_dma.enable = sbus_dma_enable;
  1517. chip->c_dma.request = sbus_dma_request;
  1518. chip->c_dma.address = sbus_dma_addr;
  1519. if (request_irq(op->archdata.irqs[0], snd_cs4231_sbus_interrupt,
  1520. IRQF_SHARED, "cs4231", chip)) {
  1521. snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %d\n",
  1522. dev, op->archdata.irqs[0]);
  1523. snd_cs4231_sbus_free(chip);
  1524. return -EBUSY;
  1525. }
  1526. chip->irq[0] = op->archdata.irqs[0];
  1527. if (snd_cs4231_probe(chip) < 0) {
  1528. snd_cs4231_sbus_free(chip);
  1529. return -ENODEV;
  1530. }
  1531. snd_cs4231_init(chip);
  1532. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1533. chip, &snd_cs4231_sbus_dev_ops)) < 0) {
  1534. snd_cs4231_sbus_free(chip);
  1535. return err;
  1536. }
  1537. return 0;
  1538. }
  1539. static int cs4231_sbus_probe(struct platform_device *op)
  1540. {
  1541. struct resource *rp = &op->resource[0];
  1542. struct snd_card *card;
  1543. int err;
  1544. err = cs4231_attach_begin(op, &card);
  1545. if (err)
  1546. return err;
  1547. sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
  1548. card->shortname,
  1549. rp->flags & 0xffL,
  1550. (unsigned long long)rp->start,
  1551. op->archdata.irqs[0]);
  1552. err = snd_cs4231_sbus_create(card, op, dev);
  1553. if (err < 0) {
  1554. snd_card_free(card);
  1555. return err;
  1556. }
  1557. return cs4231_attach_finish(card);
  1558. }
  1559. #endif
  1560. #ifdef EBUS_SUPPORT
  1561. static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event,
  1562. void *cookie)
  1563. {
  1564. struct snd_cs4231 *chip = cookie;
  1565. snd_cs4231_play_callback(chip);
  1566. }
  1567. static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p,
  1568. int event, void *cookie)
  1569. {
  1570. struct snd_cs4231 *chip = cookie;
  1571. snd_cs4231_capture_callback(chip);
  1572. }
  1573. /*
  1574. * EBUS DMA wrappers
  1575. */
  1576. static int _ebus_dma_request(struct cs4231_dma_control *dma_cont,
  1577. dma_addr_t bus_addr, size_t len)
  1578. {
  1579. return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len);
  1580. }
  1581. static void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on)
  1582. {
  1583. ebus_dma_enable(&dma_cont->ebus_info, on);
  1584. }
  1585. static void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir)
  1586. {
  1587. ebus_dma_prepare(&dma_cont->ebus_info, dir);
  1588. }
  1589. static unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont)
  1590. {
  1591. return ebus_dma_addr(&dma_cont->ebus_info);
  1592. }
  1593. /*
  1594. * Init and exit routines
  1595. */
  1596. static int snd_cs4231_ebus_free(struct snd_cs4231 *chip)
  1597. {
  1598. struct platform_device *op = chip->op;
  1599. if (chip->c_dma.ebus_info.regs) {
  1600. ebus_dma_unregister(&chip->c_dma.ebus_info);
  1601. of_iounmap(&op->resource[2], chip->c_dma.ebus_info.regs, 0x10);
  1602. }
  1603. if (chip->p_dma.ebus_info.regs) {
  1604. ebus_dma_unregister(&chip->p_dma.ebus_info);
  1605. of_iounmap(&op->resource[1], chip->p_dma.ebus_info.regs, 0x10);
  1606. }
  1607. if (chip->port)
  1608. of_iounmap(&op->resource[0], chip->port, 0x10);
  1609. return 0;
  1610. }
  1611. static int snd_cs4231_ebus_dev_free(struct snd_device *device)
  1612. {
  1613. struct snd_cs4231 *cp = device->device_data;
  1614. return snd_cs4231_ebus_free(cp);
  1615. }
  1616. static const struct snd_device_ops snd_cs4231_ebus_dev_ops = {
  1617. .dev_free = snd_cs4231_ebus_dev_free,
  1618. };
  1619. static int snd_cs4231_ebus_create(struct snd_card *card,
  1620. struct platform_device *op,
  1621. int dev)
  1622. {
  1623. struct snd_cs4231 *chip = card->private_data;
  1624. int err;
  1625. spin_lock_init(&chip->lock);
  1626. spin_lock_init(&chip->c_dma.ebus_info.lock);
  1627. spin_lock_init(&chip->p_dma.ebus_info.lock);
  1628. mutex_init(&chip->mce_mutex);
  1629. mutex_init(&chip->open_mutex);
  1630. chip->flags |= CS4231_FLAG_EBUS;
  1631. chip->op = op;
  1632. memcpy(&chip->image, &snd_cs4231_original_image,
  1633. sizeof(snd_cs4231_original_image));
  1634. strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)");
  1635. chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1636. chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback;
  1637. chip->c_dma.ebus_info.client_cookie = chip;
  1638. chip->c_dma.ebus_info.irq = op->archdata.irqs[0];
  1639. strcpy(chip->p_dma.ebus_info.name, "cs4231(play)");
  1640. chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER;
  1641. chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback;
  1642. chip->p_dma.ebus_info.client_cookie = chip;
  1643. chip->p_dma.ebus_info.irq = op->archdata.irqs[1];
  1644. chip->p_dma.prepare = _ebus_dma_prepare;
  1645. chip->p_dma.enable = _ebus_dma_enable;
  1646. chip->p_dma.request = _ebus_dma_request;
  1647. chip->p_dma.address = _ebus_dma_addr;
  1648. chip->c_dma.prepare = _ebus_dma_prepare;
  1649. chip->c_dma.enable = _ebus_dma_enable;
  1650. chip->c_dma.request = _ebus_dma_request;
  1651. chip->c_dma.address = _ebus_dma_addr;
  1652. chip->port = of_ioremap(&op->resource[0], 0, 0x10, "cs4231");
  1653. chip->p_dma.ebus_info.regs =
  1654. of_ioremap(&op->resource[1], 0, 0x10, "cs4231_pdma");
  1655. chip->c_dma.ebus_info.regs =
  1656. of_ioremap(&op->resource[2], 0, 0x10, "cs4231_cdma");
  1657. if (!chip->port || !chip->p_dma.ebus_info.regs ||
  1658. !chip->c_dma.ebus_info.regs) {
  1659. snd_cs4231_ebus_free(chip);
  1660. snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev);
  1661. return -EIO;
  1662. }
  1663. if (ebus_dma_register(&chip->c_dma.ebus_info)) {
  1664. snd_cs4231_ebus_free(chip);
  1665. snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n",
  1666. dev);
  1667. return -EBUSY;
  1668. }
  1669. if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) {
  1670. snd_cs4231_ebus_free(chip);
  1671. snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n",
  1672. dev);
  1673. return -EBUSY;
  1674. }
  1675. if (ebus_dma_register(&chip->p_dma.ebus_info)) {
  1676. snd_cs4231_ebus_free(chip);
  1677. snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n",
  1678. dev);
  1679. return -EBUSY;
  1680. }
  1681. if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) {
  1682. snd_cs4231_ebus_free(chip);
  1683. snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev);
  1684. return -EBUSY;
  1685. }
  1686. if (snd_cs4231_probe(chip) < 0) {
  1687. snd_cs4231_ebus_free(chip);
  1688. return -ENODEV;
  1689. }
  1690. snd_cs4231_init(chip);
  1691. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  1692. chip, &snd_cs4231_ebus_dev_ops)) < 0) {
  1693. snd_cs4231_ebus_free(chip);
  1694. return err;
  1695. }
  1696. return 0;
  1697. }
  1698. static int cs4231_ebus_probe(struct platform_device *op)
  1699. {
  1700. struct snd_card *card;
  1701. int err;
  1702. err = cs4231_attach_begin(op, &card);
  1703. if (err)
  1704. return err;
  1705. sprintf(card->longname, "%s at 0x%llx, irq %d",
  1706. card->shortname,
  1707. op->resource[0].start,
  1708. op->archdata.irqs[0]);
  1709. err = snd_cs4231_ebus_create(card, op, dev);
  1710. if (err < 0) {
  1711. snd_card_free(card);
  1712. return err;
  1713. }
  1714. return cs4231_attach_finish(card);
  1715. }
  1716. #endif
  1717. static int cs4231_probe(struct platform_device *op)
  1718. {
  1719. #ifdef EBUS_SUPPORT
  1720. if (of_node_name_eq(op->dev.of_node->parent, "ebus"))
  1721. return cs4231_ebus_probe(op);
  1722. #endif
  1723. #ifdef SBUS_SUPPORT
  1724. if (of_node_name_eq(op->dev.of_node->parent, "sbus") ||
  1725. of_node_name_eq(op->dev.of_node->parent, "sbi"))
  1726. return cs4231_sbus_probe(op);
  1727. #endif
  1728. return -ENODEV;
  1729. }
  1730. static int cs4231_remove(struct platform_device *op)
  1731. {
  1732. struct snd_cs4231 *chip = dev_get_drvdata(&op->dev);
  1733. snd_card_free(chip->card);
  1734. return 0;
  1735. }
  1736. static const struct of_device_id cs4231_match[] = {
  1737. {
  1738. .name = "SUNW,CS4231",
  1739. },
  1740. {
  1741. .name = "audio",
  1742. .compatible = "SUNW,CS4231",
  1743. },
  1744. {},
  1745. };
  1746. MODULE_DEVICE_TABLE(of, cs4231_match);
  1747. static struct platform_driver cs4231_driver = {
  1748. .driver = {
  1749. .name = "audio",
  1750. .of_match_table = cs4231_match,
  1751. },
  1752. .probe = cs4231_probe,
  1753. .remove = cs4231_remove,
  1754. };
  1755. module_platform_driver(cs4231_driver);