amd7930.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for AMD7930 sound chips found on Sparcs.
  4. * Copyright (C) 2002, 2008 David S. Miller <davem@davemloft.net>
  5. *
  6. * Based entirely upon drivers/sbus/audio/amd7930.c which is:
  7. * Copyright (C) 1996,1997 Thomas K. Dyas (tdyas@eden.rutgers.edu)
  8. *
  9. * --- Notes from Thomas's original driver ---
  10. * This is the lowlevel driver for the AMD7930 audio chip found on all
  11. * sun4c machines and some sun4m machines.
  12. *
  13. * The amd7930 is actually an ISDN chip which has a very simple
  14. * integrated audio encoder/decoder. When Sun decided on what chip to
  15. * use for audio, they had the brilliant idea of using the amd7930 and
  16. * only connecting the audio encoder/decoder pins.
  17. *
  18. * Thanks to the AMD engineer who was able to get us the AMD79C30
  19. * databook which has all the programming information and gain tables.
  20. *
  21. * Advanced Micro Devices' Am79C30A is an ISDN/audio chip used in the
  22. * SparcStation 1+. The chip provides microphone and speaker interfaces
  23. * which provide mono-channel audio at 8K samples per second via either
  24. * 8-bit A-law or 8-bit mu-law encoding. Also, the chip features an
  25. * ISDN BRI Line Interface Unit (LIU), I.430 S/T physical interface,
  26. * which performs basic D channel LAPD processing and provides raw
  27. * B channel data. The digital audio channel, the two ISDN B channels,
  28. * and two 64 Kbps channels to the microprocessor are all interconnected
  29. * via a multiplexer.
  30. * --- End of notes from Thoamas's original driver ---
  31. */
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/slab.h>
  35. #include <linux/init.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/moduleparam.h>
  38. #include <linux/of.h>
  39. #include <linux/of_device.h>
  40. #include <linux/io.h>
  41. #include <sound/core.h>
  42. #include <sound/pcm.h>
  43. #include <sound/info.h>
  44. #include <sound/control.h>
  45. #include <sound/initval.h>
  46. #include <asm/irq.h>
  47. #include <asm/prom.h>
  48. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  49. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  50. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  51. module_param_array(index, int, NULL, 0444);
  52. MODULE_PARM_DESC(index, "Index value for Sun AMD7930 soundcard.");
  53. module_param_array(id, charp, NULL, 0444);
  54. MODULE_PARM_DESC(id, "ID string for Sun AMD7930 soundcard.");
  55. module_param_array(enable, bool, NULL, 0444);
  56. MODULE_PARM_DESC(enable, "Enable Sun AMD7930 soundcard.");
  57. MODULE_AUTHOR("Thomas K. Dyas and David S. Miller");
  58. MODULE_DESCRIPTION("Sun AMD7930");
  59. MODULE_LICENSE("GPL");
  60. MODULE_SUPPORTED_DEVICE("{{Sun,AMD7930}}");
  61. /* Device register layout. */
  62. /* Register interface presented to the CPU by the amd7930. */
  63. #define AMD7930_CR 0x00UL /* Command Register (W) */
  64. #define AMD7930_IR AMD7930_CR /* Interrupt Register (R) */
  65. #define AMD7930_DR 0x01UL /* Data Register (R/W) */
  66. #define AMD7930_DSR1 0x02UL /* D-channel Status Register 1 (R) */
  67. #define AMD7930_DER 0x03UL /* D-channel Error Register (R) */
  68. #define AMD7930_DCTB 0x04UL /* D-channel Transmit Buffer (W) */
  69. #define AMD7930_DCRB AMD7930_DCTB /* D-channel Receive Buffer (R) */
  70. #define AMD7930_BBTB 0x05UL /* Bb-channel Transmit Buffer (W) */
  71. #define AMD7930_BBRB AMD7930_BBTB /* Bb-channel Receive Buffer (R) */
  72. #define AMD7930_BCTB 0x06UL /* Bc-channel Transmit Buffer (W) */
  73. #define AMD7930_BCRB AMD7930_BCTB /* Bc-channel Receive Buffer (R) */
  74. #define AMD7930_DSR2 0x07UL /* D-channel Status Register 2 (R) */
  75. /* Indirect registers in the Main Audio Processor. */
  76. struct amd7930_map {
  77. __u16 x[8];
  78. __u16 r[8];
  79. __u16 gx;
  80. __u16 gr;
  81. __u16 ger;
  82. __u16 stgr;
  83. __u16 ftgr;
  84. __u16 atgr;
  85. __u8 mmr1;
  86. __u8 mmr2;
  87. };
  88. /* After an amd7930 interrupt, reading the Interrupt Register (ir)
  89. * clears the interrupt and returns a bitmask indicating which
  90. * interrupt source(s) require service.
  91. */
  92. #define AMR_IR_DTTHRSH 0x01 /* D-channel xmit threshold */
  93. #define AMR_IR_DRTHRSH 0x02 /* D-channel recv threshold */
  94. #define AMR_IR_DSRI 0x04 /* D-channel packet status */
  95. #define AMR_IR_DERI 0x08 /* D-channel error */
  96. #define AMR_IR_BBUF 0x10 /* B-channel data xfer */
  97. #define AMR_IR_LSRI 0x20 /* LIU status */
  98. #define AMR_IR_DSR2I 0x40 /* D-channel buffer status */
  99. #define AMR_IR_MLTFRMI 0x80 /* multiframe or PP */
  100. /* The amd7930 has "indirect registers" which are accessed by writing
  101. * the register number into the Command Register and then reading or
  102. * writing values from the Data Register as appropriate. We define the
  103. * AMR_* macros to be the indirect register numbers and AM_* macros to
  104. * be bits in whatever register is referred to.
  105. */
  106. /* Initialization */
  107. #define AMR_INIT 0x21
  108. #define AM_INIT_ACTIVE 0x01
  109. #define AM_INIT_DATAONLY 0x02
  110. #define AM_INIT_POWERDOWN 0x03
  111. #define AM_INIT_DISABLE_INTS 0x04
  112. #define AMR_INIT2 0x20
  113. #define AM_INIT2_ENABLE_POWERDOWN 0x20
  114. #define AM_INIT2_ENABLE_MULTIFRAME 0x10
  115. /* Line Interface Unit */
  116. #define AMR_LIU_LSR 0xA1
  117. #define AM_LIU_LSR_STATE 0x07
  118. #define AM_LIU_LSR_F3 0x08
  119. #define AM_LIU_LSR_F7 0x10
  120. #define AM_LIU_LSR_F8 0x20
  121. #define AM_LIU_LSR_HSW 0x40
  122. #define AM_LIU_LSR_HSW_CHG 0x80
  123. #define AMR_LIU_LPR 0xA2
  124. #define AMR_LIU_LMR1 0xA3
  125. #define AM_LIU_LMR1_B1_ENABL 0x01
  126. #define AM_LIU_LMR1_B2_ENABL 0x02
  127. #define AM_LIU_LMR1_F_DISABL 0x04
  128. #define AM_LIU_LMR1_FA_DISABL 0x08
  129. #define AM_LIU_LMR1_REQ_ACTIV 0x10
  130. #define AM_LIU_LMR1_F8_F3 0x20
  131. #define AM_LIU_LMR1_LIU_ENABL 0x40
  132. #define AMR_LIU_LMR2 0xA4
  133. #define AM_LIU_LMR2_DECHO 0x01
  134. #define AM_LIU_LMR2_DLOOP 0x02
  135. #define AM_LIU_LMR2_DBACKOFF 0x04
  136. #define AM_LIU_LMR2_EN_F3_INT 0x08
  137. #define AM_LIU_LMR2_EN_F8_INT 0x10
  138. #define AM_LIU_LMR2_EN_HSW_INT 0x20
  139. #define AM_LIU_LMR2_EN_F7_INT 0x40
  140. #define AMR_LIU_2_4 0xA5
  141. #define AMR_LIU_MF 0xA6
  142. #define AMR_LIU_MFSB 0xA7
  143. #define AMR_LIU_MFQB 0xA8
  144. /* Multiplexor */
  145. #define AMR_MUX_MCR1 0x41
  146. #define AMR_MUX_MCR2 0x42
  147. #define AMR_MUX_MCR3 0x43
  148. #define AM_MUX_CHANNEL_B1 0x01
  149. #define AM_MUX_CHANNEL_B2 0x02
  150. #define AM_MUX_CHANNEL_Ba 0x03
  151. #define AM_MUX_CHANNEL_Bb 0x04
  152. #define AM_MUX_CHANNEL_Bc 0x05
  153. #define AM_MUX_CHANNEL_Bd 0x06
  154. #define AM_MUX_CHANNEL_Be 0x07
  155. #define AM_MUX_CHANNEL_Bf 0x08
  156. #define AMR_MUX_MCR4 0x44
  157. #define AM_MUX_MCR4_ENABLE_INTS 0x08
  158. #define AM_MUX_MCR4_REVERSE_Bb 0x10
  159. #define AM_MUX_MCR4_REVERSE_Bc 0x20
  160. #define AMR_MUX_1_4 0x45
  161. /* Main Audio Processor */
  162. #define AMR_MAP_X 0x61
  163. #define AMR_MAP_R 0x62
  164. #define AMR_MAP_GX 0x63
  165. #define AMR_MAP_GR 0x64
  166. #define AMR_MAP_GER 0x65
  167. #define AMR_MAP_STGR 0x66
  168. #define AMR_MAP_FTGR_1_2 0x67
  169. #define AMR_MAP_ATGR_1_2 0x68
  170. #define AMR_MAP_MMR1 0x69
  171. #define AM_MAP_MMR1_ALAW 0x01
  172. #define AM_MAP_MMR1_GX 0x02
  173. #define AM_MAP_MMR1_GR 0x04
  174. #define AM_MAP_MMR1_GER 0x08
  175. #define AM_MAP_MMR1_X 0x10
  176. #define AM_MAP_MMR1_R 0x20
  177. #define AM_MAP_MMR1_STG 0x40
  178. #define AM_MAP_MMR1_LOOPBACK 0x80
  179. #define AMR_MAP_MMR2 0x6A
  180. #define AM_MAP_MMR2_AINB 0x01
  181. #define AM_MAP_MMR2_LS 0x02
  182. #define AM_MAP_MMR2_ENABLE_DTMF 0x04
  183. #define AM_MAP_MMR2_ENABLE_TONEGEN 0x08
  184. #define AM_MAP_MMR2_ENABLE_TONERING 0x10
  185. #define AM_MAP_MMR2_DISABLE_HIGHPASS 0x20
  186. #define AM_MAP_MMR2_DISABLE_AUTOZERO 0x40
  187. #define AMR_MAP_1_10 0x6B
  188. #define AMR_MAP_MMR3 0x6C
  189. #define AMR_MAP_STRA 0x6D
  190. #define AMR_MAP_STRF 0x6E
  191. #define AMR_MAP_PEAKX 0x70
  192. #define AMR_MAP_PEAKR 0x71
  193. #define AMR_MAP_15_16 0x72
  194. /* Data Link Controller */
  195. #define AMR_DLC_FRAR_1_2_3 0x81
  196. #define AMR_DLC_SRAR_1_2_3 0x82
  197. #define AMR_DLC_TAR 0x83
  198. #define AMR_DLC_DRLR 0x84
  199. #define AMR_DLC_DTCR 0x85
  200. #define AMR_DLC_DMR1 0x86
  201. #define AMR_DLC_DMR1_DTTHRSH_INT 0x01
  202. #define AMR_DLC_DMR1_DRTHRSH_INT 0x02
  203. #define AMR_DLC_DMR1_TAR_ENABL 0x04
  204. #define AMR_DLC_DMR1_EORP_INT 0x08
  205. #define AMR_DLC_DMR1_EN_ADDR1 0x10
  206. #define AMR_DLC_DMR1_EN_ADDR2 0x20
  207. #define AMR_DLC_DMR1_EN_ADDR3 0x40
  208. #define AMR_DLC_DMR1_EN_ADDR4 0x80
  209. #define AMR_DLC_DMR1_EN_ADDRS 0xf0
  210. #define AMR_DLC_DMR2 0x87
  211. #define AMR_DLC_DMR2_RABRT_INT 0x01
  212. #define AMR_DLC_DMR2_RESID_INT 0x02
  213. #define AMR_DLC_DMR2_COLL_INT 0x04
  214. #define AMR_DLC_DMR2_FCS_INT 0x08
  215. #define AMR_DLC_DMR2_OVFL_INT 0x10
  216. #define AMR_DLC_DMR2_UNFL_INT 0x20
  217. #define AMR_DLC_DMR2_OVRN_INT 0x40
  218. #define AMR_DLC_DMR2_UNRN_INT 0x80
  219. #define AMR_DLC_1_7 0x88
  220. #define AMR_DLC_DRCR 0x89
  221. #define AMR_DLC_RNGR1 0x8A
  222. #define AMR_DLC_RNGR2 0x8B
  223. #define AMR_DLC_FRAR4 0x8C
  224. #define AMR_DLC_SRAR4 0x8D
  225. #define AMR_DLC_DMR3 0x8E
  226. #define AMR_DLC_DMR3_VA_INT 0x01
  227. #define AMR_DLC_DMR3_EOTP_INT 0x02
  228. #define AMR_DLC_DMR3_LBRP_INT 0x04
  229. #define AMR_DLC_DMR3_RBA_INT 0x08
  230. #define AMR_DLC_DMR3_LBT_INT 0x10
  231. #define AMR_DLC_DMR3_TBE_INT 0x20
  232. #define AMR_DLC_DMR3_RPLOST_INT 0x40
  233. #define AMR_DLC_DMR3_KEEP_FCS 0x80
  234. #define AMR_DLC_DMR4 0x8F
  235. #define AMR_DLC_DMR4_RCV_1 0x00
  236. #define AMR_DLC_DMR4_RCV_2 0x01
  237. #define AMR_DLC_DMR4_RCV_4 0x02
  238. #define AMR_DLC_DMR4_RCV_8 0x03
  239. #define AMR_DLC_DMR4_RCV_16 0x01
  240. #define AMR_DLC_DMR4_RCV_24 0x02
  241. #define AMR_DLC_DMR4_RCV_30 0x03
  242. #define AMR_DLC_DMR4_XMT_1 0x00
  243. #define AMR_DLC_DMR4_XMT_2 0x04
  244. #define AMR_DLC_DMR4_XMT_4 0x08
  245. #define AMR_DLC_DMR4_XMT_8 0x0c
  246. #define AMR_DLC_DMR4_XMT_10 0x08
  247. #define AMR_DLC_DMR4_XMT_14 0x0c
  248. #define AMR_DLC_DMR4_IDLE_MARK 0x00
  249. #define AMR_DLC_DMR4_IDLE_FLAG 0x10
  250. #define AMR_DLC_DMR4_ADDR_BOTH 0x00
  251. #define AMR_DLC_DMR4_ADDR_1ST 0x20
  252. #define AMR_DLC_DMR4_ADDR_2ND 0xa0
  253. #define AMR_DLC_DMR4_CR_ENABLE 0x40
  254. #define AMR_DLC_12_15 0x90
  255. #define AMR_DLC_ASR 0x91
  256. #define AMR_DLC_EFCR 0x92
  257. #define AMR_DLC_EFCR_EXTEND_FIFO 0x01
  258. #define AMR_DLC_EFCR_SEC_PKT_INT 0x02
  259. #define AMR_DSR1_VADDR 0x01
  260. #define AMR_DSR1_EORP 0x02
  261. #define AMR_DSR1_PKT_IP 0x04
  262. #define AMR_DSR1_DECHO_ON 0x08
  263. #define AMR_DSR1_DLOOP_ON 0x10
  264. #define AMR_DSR1_DBACK_OFF 0x20
  265. #define AMR_DSR1_EOTP 0x40
  266. #define AMR_DSR1_CXMT_ABRT 0x80
  267. #define AMR_DSR2_LBRP 0x01
  268. #define AMR_DSR2_RBA 0x02
  269. #define AMR_DSR2_RPLOST 0x04
  270. #define AMR_DSR2_LAST_BYTE 0x08
  271. #define AMR_DSR2_TBE 0x10
  272. #define AMR_DSR2_MARK_IDLE 0x20
  273. #define AMR_DSR2_FLAG_IDLE 0x40
  274. #define AMR_DSR2_SECOND_PKT 0x80
  275. #define AMR_DER_RABRT 0x01
  276. #define AMR_DER_RFRAME 0x02
  277. #define AMR_DER_COLLISION 0x04
  278. #define AMR_DER_FCS 0x08
  279. #define AMR_DER_OVFL 0x10
  280. #define AMR_DER_UNFL 0x20
  281. #define AMR_DER_OVRN 0x40
  282. #define AMR_DER_UNRN 0x80
  283. /* Peripheral Port */
  284. #define AMR_PP_PPCR1 0xC0
  285. #define AMR_PP_PPSR 0xC1
  286. #define AMR_PP_PPIER 0xC2
  287. #define AMR_PP_MTDR 0xC3
  288. #define AMR_PP_MRDR 0xC3
  289. #define AMR_PP_CITDR0 0xC4
  290. #define AMR_PP_CIRDR0 0xC4
  291. #define AMR_PP_CITDR1 0xC5
  292. #define AMR_PP_CIRDR1 0xC5
  293. #define AMR_PP_PPCR2 0xC8
  294. #define AMR_PP_PPCR3 0xC9
  295. struct snd_amd7930 {
  296. spinlock_t lock;
  297. void __iomem *regs;
  298. u32 flags;
  299. #define AMD7930_FLAG_PLAYBACK 0x00000001
  300. #define AMD7930_FLAG_CAPTURE 0x00000002
  301. struct amd7930_map map;
  302. struct snd_card *card;
  303. struct snd_pcm *pcm;
  304. struct snd_pcm_substream *playback_substream;
  305. struct snd_pcm_substream *capture_substream;
  306. /* Playback/Capture buffer state. */
  307. unsigned char *p_orig, *p_cur;
  308. int p_left;
  309. unsigned char *c_orig, *c_cur;
  310. int c_left;
  311. int rgain;
  312. int pgain;
  313. int mgain;
  314. struct platform_device *op;
  315. unsigned int irq;
  316. struct snd_amd7930 *next;
  317. };
  318. static struct snd_amd7930 *amd7930_list;
  319. /* Idle the AMD7930 chip. The amd->lock is not held. */
  320. static __inline__ void amd7930_idle(struct snd_amd7930 *amd)
  321. {
  322. unsigned long flags;
  323. spin_lock_irqsave(&amd->lock, flags);
  324. sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
  325. sbus_writeb(0, amd->regs + AMD7930_DR);
  326. spin_unlock_irqrestore(&amd->lock, flags);
  327. }
  328. /* Enable chip interrupts. The amd->lock is not held. */
  329. static __inline__ void amd7930_enable_ints(struct snd_amd7930 *amd)
  330. {
  331. unsigned long flags;
  332. spin_lock_irqsave(&amd->lock, flags);
  333. sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
  334. sbus_writeb(AM_INIT_ACTIVE, amd->regs + AMD7930_DR);
  335. spin_unlock_irqrestore(&amd->lock, flags);
  336. }
  337. /* Disable chip interrupts. The amd->lock is not held. */
  338. static __inline__ void amd7930_disable_ints(struct snd_amd7930 *amd)
  339. {
  340. unsigned long flags;
  341. spin_lock_irqsave(&amd->lock, flags);
  342. sbus_writeb(AMR_INIT, amd->regs + AMD7930_CR);
  343. sbus_writeb(AM_INIT_ACTIVE | AM_INIT_DISABLE_INTS, amd->regs + AMD7930_DR);
  344. spin_unlock_irqrestore(&amd->lock, flags);
  345. }
  346. /* Commit amd7930_map settings to the hardware.
  347. * The amd->lock is held and local interrupts are disabled.
  348. */
  349. static void __amd7930_write_map(struct snd_amd7930 *amd)
  350. {
  351. struct amd7930_map *map = &amd->map;
  352. sbus_writeb(AMR_MAP_GX, amd->regs + AMD7930_CR);
  353. sbus_writeb(((map->gx >> 0) & 0xff), amd->regs + AMD7930_DR);
  354. sbus_writeb(((map->gx >> 8) & 0xff), amd->regs + AMD7930_DR);
  355. sbus_writeb(AMR_MAP_GR, amd->regs + AMD7930_CR);
  356. sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR);
  357. sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR);
  358. sbus_writeb(AMR_MAP_STGR, amd->regs + AMD7930_CR);
  359. sbus_writeb(((map->stgr >> 0) & 0xff), amd->regs + AMD7930_DR);
  360. sbus_writeb(((map->stgr >> 8) & 0xff), amd->regs + AMD7930_DR);
  361. sbus_writeb(AMR_MAP_GER, amd->regs + AMD7930_CR);
  362. sbus_writeb(((map->ger >> 0) & 0xff), amd->regs + AMD7930_DR);
  363. sbus_writeb(((map->ger >> 8) & 0xff), amd->regs + AMD7930_DR);
  364. sbus_writeb(AMR_MAP_MMR1, amd->regs + AMD7930_CR);
  365. sbus_writeb(map->mmr1, amd->regs + AMD7930_DR);
  366. sbus_writeb(AMR_MAP_MMR2, amd->regs + AMD7930_CR);
  367. sbus_writeb(map->mmr2, amd->regs + AMD7930_DR);
  368. }
  369. /* gx, gr & stg gains. this table must contain 256 elements with
  370. * the 0th being "infinity" (the magic value 9008). The remaining
  371. * elements match sun's gain curve (but with higher resolution):
  372. * -18 to 0dB in .16dB steps then 0 to 12dB in .08dB steps.
  373. */
  374. static __const__ __u16 gx_coeff[256] = {
  375. 0x9008, 0x8b7c, 0x8b51, 0x8b45, 0x8b42, 0x8b3b, 0x8b36, 0x8b33,
  376. 0x8b32, 0x8b2a, 0x8b2b, 0x8b2c, 0x8b25, 0x8b23, 0x8b22, 0x8b22,
  377. 0x9122, 0x8b1a, 0x8aa3, 0x8aa3, 0x8b1c, 0x8aa6, 0x912d, 0x912b,
  378. 0x8aab, 0x8b12, 0x8aaa, 0x8ab2, 0x9132, 0x8ab4, 0x913c, 0x8abb,
  379. 0x9142, 0x9144, 0x9151, 0x8ad5, 0x8aeb, 0x8a79, 0x8a5a, 0x8a4a,
  380. 0x8b03, 0x91c2, 0x91bb, 0x8a3f, 0x8a33, 0x91b2, 0x9212, 0x9213,
  381. 0x8a2c, 0x921d, 0x8a23, 0x921a, 0x9222, 0x9223, 0x922d, 0x9231,
  382. 0x9234, 0x9242, 0x925b, 0x92dd, 0x92c1, 0x92b3, 0x92ab, 0x92a4,
  383. 0x92a2, 0x932b, 0x9341, 0x93d3, 0x93b2, 0x93a2, 0x943c, 0x94b2,
  384. 0x953a, 0x9653, 0x9782, 0x9e21, 0x9d23, 0x9cd2, 0x9c23, 0x9baa,
  385. 0x9bde, 0x9b33, 0x9b22, 0x9b1d, 0x9ab2, 0xa142, 0xa1e5, 0x9a3b,
  386. 0xa213, 0xa1a2, 0xa231, 0xa2eb, 0xa313, 0xa334, 0xa421, 0xa54b,
  387. 0xada4, 0xac23, 0xab3b, 0xaaab, 0xaa5c, 0xb1a3, 0xb2ca, 0xb3bd,
  388. 0xbe24, 0xbb2b, 0xba33, 0xc32b, 0xcb5a, 0xd2a2, 0xe31d, 0x0808,
  389. 0x72ba, 0x62c2, 0x5c32, 0x52db, 0x513e, 0x4cce, 0x43b2, 0x4243,
  390. 0x41b4, 0x3b12, 0x3bc3, 0x3df2, 0x34bd, 0x3334, 0x32c2, 0x3224,
  391. 0x31aa, 0x2a7b, 0x2aaa, 0x2b23, 0x2bba, 0x2c42, 0x2e23, 0x25bb,
  392. 0x242b, 0x240f, 0x231a, 0x22bb, 0x2241, 0x2223, 0x221f, 0x1a33,
  393. 0x1a4a, 0x1acd, 0x2132, 0x1b1b, 0x1b2c, 0x1b62, 0x1c12, 0x1c32,
  394. 0x1d1b, 0x1e71, 0x16b1, 0x1522, 0x1434, 0x1412, 0x1352, 0x1323,
  395. 0x1315, 0x12bc, 0x127a, 0x1235, 0x1226, 0x11a2, 0x1216, 0x0a2a,
  396. 0x11bc, 0x11d1, 0x1163, 0x0ac2, 0x0ab2, 0x0aab, 0x0b1b, 0x0b23,
  397. 0x0b33, 0x0c0f, 0x0bb3, 0x0c1b, 0x0c3e, 0x0cb1, 0x0d4c, 0x0ec1,
  398. 0x079a, 0x0614, 0x0521, 0x047c, 0x0422, 0x03b1, 0x03e3, 0x0333,
  399. 0x0322, 0x031c, 0x02aa, 0x02ba, 0x02f2, 0x0242, 0x0232, 0x0227,
  400. 0x0222, 0x021b, 0x01ad, 0x0212, 0x01b2, 0x01bb, 0x01cb, 0x01f6,
  401. 0x0152, 0x013a, 0x0133, 0x0131, 0x012c, 0x0123, 0x0122, 0x00a2,
  402. 0x011b, 0x011e, 0x0114, 0x00b1, 0x00aa, 0x00b3, 0x00bd, 0x00ba,
  403. 0x00c5, 0x00d3, 0x00f3, 0x0062, 0x0051, 0x0042, 0x003b, 0x0033,
  404. 0x0032, 0x002a, 0x002c, 0x0025, 0x0023, 0x0022, 0x001a, 0x0021,
  405. 0x001b, 0x001b, 0x001d, 0x0015, 0x0013, 0x0013, 0x0012, 0x0012,
  406. 0x000a, 0x000a, 0x0011, 0x0011, 0x000b, 0x000b, 0x000c, 0x000e,
  407. };
  408. static __const__ __u16 ger_coeff[] = {
  409. 0x431f, /* 5. dB */
  410. 0x331f, /* 5.5 dB */
  411. 0x40dd, /* 6. dB */
  412. 0x11dd, /* 6.5 dB */
  413. 0x440f, /* 7. dB */
  414. 0x411f, /* 7.5 dB */
  415. 0x311f, /* 8. dB */
  416. 0x5520, /* 8.5 dB */
  417. 0x10dd, /* 9. dB */
  418. 0x4211, /* 9.5 dB */
  419. 0x410f, /* 10. dB */
  420. 0x111f, /* 10.5 dB */
  421. 0x600b, /* 11. dB */
  422. 0x00dd, /* 11.5 dB */
  423. 0x4210, /* 12. dB */
  424. 0x110f, /* 13. dB */
  425. 0x7200, /* 14. dB */
  426. 0x2110, /* 15. dB */
  427. 0x2200, /* 15.9 dB */
  428. 0x000b, /* 16.9 dB */
  429. 0x000f /* 18. dB */
  430. };
  431. /* Update amd7930_map settings and program them into the hardware.
  432. * The amd->lock is held and local interrupts are disabled.
  433. */
  434. static void __amd7930_update_map(struct snd_amd7930 *amd)
  435. {
  436. struct amd7930_map *map = &amd->map;
  437. int level;
  438. map->gx = gx_coeff[amd->rgain];
  439. map->stgr = gx_coeff[amd->mgain];
  440. level = (amd->pgain * (256 + ARRAY_SIZE(ger_coeff))) >> 8;
  441. if (level >= 256) {
  442. map->ger = ger_coeff[level - 256];
  443. map->gr = gx_coeff[255];
  444. } else {
  445. map->ger = ger_coeff[0];
  446. map->gr = gx_coeff[level];
  447. }
  448. __amd7930_write_map(amd);
  449. }
  450. static irqreturn_t snd_amd7930_interrupt(int irq, void *dev_id)
  451. {
  452. struct snd_amd7930 *amd = dev_id;
  453. unsigned int elapsed;
  454. u8 ir;
  455. spin_lock(&amd->lock);
  456. elapsed = 0;
  457. ir = sbus_readb(amd->regs + AMD7930_IR);
  458. if (ir & AMR_IR_BBUF) {
  459. u8 byte;
  460. if (amd->flags & AMD7930_FLAG_PLAYBACK) {
  461. if (amd->p_left > 0) {
  462. byte = *(amd->p_cur++);
  463. amd->p_left--;
  464. sbus_writeb(byte, amd->regs + AMD7930_BBTB);
  465. if (amd->p_left == 0)
  466. elapsed |= AMD7930_FLAG_PLAYBACK;
  467. } else
  468. sbus_writeb(0, amd->regs + AMD7930_BBTB);
  469. } else if (amd->flags & AMD7930_FLAG_CAPTURE) {
  470. byte = sbus_readb(amd->regs + AMD7930_BBRB);
  471. if (amd->c_left > 0) {
  472. *(amd->c_cur++) = byte;
  473. amd->c_left--;
  474. if (amd->c_left == 0)
  475. elapsed |= AMD7930_FLAG_CAPTURE;
  476. }
  477. }
  478. }
  479. spin_unlock(&amd->lock);
  480. if (elapsed & AMD7930_FLAG_PLAYBACK)
  481. snd_pcm_period_elapsed(amd->playback_substream);
  482. else
  483. snd_pcm_period_elapsed(amd->capture_substream);
  484. return IRQ_HANDLED;
  485. }
  486. static int snd_amd7930_trigger(struct snd_amd7930 *amd, unsigned int flag, int cmd)
  487. {
  488. unsigned long flags;
  489. int result = 0;
  490. spin_lock_irqsave(&amd->lock, flags);
  491. if (cmd == SNDRV_PCM_TRIGGER_START) {
  492. if (!(amd->flags & flag)) {
  493. amd->flags |= flag;
  494. /* Enable B channel interrupts. */
  495. sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
  496. sbus_writeb(AM_MUX_MCR4_ENABLE_INTS, amd->regs + AMD7930_DR);
  497. }
  498. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  499. if (amd->flags & flag) {
  500. amd->flags &= ~flag;
  501. /* Disable B channel interrupts. */
  502. sbus_writeb(AMR_MUX_MCR4, amd->regs + AMD7930_CR);
  503. sbus_writeb(0, amd->regs + AMD7930_DR);
  504. }
  505. } else {
  506. result = -EINVAL;
  507. }
  508. spin_unlock_irqrestore(&amd->lock, flags);
  509. return result;
  510. }
  511. static int snd_amd7930_playback_trigger(struct snd_pcm_substream *substream,
  512. int cmd)
  513. {
  514. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  515. return snd_amd7930_trigger(amd, AMD7930_FLAG_PLAYBACK, cmd);
  516. }
  517. static int snd_amd7930_capture_trigger(struct snd_pcm_substream *substream,
  518. int cmd)
  519. {
  520. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  521. return snd_amd7930_trigger(amd, AMD7930_FLAG_CAPTURE, cmd);
  522. }
  523. static int snd_amd7930_playback_prepare(struct snd_pcm_substream *substream)
  524. {
  525. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  526. struct snd_pcm_runtime *runtime = substream->runtime;
  527. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  528. unsigned long flags;
  529. u8 new_mmr1;
  530. spin_lock_irqsave(&amd->lock, flags);
  531. amd->flags |= AMD7930_FLAG_PLAYBACK;
  532. /* Setup the pseudo-dma transfer pointers. */
  533. amd->p_orig = amd->p_cur = runtime->dma_area;
  534. amd->p_left = size;
  535. /* Put the chip into the correct encoding format. */
  536. new_mmr1 = amd->map.mmr1;
  537. if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
  538. new_mmr1 |= AM_MAP_MMR1_ALAW;
  539. else
  540. new_mmr1 &= ~AM_MAP_MMR1_ALAW;
  541. if (new_mmr1 != amd->map.mmr1) {
  542. amd->map.mmr1 = new_mmr1;
  543. __amd7930_update_map(amd);
  544. }
  545. spin_unlock_irqrestore(&amd->lock, flags);
  546. return 0;
  547. }
  548. static int snd_amd7930_capture_prepare(struct snd_pcm_substream *substream)
  549. {
  550. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  551. struct snd_pcm_runtime *runtime = substream->runtime;
  552. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  553. unsigned long flags;
  554. u8 new_mmr1;
  555. spin_lock_irqsave(&amd->lock, flags);
  556. amd->flags |= AMD7930_FLAG_CAPTURE;
  557. /* Setup the pseudo-dma transfer pointers. */
  558. amd->c_orig = amd->c_cur = runtime->dma_area;
  559. amd->c_left = size;
  560. /* Put the chip into the correct encoding format. */
  561. new_mmr1 = amd->map.mmr1;
  562. if (runtime->format == SNDRV_PCM_FORMAT_A_LAW)
  563. new_mmr1 |= AM_MAP_MMR1_ALAW;
  564. else
  565. new_mmr1 &= ~AM_MAP_MMR1_ALAW;
  566. if (new_mmr1 != amd->map.mmr1) {
  567. amd->map.mmr1 = new_mmr1;
  568. __amd7930_update_map(amd);
  569. }
  570. spin_unlock_irqrestore(&amd->lock, flags);
  571. return 0;
  572. }
  573. static snd_pcm_uframes_t snd_amd7930_playback_pointer(struct snd_pcm_substream *substream)
  574. {
  575. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  576. size_t ptr;
  577. if (!(amd->flags & AMD7930_FLAG_PLAYBACK))
  578. return 0;
  579. ptr = amd->p_cur - amd->p_orig;
  580. return bytes_to_frames(substream->runtime, ptr);
  581. }
  582. static snd_pcm_uframes_t snd_amd7930_capture_pointer(struct snd_pcm_substream *substream)
  583. {
  584. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  585. size_t ptr;
  586. if (!(amd->flags & AMD7930_FLAG_CAPTURE))
  587. return 0;
  588. ptr = amd->c_cur - amd->c_orig;
  589. return bytes_to_frames(substream->runtime, ptr);
  590. }
  591. /* Playback and capture have identical properties. */
  592. static const struct snd_pcm_hardware snd_amd7930_pcm_hw =
  593. {
  594. .info = (SNDRV_PCM_INFO_MMAP |
  595. SNDRV_PCM_INFO_MMAP_VALID |
  596. SNDRV_PCM_INFO_INTERLEAVED |
  597. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  598. SNDRV_PCM_INFO_HALF_DUPLEX),
  599. .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
  600. .rates = SNDRV_PCM_RATE_8000,
  601. .rate_min = 8000,
  602. .rate_max = 8000,
  603. .channels_min = 1,
  604. .channels_max = 1,
  605. .buffer_bytes_max = (64*1024),
  606. .period_bytes_min = 1,
  607. .period_bytes_max = (64*1024),
  608. .periods_min = 1,
  609. .periods_max = 1024,
  610. };
  611. static int snd_amd7930_playback_open(struct snd_pcm_substream *substream)
  612. {
  613. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  614. struct snd_pcm_runtime *runtime = substream->runtime;
  615. amd->playback_substream = substream;
  616. runtime->hw = snd_amd7930_pcm_hw;
  617. return 0;
  618. }
  619. static int snd_amd7930_capture_open(struct snd_pcm_substream *substream)
  620. {
  621. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  622. struct snd_pcm_runtime *runtime = substream->runtime;
  623. amd->capture_substream = substream;
  624. runtime->hw = snd_amd7930_pcm_hw;
  625. return 0;
  626. }
  627. static int snd_amd7930_playback_close(struct snd_pcm_substream *substream)
  628. {
  629. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  630. amd->playback_substream = NULL;
  631. return 0;
  632. }
  633. static int snd_amd7930_capture_close(struct snd_pcm_substream *substream)
  634. {
  635. struct snd_amd7930 *amd = snd_pcm_substream_chip(substream);
  636. amd->capture_substream = NULL;
  637. return 0;
  638. }
  639. static const struct snd_pcm_ops snd_amd7930_playback_ops = {
  640. .open = snd_amd7930_playback_open,
  641. .close = snd_amd7930_playback_close,
  642. .prepare = snd_amd7930_playback_prepare,
  643. .trigger = snd_amd7930_playback_trigger,
  644. .pointer = snd_amd7930_playback_pointer,
  645. };
  646. static const struct snd_pcm_ops snd_amd7930_capture_ops = {
  647. .open = snd_amd7930_capture_open,
  648. .close = snd_amd7930_capture_close,
  649. .prepare = snd_amd7930_capture_prepare,
  650. .trigger = snd_amd7930_capture_trigger,
  651. .pointer = snd_amd7930_capture_pointer,
  652. };
  653. static int snd_amd7930_pcm(struct snd_amd7930 *amd)
  654. {
  655. struct snd_pcm *pcm;
  656. int err;
  657. if ((err = snd_pcm_new(amd->card,
  658. /* ID */ "sun_amd7930",
  659. /* device */ 0,
  660. /* playback count */ 1,
  661. /* capture count */ 1, &pcm)) < 0)
  662. return err;
  663. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_amd7930_playback_ops);
  664. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_amd7930_capture_ops);
  665. pcm->private_data = amd;
  666. pcm->info_flags = 0;
  667. strcpy(pcm->name, amd->card->shortname);
  668. amd->pcm = pcm;
  669. snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  670. NULL, 64*1024, 64*1024);
  671. return 0;
  672. }
  673. #define VOLUME_MONITOR 0
  674. #define VOLUME_CAPTURE 1
  675. #define VOLUME_PLAYBACK 2
  676. static int snd_amd7930_info_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo)
  677. {
  678. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  679. uinfo->count = 1;
  680. uinfo->value.integer.min = 0;
  681. uinfo->value.integer.max = 255;
  682. return 0;
  683. }
  684. static int snd_amd7930_get_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
  685. {
  686. struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
  687. int type = kctl->private_value;
  688. int *swval;
  689. switch (type) {
  690. case VOLUME_MONITOR:
  691. swval = &amd->mgain;
  692. break;
  693. case VOLUME_CAPTURE:
  694. swval = &amd->rgain;
  695. break;
  696. case VOLUME_PLAYBACK:
  697. default:
  698. swval = &amd->pgain;
  699. break;
  700. }
  701. ucontrol->value.integer.value[0] = *swval;
  702. return 0;
  703. }
  704. static int snd_amd7930_put_volume(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol)
  705. {
  706. struct snd_amd7930 *amd = snd_kcontrol_chip(kctl);
  707. unsigned long flags;
  708. int type = kctl->private_value;
  709. int *swval, change;
  710. switch (type) {
  711. case VOLUME_MONITOR:
  712. swval = &amd->mgain;
  713. break;
  714. case VOLUME_CAPTURE:
  715. swval = &amd->rgain;
  716. break;
  717. case VOLUME_PLAYBACK:
  718. default:
  719. swval = &amd->pgain;
  720. break;
  721. }
  722. spin_lock_irqsave(&amd->lock, flags);
  723. if (*swval != ucontrol->value.integer.value[0]) {
  724. *swval = ucontrol->value.integer.value[0] & 0xff;
  725. __amd7930_update_map(amd);
  726. change = 1;
  727. } else
  728. change = 0;
  729. spin_unlock_irqrestore(&amd->lock, flags);
  730. return change;
  731. }
  732. static const struct snd_kcontrol_new amd7930_controls[] = {
  733. {
  734. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  735. .name = "Monitor Volume",
  736. .index = 0,
  737. .info = snd_amd7930_info_volume,
  738. .get = snd_amd7930_get_volume,
  739. .put = snd_amd7930_put_volume,
  740. .private_value = VOLUME_MONITOR,
  741. },
  742. {
  743. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  744. .name = "Capture Volume",
  745. .index = 0,
  746. .info = snd_amd7930_info_volume,
  747. .get = snd_amd7930_get_volume,
  748. .put = snd_amd7930_put_volume,
  749. .private_value = VOLUME_CAPTURE,
  750. },
  751. {
  752. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  753. .name = "Playback Volume",
  754. .index = 0,
  755. .info = snd_amd7930_info_volume,
  756. .get = snd_amd7930_get_volume,
  757. .put = snd_amd7930_put_volume,
  758. .private_value = VOLUME_PLAYBACK,
  759. },
  760. };
  761. static int snd_amd7930_mixer(struct snd_amd7930 *amd)
  762. {
  763. struct snd_card *card;
  764. int idx, err;
  765. if (snd_BUG_ON(!amd || !amd->card))
  766. return -EINVAL;
  767. card = amd->card;
  768. strcpy(card->mixername, card->shortname);
  769. for (idx = 0; idx < ARRAY_SIZE(amd7930_controls); idx++) {
  770. if ((err = snd_ctl_add(card,
  771. snd_ctl_new1(&amd7930_controls[idx], amd))) < 0)
  772. return err;
  773. }
  774. return 0;
  775. }
  776. static int snd_amd7930_free(struct snd_amd7930 *amd)
  777. {
  778. struct platform_device *op = amd->op;
  779. amd7930_idle(amd);
  780. if (amd->irq)
  781. free_irq(amd->irq, amd);
  782. if (amd->regs)
  783. of_iounmap(&op->resource[0], amd->regs,
  784. resource_size(&op->resource[0]));
  785. kfree(amd);
  786. return 0;
  787. }
  788. static int snd_amd7930_dev_free(struct snd_device *device)
  789. {
  790. struct snd_amd7930 *amd = device->device_data;
  791. return snd_amd7930_free(amd);
  792. }
  793. static const struct snd_device_ops snd_amd7930_dev_ops = {
  794. .dev_free = snd_amd7930_dev_free,
  795. };
  796. static int snd_amd7930_create(struct snd_card *card,
  797. struct platform_device *op,
  798. int irq, int dev,
  799. struct snd_amd7930 **ramd)
  800. {
  801. struct snd_amd7930 *amd;
  802. unsigned long flags;
  803. int err;
  804. *ramd = NULL;
  805. amd = kzalloc(sizeof(*amd), GFP_KERNEL);
  806. if (amd == NULL)
  807. return -ENOMEM;
  808. spin_lock_init(&amd->lock);
  809. amd->card = card;
  810. amd->op = op;
  811. amd->regs = of_ioremap(&op->resource[0], 0,
  812. resource_size(&op->resource[0]), "amd7930");
  813. if (!amd->regs) {
  814. snd_printk(KERN_ERR
  815. "amd7930-%d: Unable to map chip registers.\n", dev);
  816. kfree(amd);
  817. return -EIO;
  818. }
  819. amd7930_idle(amd);
  820. if (request_irq(irq, snd_amd7930_interrupt,
  821. IRQF_SHARED, "amd7930", amd)) {
  822. snd_printk(KERN_ERR "amd7930-%d: Unable to grab IRQ %d\n",
  823. dev, irq);
  824. snd_amd7930_free(amd);
  825. return -EBUSY;
  826. }
  827. amd->irq = irq;
  828. amd7930_enable_ints(amd);
  829. spin_lock_irqsave(&amd->lock, flags);
  830. amd->rgain = 128;
  831. amd->pgain = 200;
  832. amd->mgain = 0;
  833. memset(&amd->map, 0, sizeof(amd->map));
  834. amd->map.mmr1 = (AM_MAP_MMR1_GX | AM_MAP_MMR1_GER |
  835. AM_MAP_MMR1_GR | AM_MAP_MMR1_STG);
  836. amd->map.mmr2 = (AM_MAP_MMR2_LS | AM_MAP_MMR2_AINB);
  837. __amd7930_update_map(amd);
  838. /* Always MUX audio (Ba) to channel Bb. */
  839. sbus_writeb(AMR_MUX_MCR1, amd->regs + AMD7930_CR);
  840. sbus_writeb(AM_MUX_CHANNEL_Ba | (AM_MUX_CHANNEL_Bb << 4),
  841. amd->regs + AMD7930_DR);
  842. spin_unlock_irqrestore(&amd->lock, flags);
  843. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
  844. amd, &snd_amd7930_dev_ops)) < 0) {
  845. snd_amd7930_free(amd);
  846. return err;
  847. }
  848. *ramd = amd;
  849. return 0;
  850. }
  851. static int amd7930_sbus_probe(struct platform_device *op)
  852. {
  853. struct resource *rp = &op->resource[0];
  854. static int dev_num;
  855. struct snd_card *card;
  856. struct snd_amd7930 *amd;
  857. int err, irq;
  858. irq = op->archdata.irqs[0];
  859. if (dev_num >= SNDRV_CARDS)
  860. return -ENODEV;
  861. if (!enable[dev_num]) {
  862. dev_num++;
  863. return -ENOENT;
  864. }
  865. err = snd_card_new(&op->dev, index[dev_num], id[dev_num],
  866. THIS_MODULE, 0, &card);
  867. if (err < 0)
  868. return err;
  869. strcpy(card->driver, "AMD7930");
  870. strcpy(card->shortname, "Sun AMD7930");
  871. sprintf(card->longname, "%s at 0x%02lx:0x%08Lx, irq %d",
  872. card->shortname,
  873. rp->flags & 0xffL,
  874. (unsigned long long)rp->start,
  875. irq);
  876. if ((err = snd_amd7930_create(card, op,
  877. irq, dev_num, &amd)) < 0)
  878. goto out_err;
  879. if ((err = snd_amd7930_pcm(amd)) < 0)
  880. goto out_err;
  881. if ((err = snd_amd7930_mixer(amd)) < 0)
  882. goto out_err;
  883. if ((err = snd_card_register(card)) < 0)
  884. goto out_err;
  885. amd->next = amd7930_list;
  886. amd7930_list = amd;
  887. dev_num++;
  888. return 0;
  889. out_err:
  890. snd_card_free(card);
  891. return err;
  892. }
  893. static const struct of_device_id amd7930_match[] = {
  894. {
  895. .name = "audio",
  896. },
  897. {},
  898. };
  899. MODULE_DEVICE_TABLE(of, amd7930_match);
  900. static struct platform_driver amd7930_sbus_driver = {
  901. .driver = {
  902. .name = "audio",
  903. .of_match_table = amd7930_match,
  904. },
  905. .probe = amd7930_sbus_probe,
  906. };
  907. static int __init amd7930_init(void)
  908. {
  909. return platform_driver_register(&amd7930_sbus_driver);
  910. }
  911. static void __exit amd7930_exit(void)
  912. {
  913. struct snd_amd7930 *p = amd7930_list;
  914. while (p != NULL) {
  915. struct snd_amd7930 *next = p->next;
  916. snd_card_free(p->card);
  917. p = next;
  918. }
  919. amd7930_list = NULL;
  920. platform_driver_unregister(&amd7930_sbus_driver);
  921. }
  922. module_init(amd7930_init);
  923. module_exit(amd7930_exit);