zx-tdm.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ZTE's TDM driver
  4. *
  5. * Copyright (C) 2017 ZTE Ltd
  6. *
  7. * Author: Baoyou Xie <baoyou.xie@linaro.org>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/module.h>
  13. #include <sound/dmaengine_pcm.h>
  14. #include <sound/pcm_params.h>
  15. #include <sound/soc.h>
  16. #include <sound/soc-dai.h>
  17. #define REG_TIMING_CTRL 0x04
  18. #define REG_TX_FIFO_CTRL 0x0C
  19. #define REG_RX_FIFO_CTRL 0x10
  20. #define REG_INT_EN 0x1C
  21. #define REG_INT_STATUS 0x20
  22. #define REG_DATABUF 0x24
  23. #define REG_TS_MASK0 0x44
  24. #define REG_PROCESS_CTRL 0x54
  25. #define FIFO_CTRL_TX_RST BIT(0)
  26. #define FIFO_CTRL_RX_RST BIT(0)
  27. #define DEAGULT_FIFO_THRES GENMASK(4, 2)
  28. #define FIFO_CTRL_TX_DMA_EN BIT(1)
  29. #define FIFO_CTRL_RX_DMA_EN BIT(1)
  30. #define TX_FIFO_RST_MASK BIT(0)
  31. #define RX_FIFO_RST_MASK BIT(0)
  32. #define FIFOCTRL_TX_FIFO_RST BIT(0)
  33. #define FIFOCTRL_RX_FIFO_RST BIT(0)
  34. #define TXTH_MASK GENMASK(5, 2)
  35. #define RXTH_MASK GENMASK(5, 2)
  36. #define FIFOCTRL_THRESHOLD(x) ((x) << 2)
  37. #define TIMING_MS_MASK BIT(1)
  38. /*
  39. * 00: 8 clk cycles every timeslot
  40. * 01: 16 clk cycles every timeslot
  41. * 10: 32 clk cycles every timeslot
  42. */
  43. #define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
  44. #define TIMING_WIDTH_SHIFT 5
  45. #define TIMING_DEFAULT_WIDTH 0
  46. #define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
  47. #define TIMING_WIDTH_FACTOR 8
  48. #define TIMING_MASTER_MODE BIT(21)
  49. #define TIMING_LSB_FIRST BIT(20)
  50. #define TIMING_TS_NUM(x) (((x) - 1) << 7)
  51. #define TIMING_CLK_SEL_MASK GENMASK(2, 0)
  52. #define TIMING_CLK_SEL_DEF BIT(2)
  53. #define PROCESS_TX_EN BIT(0)
  54. #define PROCESS_RX_EN BIT(1)
  55. #define PROCESS_TDM_EN BIT(2)
  56. #define PROCESS_DISABLE_ALL 0
  57. #define INT_DISABLE_ALL 0
  58. #define INT_STATUS_MASK GENMASK(6, 0)
  59. struct zx_tdm_info {
  60. struct snd_dmaengine_dai_dma_data dma_playback;
  61. struct snd_dmaengine_dai_dma_data dma_capture;
  62. resource_size_t phy_addr;
  63. void __iomem *regbase;
  64. struct clk *dai_wclk;
  65. struct clk *dai_pclk;
  66. int master;
  67. struct device *dev;
  68. };
  69. static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
  70. {
  71. return readl_relaxed(tdm->regbase + reg);
  72. }
  73. static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
  74. {
  75. writel_relaxed(val, tdm->regbase + reg);
  76. }
  77. static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
  78. {
  79. unsigned long val;
  80. val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
  81. if (on)
  82. val |= PROCESS_TX_EN | PROCESS_TDM_EN;
  83. else
  84. val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
  85. zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
  86. }
  87. static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
  88. {
  89. unsigned long val;
  90. val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
  91. if (on)
  92. val |= PROCESS_RX_EN | PROCESS_TDM_EN;
  93. else
  94. val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
  95. zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
  96. }
  97. static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
  98. {
  99. unsigned long val;
  100. val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
  101. val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
  102. if (on)
  103. val |= FIFO_CTRL_TX_DMA_EN;
  104. else
  105. val &= ~FIFO_CTRL_TX_DMA_EN;
  106. zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);
  107. }
  108. static void zx_tdm_rx_dma_en(struct zx_tdm_info *tdm, bool on)
  109. {
  110. unsigned long val;
  111. val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);
  112. val |= FIFO_CTRL_RX_RST | DEAGULT_FIFO_THRES;
  113. if (on)
  114. val |= FIFO_CTRL_RX_DMA_EN;
  115. else
  116. val &= ~FIFO_CTRL_RX_DMA_EN;
  117. zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);
  118. }
  119. #define ZX_TDM_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
  120. #define ZX_TDM_FMTBIT \
  121. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_MU_LAW | \
  122. SNDRV_PCM_FMTBIT_A_LAW)
  123. static int zx_tdm_dai_probe(struct snd_soc_dai *dai)
  124. {
  125. struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
  126. snd_soc_dai_set_drvdata(dai, zx_tdm);
  127. zx_tdm->dma_playback.addr = zx_tdm->phy_addr + REG_DATABUF;
  128. zx_tdm->dma_playback.maxburst = 16;
  129. zx_tdm->dma_capture.addr = zx_tdm->phy_addr + REG_DATABUF;
  130. zx_tdm->dma_capture.maxburst = 16;
  131. snd_soc_dai_init_dma_data(dai, &zx_tdm->dma_playback,
  132. &zx_tdm->dma_capture);
  133. return 0;
  134. }
  135. static int zx_tdm_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  136. {
  137. struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(cpu_dai);
  138. unsigned long val;
  139. val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
  140. val &= ~(TIMING_SYNC_WIDTH_MASK | TIMING_MS_MASK);
  141. val |= TIMING_DEFAULT_WIDTH << TIMING_WIDTH_SHIFT;
  142. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  143. case SND_SOC_DAIFMT_CBM_CFM:
  144. tdm->master = 1;
  145. val |= TIMING_MASTER_MODE;
  146. break;
  147. case SND_SOC_DAIFMT_CBS_CFS:
  148. tdm->master = 0;
  149. val &= ~TIMING_MASTER_MODE;
  150. break;
  151. default:
  152. dev_err(cpu_dai->dev, "Unknown master/slave format\n");
  153. return -EINVAL;
  154. }
  155. zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
  156. return 0;
  157. }
  158. static int zx_tdm_hw_params(struct snd_pcm_substream *substream,
  159. struct snd_pcm_hw_params *params,
  160. struct snd_soc_dai *socdai)
  161. {
  162. struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(socdai);
  163. struct snd_dmaengine_dai_dma_data *dma_data;
  164. unsigned int ts_width = TIMING_DEFAULT_WIDTH;
  165. unsigned int ch_num = 32;
  166. unsigned int mask = 0;
  167. unsigned int ret = 0;
  168. unsigned long val;
  169. dma_data = snd_soc_dai_get_dma_data(socdai, substream);
  170. dma_data->addr_width = ch_num >> 3;
  171. switch (params_format(params)) {
  172. case SNDRV_PCM_FORMAT_MU_LAW:
  173. case SNDRV_PCM_FORMAT_A_LAW:
  174. case SNDRV_PCM_FORMAT_S16_LE:
  175. ts_width = 1;
  176. break;
  177. default:
  178. dev_err(socdai->dev, "Unknown data format\n");
  179. return -EINVAL;
  180. }
  181. val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
  182. val |= TIMING_TS_WIDTH(ts_width) | TIMING_TS_NUM(1);
  183. zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
  184. zx_tdm_writel(tdm, REG_TS_MASK0, mask);
  185. if (tdm->master)
  186. ret = clk_set_rate(tdm->dai_wclk,
  187. params_rate(params) * TIMING_WIDTH_FACTOR * ch_num);
  188. return ret;
  189. }
  190. static int zx_tdm_trigger(struct snd_pcm_substream *substream, int cmd,
  191. struct snd_soc_dai *dai)
  192. {
  193. int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
  194. struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
  195. unsigned int val;
  196. int ret = 0;
  197. switch (cmd) {
  198. case SNDRV_PCM_TRIGGER_START:
  199. if (capture) {
  200. val = zx_tdm_readl(zx_tdm, REG_RX_FIFO_CTRL);
  201. val |= FIFOCTRL_RX_FIFO_RST;
  202. zx_tdm_writel(zx_tdm, REG_RX_FIFO_CTRL, val);
  203. zx_tdm_rx_dma_en(zx_tdm, true);
  204. } else {
  205. val = zx_tdm_readl(zx_tdm, REG_TX_FIFO_CTRL);
  206. val |= FIFOCTRL_TX_FIFO_RST;
  207. zx_tdm_writel(zx_tdm, REG_TX_FIFO_CTRL, val);
  208. zx_tdm_tx_dma_en(zx_tdm, true);
  209. }
  210. break;
  211. case SNDRV_PCM_TRIGGER_RESUME:
  212. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  213. if (capture)
  214. zx_tdm_rx_en(zx_tdm, true);
  215. else
  216. zx_tdm_tx_en(zx_tdm, true);
  217. break;
  218. case SNDRV_PCM_TRIGGER_STOP:
  219. if (capture)
  220. zx_tdm_rx_dma_en(zx_tdm, false);
  221. else
  222. zx_tdm_tx_dma_en(zx_tdm, false);
  223. break;
  224. case SNDRV_PCM_TRIGGER_SUSPEND:
  225. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  226. if (capture)
  227. zx_tdm_rx_en(zx_tdm, false);
  228. else
  229. zx_tdm_tx_en(zx_tdm, false);
  230. break;
  231. default:
  232. ret = -EINVAL;
  233. break;
  234. }
  235. return ret;
  236. }
  237. static int zx_tdm_startup(struct snd_pcm_substream *substream,
  238. struct snd_soc_dai *dai)
  239. {
  240. struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
  241. int ret;
  242. ret = clk_prepare_enable(zx_tdm->dai_wclk);
  243. if (ret)
  244. return ret;
  245. ret = clk_prepare_enable(zx_tdm->dai_pclk);
  246. if (ret) {
  247. clk_disable_unprepare(zx_tdm->dai_wclk);
  248. return ret;
  249. }
  250. return 0;
  251. }
  252. static void zx_tdm_shutdown(struct snd_pcm_substream *substream,
  253. struct snd_soc_dai *dai)
  254. {
  255. struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
  256. clk_disable_unprepare(zx_tdm->dai_pclk);
  257. clk_disable_unprepare(zx_tdm->dai_wclk);
  258. }
  259. static const struct snd_soc_dai_ops zx_tdm_dai_ops = {
  260. .trigger = zx_tdm_trigger,
  261. .hw_params = zx_tdm_hw_params,
  262. .set_fmt = zx_tdm_set_fmt,
  263. .startup = zx_tdm_startup,
  264. .shutdown = zx_tdm_shutdown,
  265. };
  266. static const struct snd_soc_component_driver zx_tdm_component = {
  267. .name = "zx-tdm",
  268. };
  269. static void zx_tdm_init_state(struct zx_tdm_info *tdm)
  270. {
  271. unsigned int val;
  272. zx_tdm_writel(tdm, REG_PROCESS_CTRL, PROCESS_DISABLE_ALL);
  273. val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
  274. val |= TIMING_LSB_FIRST;
  275. val &= ~TIMING_CLK_SEL_MASK;
  276. val |= TIMING_CLK_SEL_DEF;
  277. zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
  278. zx_tdm_writel(tdm, REG_INT_EN, INT_DISABLE_ALL);
  279. /*
  280. * write INT_STATUS register to clear it.
  281. */
  282. zx_tdm_writel(tdm, REG_INT_STATUS, INT_STATUS_MASK);
  283. zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, FIFOCTRL_RX_FIFO_RST);
  284. zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, FIFOCTRL_TX_FIFO_RST);
  285. val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);
  286. val &= ~(RXTH_MASK | RX_FIFO_RST_MASK);
  287. val |= FIFOCTRL_THRESHOLD(8);
  288. zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);
  289. val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
  290. val &= ~(TXTH_MASK | TX_FIFO_RST_MASK);
  291. val |= FIFOCTRL_THRESHOLD(8);
  292. zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);
  293. }
  294. static struct snd_soc_dai_driver zx_tdm_dai = {
  295. .name = "zx-tdm-dai",
  296. .id = 0,
  297. .probe = zx_tdm_dai_probe,
  298. .playback = {
  299. .channels_min = 1,
  300. .channels_max = 4,
  301. .rates = ZX_TDM_RATES,
  302. .formats = ZX_TDM_FMTBIT,
  303. },
  304. .capture = {
  305. .channels_min = 1,
  306. .channels_max = 4,
  307. .rates = ZX_TDM_RATES,
  308. .formats = ZX_TDM_FMTBIT,
  309. },
  310. .ops = &zx_tdm_dai_ops,
  311. };
  312. static int zx_tdm_probe(struct platform_device *pdev)
  313. {
  314. struct of_phandle_args out_args;
  315. unsigned int dma_reg_offset;
  316. struct zx_tdm_info *zx_tdm;
  317. unsigned int dma_mask;
  318. struct resource *res;
  319. struct regmap *regmap_sysctrl;
  320. int ret;
  321. zx_tdm = devm_kzalloc(&pdev->dev, sizeof(*zx_tdm), GFP_KERNEL);
  322. if (!zx_tdm)
  323. return -ENOMEM;
  324. zx_tdm->dev = &pdev->dev;
  325. zx_tdm->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
  326. if (IS_ERR(zx_tdm->dai_wclk)) {
  327. dev_err(&pdev->dev, "Fail to get wclk\n");
  328. return PTR_ERR(zx_tdm->dai_wclk);
  329. }
  330. zx_tdm->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
  331. if (IS_ERR(zx_tdm->dai_pclk)) {
  332. dev_err(&pdev->dev, "Fail to get pclk\n");
  333. return PTR_ERR(zx_tdm->dai_pclk);
  334. }
  335. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  336. zx_tdm->phy_addr = res->start;
  337. zx_tdm->regbase = devm_ioremap_resource(&pdev->dev, res);
  338. if (IS_ERR(zx_tdm->regbase))
  339. return PTR_ERR(zx_tdm->regbase);
  340. ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
  341. "zte,tdm-dma-sysctrl", 2, 0, &out_args);
  342. if (ret) {
  343. dev_err(&pdev->dev, "Fail to get zte,tdm-dma-sysctrl\n");
  344. return ret;
  345. }
  346. dma_reg_offset = out_args.args[0];
  347. dma_mask = out_args.args[1];
  348. regmap_sysctrl = syscon_node_to_regmap(out_args.np);
  349. if (IS_ERR(regmap_sysctrl)) {
  350. of_node_put(out_args.np);
  351. return PTR_ERR(regmap_sysctrl);
  352. }
  353. regmap_update_bits(regmap_sysctrl, dma_reg_offset, dma_mask, dma_mask);
  354. of_node_put(out_args.np);
  355. zx_tdm_init_state(zx_tdm);
  356. platform_set_drvdata(pdev, zx_tdm);
  357. ret = devm_snd_soc_register_component(&pdev->dev, &zx_tdm_component,
  358. &zx_tdm_dai, 1);
  359. if (ret) {
  360. dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
  361. return ret;
  362. }
  363. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  364. if (ret)
  365. dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
  366. return ret;
  367. }
  368. static const struct of_device_id zx_tdm_dt_ids[] = {
  369. { .compatible = "zte,zx296718-tdm", },
  370. {}
  371. };
  372. MODULE_DEVICE_TABLE(of, zx_tdm_dt_ids);
  373. static struct platform_driver tdm_driver = {
  374. .probe = zx_tdm_probe,
  375. .driver = {
  376. .name = "zx-tdm",
  377. .of_match_table = zx_tdm_dt_ids,
  378. },
  379. };
  380. module_platform_driver(tdm_driver);
  381. MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
  382. MODULE_DESCRIPTION("ZTE TDM DAI driver");
  383. MODULE_LICENSE("GPL v2");