zx-i2s.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Linaro
  4. *
  5. * Author: Jun Nie <jun.nie@linaro.org>
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/device.h>
  9. #include <linux/init.h>
  10. #include <linux/io.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <sound/pcm.h>
  14. #include <sound/pcm_params.h>
  15. #include <sound/soc.h>
  16. #include <sound/soc-dai.h>
  17. #include <sound/core.h>
  18. #include <sound/dmaengine_pcm.h>
  19. #include <sound/initval.h>
  20. #define ZX_I2S_PROCESS_CTRL 0x04
  21. #define ZX_I2S_TIMING_CTRL 0x08
  22. #define ZX_I2S_FIFO_CTRL 0x0C
  23. #define ZX_I2S_FIFO_STATUS 0x10
  24. #define ZX_I2S_INT_EN 0x14
  25. #define ZX_I2S_INT_STATUS 0x18
  26. #define ZX_I2S_DATA 0x1C
  27. #define ZX_I2S_FRAME_CNTR 0x20
  28. #define I2S_DEAGULT_FIFO_THRES (0x10)
  29. #define I2S_MAX_FIFO_THRES (0x20)
  30. #define ZX_I2S_PROCESS_TX_EN (1 << 0)
  31. #define ZX_I2S_PROCESS_TX_DIS (0 << 0)
  32. #define ZX_I2S_PROCESS_RX_EN (1 << 1)
  33. #define ZX_I2S_PROCESS_RX_DIS (0 << 1)
  34. #define ZX_I2S_PROCESS_I2S_EN (1 << 2)
  35. #define ZX_I2S_PROCESS_I2S_DIS (0 << 2)
  36. #define ZX_I2S_TIMING_MAST (1 << 0)
  37. #define ZX_I2S_TIMING_SLAVE (0 << 0)
  38. #define ZX_I2S_TIMING_MS_MASK (1 << 0)
  39. #define ZX_I2S_TIMING_LOOP (1 << 1)
  40. #define ZX_I2S_TIMING_NOR (0 << 1)
  41. #define ZX_I2S_TIMING_LOOP_MASK (1 << 1)
  42. #define ZX_I2S_TIMING_PTNR (1 << 2)
  43. #define ZX_I2S_TIMING_NTPR (0 << 2)
  44. #define ZX_I2S_TIMING_PHASE_MASK (1 << 2)
  45. #define ZX_I2S_TIMING_TDM (1 << 3)
  46. #define ZX_I2S_TIMING_I2S (0 << 3)
  47. #define ZX_I2S_TIMING_TIMING_MASK (1 << 3)
  48. #define ZX_I2S_TIMING_LONG_SYNC (1 << 4)
  49. #define ZX_I2S_TIMING_SHORT_SYNC (0 << 4)
  50. #define ZX_I2S_TIMING_SYNC_MASK (1 << 4)
  51. #define ZX_I2S_TIMING_TEAK_EN (1 << 5)
  52. #define ZX_I2S_TIMING_TEAK_DIS (0 << 5)
  53. #define ZX_I2S_TIMING_TEAK_MASK (1 << 5)
  54. #define ZX_I2S_TIMING_STD_I2S (0 << 6)
  55. #define ZX_I2S_TIMING_MSB_JUSTIF (1 << 6)
  56. #define ZX_I2S_TIMING_LSB_JUSTIF (2 << 6)
  57. #define ZX_I2S_TIMING_ALIGN_MASK (3 << 6)
  58. #define ZX_I2S_TIMING_CHN_MASK (7 << 8)
  59. #define ZX_I2S_TIMING_CHN(x) ((x - 1) << 8)
  60. #define ZX_I2S_TIMING_LANE_MASK (3 << 11)
  61. #define ZX_I2S_TIMING_LANE(x) ((x - 1) << 11)
  62. #define ZX_I2S_TIMING_TSCFG_MASK (7 << 13)
  63. #define ZX_I2S_TIMING_TSCFG(x) (x << 13)
  64. #define ZX_I2S_TIMING_TS_WIDTH_MASK (0x1f << 16)
  65. #define ZX_I2S_TIMING_TS_WIDTH(x) ((x - 1) << 16)
  66. #define ZX_I2S_TIMING_DATA_SIZE_MASK (0x1f << 21)
  67. #define ZX_I2S_TIMING_DATA_SIZE(x) ((x - 1) << 21)
  68. #define ZX_I2S_TIMING_CFG_ERR_MASK (1 << 31)
  69. #define ZX_I2S_FIFO_CTRL_TX_RST (1 << 0)
  70. #define ZX_I2S_FIFO_CTRL_TX_RST_MASK (1 << 0)
  71. #define ZX_I2S_FIFO_CTRL_RX_RST (1 << 1)
  72. #define ZX_I2S_FIFO_CTRL_RX_RST_MASK (1 << 1)
  73. #define ZX_I2S_FIFO_CTRL_TX_DMA_EN (1 << 4)
  74. #define ZX_I2S_FIFO_CTRL_TX_DMA_DIS (0 << 4)
  75. #define ZX_I2S_FIFO_CTRL_TX_DMA_MASK (1 << 4)
  76. #define ZX_I2S_FIFO_CTRL_RX_DMA_EN (1 << 5)
  77. #define ZX_I2S_FIFO_CTRL_RX_DMA_DIS (0 << 5)
  78. #define ZX_I2S_FIFO_CTRL_RX_DMA_MASK (1 << 5)
  79. #define ZX_I2S_FIFO_CTRL_TX_THRES_MASK (0x1F << 8)
  80. #define ZX_I2S_FIFO_CTRL_RX_THRES_MASK (0x1F << 16)
  81. #define CLK_RAT (32 * 4)
  82. struct zx_i2s_info {
  83. struct snd_dmaengine_dai_dma_data dma_playback;
  84. struct snd_dmaengine_dai_dma_data dma_capture;
  85. struct clk *dai_wclk;
  86. struct clk *dai_pclk;
  87. void __iomem *reg_base;
  88. int master;
  89. resource_size_t mapbase;
  90. };
  91. static void zx_i2s_tx_en(void __iomem *base, bool on)
  92. {
  93. unsigned long val;
  94. val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
  95. if (on)
  96. val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;
  97. else
  98. val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);
  99. writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
  100. }
  101. static void zx_i2s_rx_en(void __iomem *base, bool on)
  102. {
  103. unsigned long val;
  104. val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
  105. if (on)
  106. val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;
  107. else
  108. val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);
  109. writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
  110. }
  111. static void zx_i2s_tx_dma_en(void __iomem *base, bool on)
  112. {
  113. unsigned long val;
  114. val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
  115. val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);
  116. if (on)
  117. val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;
  118. else
  119. val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;
  120. writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
  121. }
  122. static void zx_i2s_rx_dma_en(void __iomem *base, bool on)
  123. {
  124. unsigned long val;
  125. val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
  126. val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);
  127. if (on)
  128. val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;
  129. else
  130. val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;
  131. writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
  132. }
  133. #define ZX_I2S_RATES \
  134. (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
  135. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  136. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000| \
  137. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  138. #define ZX_I2S_FMTBIT \
  139. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
  140. SNDRV_PCM_FMTBIT_S32_LE)
  141. static int zx_i2s_dai_probe(struct snd_soc_dai *dai)
  142. {
  143. struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
  144. snd_soc_dai_set_drvdata(dai, zx_i2s);
  145. zx_i2s->dma_playback.addr = zx_i2s->mapbase + ZX_I2S_DATA;
  146. zx_i2s->dma_playback.maxburst = 16;
  147. zx_i2s->dma_capture.addr = zx_i2s->mapbase + ZX_I2S_DATA;
  148. zx_i2s->dma_capture.maxburst = 16;
  149. snd_soc_dai_init_dma_data(dai, &zx_i2s->dma_playback,
  150. &zx_i2s->dma_capture);
  151. return 0;
  152. }
  153. static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
  154. {
  155. struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
  156. unsigned long val;
  157. val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
  158. val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |
  159. ZX_I2S_TIMING_TEAK_MASK | ZX_I2S_TIMING_SYNC_MASK |
  160. ZX_I2S_TIMING_MS_MASK);
  161. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  162. case SND_SOC_DAIFMT_I2S:
  163. val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);
  164. break;
  165. case SND_SOC_DAIFMT_LEFT_J:
  166. val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);
  167. break;
  168. case SND_SOC_DAIFMT_RIGHT_J:
  169. val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);
  170. break;
  171. default:
  172. dev_err(cpu_dai->dev, "Unknown i2s timing\n");
  173. return -EINVAL;
  174. }
  175. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  176. case SND_SOC_DAIFMT_CBM_CFM:
  177. /* Codec is master, and I2S is slave. */
  178. i2s->master = 0;
  179. val |= ZX_I2S_TIMING_SLAVE;
  180. break;
  181. case SND_SOC_DAIFMT_CBS_CFS:
  182. /* Codec is slave, and I2S is master. */
  183. i2s->master = 1;
  184. val |= ZX_I2S_TIMING_MAST;
  185. break;
  186. default:
  187. dev_err(cpu_dai->dev, "Unknown master/slave format\n");
  188. return -EINVAL;
  189. }
  190. writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
  191. return 0;
  192. }
  193. static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
  194. struct snd_pcm_hw_params *params,
  195. struct snd_soc_dai *socdai)
  196. {
  197. struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(socdai);
  198. struct snd_dmaengine_dai_dma_data *dma_data;
  199. unsigned int lane, ch_num, len, ret = 0;
  200. unsigned int ts_width = 32;
  201. unsigned long val;
  202. unsigned long chn_cfg;
  203. dma_data = snd_soc_dai_get_dma_data(socdai, substream);
  204. dma_data->addr_width = ts_width >> 3;
  205. val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
  206. val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |
  207. ZX_I2S_TIMING_LANE_MASK | ZX_I2S_TIMING_CHN_MASK |
  208. ZX_I2S_TIMING_TSCFG_MASK);
  209. switch (params_format(params)) {
  210. case SNDRV_PCM_FORMAT_S16_LE:
  211. len = 16;
  212. break;
  213. case SNDRV_PCM_FORMAT_S24_LE:
  214. len = 24;
  215. break;
  216. case SNDRV_PCM_FORMAT_S32_LE:
  217. len = 32;
  218. break;
  219. default:
  220. dev_err(socdai->dev, "Unknown data format\n");
  221. return -EINVAL;
  222. }
  223. val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);
  224. ch_num = params_channels(params);
  225. switch (ch_num) {
  226. case 1:
  227. lane = 1;
  228. chn_cfg = 2;
  229. break;
  230. case 2:
  231. case 4:
  232. case 6:
  233. case 8:
  234. lane = ch_num / 2;
  235. chn_cfg = 3;
  236. break;
  237. default:
  238. dev_err(socdai->dev, "Not support channel num %d\n", ch_num);
  239. return -EINVAL;
  240. }
  241. val |= ZX_I2S_TIMING_LANE(lane);
  242. val |= ZX_I2S_TIMING_TSCFG(chn_cfg);
  243. val |= ZX_I2S_TIMING_CHN(ch_num);
  244. writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
  245. if (i2s->master)
  246. ret = clk_set_rate(i2s->dai_wclk,
  247. params_rate(params) * ch_num * CLK_RAT);
  248. return ret;
  249. }
  250. static int zx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  251. struct snd_soc_dai *dai)
  252. {
  253. struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
  254. int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
  255. int ret = 0;
  256. switch (cmd) {
  257. case SNDRV_PCM_TRIGGER_START:
  258. if (capture)
  259. zx_i2s_rx_dma_en(zx_i2s->reg_base, true);
  260. else
  261. zx_i2s_tx_dma_en(zx_i2s->reg_base, true);
  262. fallthrough;
  263. case SNDRV_PCM_TRIGGER_RESUME:
  264. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  265. if (capture)
  266. zx_i2s_rx_en(zx_i2s->reg_base, true);
  267. else
  268. zx_i2s_tx_en(zx_i2s->reg_base, true);
  269. break;
  270. case SNDRV_PCM_TRIGGER_STOP:
  271. if (capture)
  272. zx_i2s_rx_dma_en(zx_i2s->reg_base, false);
  273. else
  274. zx_i2s_tx_dma_en(zx_i2s->reg_base, false);
  275. fallthrough;
  276. case SNDRV_PCM_TRIGGER_SUSPEND:
  277. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  278. if (capture)
  279. zx_i2s_rx_en(zx_i2s->reg_base, false);
  280. else
  281. zx_i2s_tx_en(zx_i2s->reg_base, false);
  282. break;
  283. default:
  284. ret = -EINVAL;
  285. break;
  286. }
  287. return ret;
  288. }
  289. static int zx_i2s_startup(struct snd_pcm_substream *substream,
  290. struct snd_soc_dai *dai)
  291. {
  292. struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
  293. int ret;
  294. ret = clk_prepare_enable(zx_i2s->dai_wclk);
  295. if (ret)
  296. return ret;
  297. ret = clk_prepare_enable(zx_i2s->dai_pclk);
  298. if (ret) {
  299. clk_disable_unprepare(zx_i2s->dai_wclk);
  300. return ret;
  301. }
  302. return ret;
  303. }
  304. static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
  305. struct snd_soc_dai *dai)
  306. {
  307. struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
  308. clk_disable_unprepare(zx_i2s->dai_wclk);
  309. clk_disable_unprepare(zx_i2s->dai_pclk);
  310. }
  311. static const struct snd_soc_dai_ops zx_i2s_dai_ops = {
  312. .trigger = zx_i2s_trigger,
  313. .hw_params = zx_i2s_hw_params,
  314. .set_fmt = zx_i2s_set_fmt,
  315. .startup = zx_i2s_startup,
  316. .shutdown = zx_i2s_shutdown,
  317. };
  318. static const struct snd_soc_component_driver zx_i2s_component = {
  319. .name = "zx-i2s",
  320. };
  321. static struct snd_soc_dai_driver zx_i2s_dai = {
  322. .name = "zx-i2s-dai",
  323. .id = 0,
  324. .probe = zx_i2s_dai_probe,
  325. .playback = {
  326. .channels_min = 1,
  327. .channels_max = 8,
  328. .rates = ZX_I2S_RATES,
  329. .formats = ZX_I2S_FMTBIT,
  330. },
  331. .capture = {
  332. .channels_min = 1,
  333. .channels_max = 2,
  334. .rates = ZX_I2S_RATES,
  335. .formats = ZX_I2S_FMTBIT,
  336. },
  337. .ops = &zx_i2s_dai_ops,
  338. };
  339. static int zx_i2s_probe(struct platform_device *pdev)
  340. {
  341. struct resource *res;
  342. struct zx_i2s_info *zx_i2s;
  343. int ret;
  344. zx_i2s = devm_kzalloc(&pdev->dev, sizeof(*zx_i2s), GFP_KERNEL);
  345. if (!zx_i2s)
  346. return -ENOMEM;
  347. zx_i2s->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
  348. if (IS_ERR(zx_i2s->dai_wclk)) {
  349. dev_err(&pdev->dev, "Fail to get wclk\n");
  350. return PTR_ERR(zx_i2s->dai_wclk);
  351. }
  352. zx_i2s->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
  353. if (IS_ERR(zx_i2s->dai_pclk)) {
  354. dev_err(&pdev->dev, "Fail to get pclk\n");
  355. return PTR_ERR(zx_i2s->dai_pclk);
  356. }
  357. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  358. zx_i2s->mapbase = res->start;
  359. zx_i2s->reg_base = devm_ioremap_resource(&pdev->dev, res);
  360. if (IS_ERR(zx_i2s->reg_base)) {
  361. dev_err(&pdev->dev, "ioremap failed!\n");
  362. return PTR_ERR(zx_i2s->reg_base);
  363. }
  364. writel_relaxed(0, zx_i2s->reg_base + ZX_I2S_FIFO_CTRL);
  365. platform_set_drvdata(pdev, zx_i2s);
  366. ret = devm_snd_soc_register_component(&pdev->dev, &zx_i2s_component,
  367. &zx_i2s_dai, 1);
  368. if (ret) {
  369. dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
  370. return ret;
  371. }
  372. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  373. if (ret)
  374. dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
  375. return ret;
  376. }
  377. static const struct of_device_id zx_i2s_dt_ids[] = {
  378. { .compatible = "zte,zx296702-i2s", },
  379. {}
  380. };
  381. MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
  382. static struct platform_driver i2s_driver = {
  383. .probe = zx_i2s_probe,
  384. .driver = {
  385. .name = "zx-i2s",
  386. .of_match_table = zx_i2s_dt_ids,
  387. },
  388. };
  389. module_platform_driver(i2s_driver);
  390. MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
  391. MODULE_DESCRIPTION("ZTE I2S SoC DAI");
  392. MODULE_LICENSE("GPL");