xtfpga-i2s.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Xtfpga I2S controller driver
  4. *
  5. * Copyright (c) 2014 Cadence Design Systems Inc.
  6. */
  7. #include <linux/clk.h>
  8. #include <linux/io.h>
  9. #include <linux/module.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm_runtime.h>
  13. #include <sound/pcm_params.h>
  14. #include <sound/soc.h>
  15. #define DRV_NAME "xtfpga-i2s"
  16. #define XTFPGA_I2S_VERSION 0x00
  17. #define XTFPGA_I2S_CONFIG 0x04
  18. #define XTFPGA_I2S_INT_MASK 0x08
  19. #define XTFPGA_I2S_INT_STATUS 0x0c
  20. #define XTFPGA_I2S_CHAN0_DATA 0x10
  21. #define XTFPGA_I2S_CHAN1_DATA 0x14
  22. #define XTFPGA_I2S_CHAN2_DATA 0x18
  23. #define XTFPGA_I2S_CHAN3_DATA 0x1c
  24. #define XTFPGA_I2S_CONFIG_TX_ENABLE 0x1
  25. #define XTFPGA_I2S_CONFIG_INT_ENABLE 0x2
  26. #define XTFPGA_I2S_CONFIG_LEFT 0x4
  27. #define XTFPGA_I2S_CONFIG_RATIO_BASE 8
  28. #define XTFPGA_I2S_CONFIG_RATIO_MASK 0x0000ff00
  29. #define XTFPGA_I2S_CONFIG_RES_BASE 16
  30. #define XTFPGA_I2S_CONFIG_RES_MASK 0x003f0000
  31. #define XTFPGA_I2S_CONFIG_LEVEL_BASE 24
  32. #define XTFPGA_I2S_CONFIG_LEVEL_MASK 0x0f000000
  33. #define XTFPGA_I2S_CONFIG_CHANNEL_BASE 28
  34. #define XTFPGA_I2S_INT_UNDERRUN 0x1
  35. #define XTFPGA_I2S_INT_LEVEL 0x2
  36. #define XTFPGA_I2S_INT_VALID 0x3
  37. #define XTFPGA_I2S_FIFO_SIZE 8192
  38. /*
  39. * I2S controller operation:
  40. *
  41. * Enabling TX: output 1 period of zeros (starting with left channel)
  42. * and then queued data.
  43. *
  44. * Level status and interrupt: whenever FIFO level is below FIFO trigger,
  45. * level status is 1 and an IRQ is asserted (if enabled).
  46. *
  47. * Underrun status and interrupt: whenever FIFO is empty, underrun status
  48. * is 1 and an IRQ is asserted (if enabled).
  49. */
  50. struct xtfpga_i2s {
  51. struct device *dev;
  52. struct clk *clk;
  53. struct regmap *regmap;
  54. void __iomem *regs;
  55. /* current playback substream. NULL if not playing.
  56. *
  57. * Access to that field is synchronized between the interrupt handler
  58. * and userspace through RCU.
  59. *
  60. * Interrupt handler (threaded part) does PIO on substream data in RCU
  61. * read-side critical section. Trigger callback sets and clears the
  62. * pointer when the playback is started and stopped with
  63. * rcu_assign_pointer. When userspace is about to free the playback
  64. * stream in the pcm_close callback it synchronizes with the interrupt
  65. * handler by means of synchronize_rcu call.
  66. */
  67. struct snd_pcm_substream __rcu *tx_substream;
  68. unsigned (*tx_fn)(struct xtfpga_i2s *i2s,
  69. struct snd_pcm_runtime *runtime,
  70. unsigned tx_ptr);
  71. unsigned tx_ptr; /* next frame index in the sample buffer */
  72. /* current fifo level estimate.
  73. * Doesn't have to be perfectly accurate, but must be not less than
  74. * the actual FIFO level in order to avoid stall on push attempt.
  75. */
  76. unsigned tx_fifo_level;
  77. /* FIFO level at which level interrupt occurs */
  78. unsigned tx_fifo_low;
  79. /* maximal FIFO level */
  80. unsigned tx_fifo_high;
  81. };
  82. static bool xtfpga_i2s_wr_reg(struct device *dev, unsigned int reg)
  83. {
  84. return reg >= XTFPGA_I2S_CONFIG;
  85. }
  86. static bool xtfpga_i2s_rd_reg(struct device *dev, unsigned int reg)
  87. {
  88. return reg < XTFPGA_I2S_CHAN0_DATA;
  89. }
  90. static bool xtfpga_i2s_volatile_reg(struct device *dev, unsigned int reg)
  91. {
  92. return reg == XTFPGA_I2S_INT_STATUS;
  93. }
  94. static const struct regmap_config xtfpga_i2s_regmap_config = {
  95. .reg_bits = 32,
  96. .reg_stride = 4,
  97. .val_bits = 32,
  98. .max_register = XTFPGA_I2S_CHAN3_DATA,
  99. .writeable_reg = xtfpga_i2s_wr_reg,
  100. .readable_reg = xtfpga_i2s_rd_reg,
  101. .volatile_reg = xtfpga_i2s_volatile_reg,
  102. .cache_type = REGCACHE_FLAT,
  103. };
  104. /* Generate functions that do PIO from TX DMA area to FIFO for all supported
  105. * stream formats.
  106. * Functions will be called xtfpga_pcm_tx_<channels>x<sample bits>, e.g.
  107. * xtfpga_pcm_tx_2x16 for 16-bit stereo.
  108. *
  109. * FIFO consists of 32-bit words, one word per channel, always 2 channels.
  110. * If I2S interface is configured with smaller sample resolution, only
  111. * the LSB of each word is used.
  112. */
  113. #define xtfpga_pcm_tx_fn(channels, sample_bits) \
  114. static unsigned xtfpga_pcm_tx_##channels##x##sample_bits( \
  115. struct xtfpga_i2s *i2s, struct snd_pcm_runtime *runtime, \
  116. unsigned tx_ptr) \
  117. { \
  118. const u##sample_bits (*p)[channels] = \
  119. (void *)runtime->dma_area; \
  120. \
  121. for (; i2s->tx_fifo_level < i2s->tx_fifo_high; \
  122. i2s->tx_fifo_level += 2) { \
  123. iowrite32(p[tx_ptr][0], \
  124. i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
  125. iowrite32(p[tx_ptr][channels - 1], \
  126. i2s->regs + XTFPGA_I2S_CHAN0_DATA); \
  127. if (++tx_ptr >= runtime->buffer_size) \
  128. tx_ptr = 0; \
  129. } \
  130. return tx_ptr; \
  131. }
  132. xtfpga_pcm_tx_fn(1, 16)
  133. xtfpga_pcm_tx_fn(2, 16)
  134. xtfpga_pcm_tx_fn(1, 32)
  135. xtfpga_pcm_tx_fn(2, 32)
  136. #undef xtfpga_pcm_tx_fn
  137. static bool xtfpga_pcm_push_tx(struct xtfpga_i2s *i2s)
  138. {
  139. struct snd_pcm_substream *tx_substream;
  140. bool tx_active;
  141. rcu_read_lock();
  142. tx_substream = rcu_dereference(i2s->tx_substream);
  143. tx_active = tx_substream && snd_pcm_running(tx_substream);
  144. if (tx_active) {
  145. unsigned tx_ptr = READ_ONCE(i2s->tx_ptr);
  146. unsigned new_tx_ptr = i2s->tx_fn(i2s, tx_substream->runtime,
  147. tx_ptr);
  148. cmpxchg(&i2s->tx_ptr, tx_ptr, new_tx_ptr);
  149. }
  150. rcu_read_unlock();
  151. return tx_active;
  152. }
  153. static void xtfpga_pcm_refill_fifo(struct xtfpga_i2s *i2s)
  154. {
  155. unsigned int_status;
  156. unsigned i;
  157. regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
  158. &int_status);
  159. for (i = 0; i < 2; ++i) {
  160. bool tx_active = xtfpga_pcm_push_tx(i2s);
  161. regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
  162. XTFPGA_I2S_INT_VALID);
  163. if (tx_active)
  164. regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS,
  165. &int_status);
  166. if (!tx_active ||
  167. !(int_status & XTFPGA_I2S_INT_LEVEL))
  168. break;
  169. /* After the push the level IRQ is still asserted,
  170. * means FIFO level is below tx_fifo_low. Estimate
  171. * it as tx_fifo_low.
  172. */
  173. i2s->tx_fifo_level = i2s->tx_fifo_low;
  174. }
  175. if (!(int_status & XTFPGA_I2S_INT_LEVEL))
  176. regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
  177. XTFPGA_I2S_INT_VALID);
  178. else if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
  179. regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK,
  180. XTFPGA_I2S_INT_UNDERRUN);
  181. if (!(int_status & XTFPGA_I2S_INT_UNDERRUN))
  182. regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
  183. XTFPGA_I2S_CONFIG_INT_ENABLE |
  184. XTFPGA_I2S_CONFIG_TX_ENABLE,
  185. XTFPGA_I2S_CONFIG_INT_ENABLE |
  186. XTFPGA_I2S_CONFIG_TX_ENABLE);
  187. else
  188. regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
  189. XTFPGA_I2S_CONFIG_INT_ENABLE |
  190. XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
  191. }
  192. static irqreturn_t xtfpga_i2s_threaded_irq_handler(int irq, void *dev_id)
  193. {
  194. struct xtfpga_i2s *i2s = dev_id;
  195. struct snd_pcm_substream *tx_substream;
  196. unsigned config, int_status, int_mask;
  197. regmap_read(i2s->regmap, XTFPGA_I2S_CONFIG, &config);
  198. regmap_read(i2s->regmap, XTFPGA_I2S_INT_MASK, &int_mask);
  199. regmap_read(i2s->regmap, XTFPGA_I2S_INT_STATUS, &int_status);
  200. if (!(config & XTFPGA_I2S_CONFIG_INT_ENABLE) ||
  201. !(int_status & int_mask & XTFPGA_I2S_INT_VALID))
  202. return IRQ_NONE;
  203. /* Update FIFO level estimate in accordance with interrupt status
  204. * register.
  205. */
  206. if (int_status & XTFPGA_I2S_INT_UNDERRUN) {
  207. i2s->tx_fifo_level = 0;
  208. regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
  209. XTFPGA_I2S_CONFIG_TX_ENABLE, 0);
  210. } else {
  211. /* The FIFO isn't empty, but is below tx_fifo_low. Estimate
  212. * it as tx_fifo_low.
  213. */
  214. i2s->tx_fifo_level = i2s->tx_fifo_low;
  215. }
  216. rcu_read_lock();
  217. tx_substream = rcu_dereference(i2s->tx_substream);
  218. if (tx_substream && snd_pcm_running(tx_substream)) {
  219. snd_pcm_period_elapsed(tx_substream);
  220. if (int_status & XTFPGA_I2S_INT_UNDERRUN)
  221. dev_dbg_ratelimited(i2s->dev, "%s: underrun\n",
  222. __func__);
  223. }
  224. rcu_read_unlock();
  225. /* Refill FIFO, update allowed IRQ reasons, enable IRQ if FIFO is
  226. * not empty.
  227. */
  228. xtfpga_pcm_refill_fifo(i2s);
  229. return IRQ_HANDLED;
  230. }
  231. static int xtfpga_i2s_startup(struct snd_pcm_substream *substream,
  232. struct snd_soc_dai *dai)
  233. {
  234. struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  235. snd_soc_dai_set_dma_data(dai, substream, i2s);
  236. return 0;
  237. }
  238. static int xtfpga_i2s_hw_params(struct snd_pcm_substream *substream,
  239. struct snd_pcm_hw_params *params,
  240. struct snd_soc_dai *dai)
  241. {
  242. struct xtfpga_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  243. unsigned srate = params_rate(params);
  244. unsigned channels = params_channels(params);
  245. unsigned period_size = params_period_size(params);
  246. unsigned sample_size = snd_pcm_format_width(params_format(params));
  247. unsigned freq, ratio, level;
  248. int err;
  249. regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
  250. XTFPGA_I2S_CONFIG_RES_MASK,
  251. sample_size << XTFPGA_I2S_CONFIG_RES_BASE);
  252. freq = 256 * srate;
  253. err = clk_set_rate(i2s->clk, freq);
  254. if (err < 0)
  255. return err;
  256. /* ratio field of the config register controls MCLK->I2S clock
  257. * derivation: I2S clock = MCLK / (2 * (ratio + 2)).
  258. *
  259. * So with MCLK = 256 * sample rate ratio is 0 for 32 bit stereo
  260. * and 2 for 16 bit stereo.
  261. */
  262. ratio = (freq - (srate * sample_size * 8)) /
  263. (srate * sample_size * 4);
  264. regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
  265. XTFPGA_I2S_CONFIG_RATIO_MASK,
  266. ratio << XTFPGA_I2S_CONFIG_RATIO_BASE);
  267. i2s->tx_fifo_low = XTFPGA_I2S_FIFO_SIZE / 2;
  268. /* period_size * 2: FIFO always gets 2 samples per frame */
  269. for (level = 1;
  270. i2s->tx_fifo_low / 2 >= period_size * 2 &&
  271. level < (XTFPGA_I2S_CONFIG_LEVEL_MASK >>
  272. XTFPGA_I2S_CONFIG_LEVEL_BASE); ++level)
  273. i2s->tx_fifo_low /= 2;
  274. i2s->tx_fifo_high = 2 * i2s->tx_fifo_low;
  275. regmap_update_bits(i2s->regmap, XTFPGA_I2S_CONFIG,
  276. XTFPGA_I2S_CONFIG_LEVEL_MASK,
  277. level << XTFPGA_I2S_CONFIG_LEVEL_BASE);
  278. dev_dbg(i2s->dev,
  279. "%s srate: %u, channels: %u, sample_size: %u, period_size: %u\n",
  280. __func__, srate, channels, sample_size, period_size);
  281. dev_dbg(i2s->dev, "%s freq: %u, ratio: %u, level: %u\n",
  282. __func__, freq, ratio, level);
  283. return 0;
  284. }
  285. static int xtfpga_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
  286. unsigned int fmt)
  287. {
  288. if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
  289. return -EINVAL;
  290. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  291. return -EINVAL;
  292. if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
  293. return -EINVAL;
  294. return 0;
  295. }
  296. /* PCM */
  297. static const struct snd_pcm_hardware xtfpga_pcm_hardware = {
  298. .info = SNDRV_PCM_INFO_INTERLEAVED |
  299. SNDRV_PCM_INFO_MMAP_VALID |
  300. SNDRV_PCM_INFO_BLOCK_TRANSFER,
  301. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  302. SNDRV_PCM_FMTBIT_S32_LE,
  303. .channels_min = 1,
  304. .channels_max = 2,
  305. .period_bytes_min = 2,
  306. .period_bytes_max = XTFPGA_I2S_FIFO_SIZE / 2 * 8,
  307. .periods_min = 2,
  308. .periods_max = XTFPGA_I2S_FIFO_SIZE * 8 / 2,
  309. .buffer_bytes_max = XTFPGA_I2S_FIFO_SIZE * 8,
  310. .fifo_size = 16,
  311. };
  312. static int xtfpga_pcm_open(struct snd_soc_component *component,
  313. struct snd_pcm_substream *substream)
  314. {
  315. struct snd_pcm_runtime *runtime = substream->runtime;
  316. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  317. void *p;
  318. snd_soc_set_runtime_hwparams(substream, &xtfpga_pcm_hardware);
  319. p = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
  320. runtime->private_data = p;
  321. return 0;
  322. }
  323. static int xtfpga_pcm_close(struct snd_soc_component *component,
  324. struct snd_pcm_substream *substream)
  325. {
  326. synchronize_rcu();
  327. return 0;
  328. }
  329. static int xtfpga_pcm_hw_params(struct snd_soc_component *component,
  330. struct snd_pcm_substream *substream,
  331. struct snd_pcm_hw_params *hw_params)
  332. {
  333. struct snd_pcm_runtime *runtime = substream->runtime;
  334. struct xtfpga_i2s *i2s = runtime->private_data;
  335. unsigned channels = params_channels(hw_params);
  336. switch (channels) {
  337. case 1:
  338. case 2:
  339. break;
  340. default:
  341. return -EINVAL;
  342. }
  343. switch (params_format(hw_params)) {
  344. case SNDRV_PCM_FORMAT_S16_LE:
  345. i2s->tx_fn = (channels == 1) ?
  346. xtfpga_pcm_tx_1x16 :
  347. xtfpga_pcm_tx_2x16;
  348. break;
  349. case SNDRV_PCM_FORMAT_S32_LE:
  350. i2s->tx_fn = (channels == 1) ?
  351. xtfpga_pcm_tx_1x32 :
  352. xtfpga_pcm_tx_2x32;
  353. break;
  354. default:
  355. return -EINVAL;
  356. }
  357. return 0;
  358. }
  359. static int xtfpga_pcm_trigger(struct snd_soc_component *component,
  360. struct snd_pcm_substream *substream, int cmd)
  361. {
  362. int ret = 0;
  363. struct snd_pcm_runtime *runtime = substream->runtime;
  364. struct xtfpga_i2s *i2s = runtime->private_data;
  365. switch (cmd) {
  366. case SNDRV_PCM_TRIGGER_START:
  367. case SNDRV_PCM_TRIGGER_RESUME:
  368. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  369. WRITE_ONCE(i2s->tx_ptr, 0);
  370. rcu_assign_pointer(i2s->tx_substream, substream);
  371. xtfpga_pcm_refill_fifo(i2s);
  372. break;
  373. case SNDRV_PCM_TRIGGER_STOP:
  374. case SNDRV_PCM_TRIGGER_SUSPEND:
  375. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  376. rcu_assign_pointer(i2s->tx_substream, NULL);
  377. break;
  378. default:
  379. ret = -EINVAL;
  380. break;
  381. }
  382. return ret;
  383. }
  384. static snd_pcm_uframes_t xtfpga_pcm_pointer(struct snd_soc_component *component,
  385. struct snd_pcm_substream *substream)
  386. {
  387. struct snd_pcm_runtime *runtime = substream->runtime;
  388. struct xtfpga_i2s *i2s = runtime->private_data;
  389. snd_pcm_uframes_t pos = READ_ONCE(i2s->tx_ptr);
  390. return pos < runtime->buffer_size ? pos : 0;
  391. }
  392. static int xtfpga_pcm_new(struct snd_soc_component *component,
  393. struct snd_soc_pcm_runtime *rtd)
  394. {
  395. struct snd_card *card = rtd->card->snd_card;
  396. size_t size = xtfpga_pcm_hardware.buffer_bytes_max;
  397. snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
  398. card->dev, size, size);
  399. return 0;
  400. }
  401. static const struct snd_soc_component_driver xtfpga_i2s_component = {
  402. .name = DRV_NAME,
  403. .open = xtfpga_pcm_open,
  404. .close = xtfpga_pcm_close,
  405. .hw_params = xtfpga_pcm_hw_params,
  406. .trigger = xtfpga_pcm_trigger,
  407. .pointer = xtfpga_pcm_pointer,
  408. .pcm_construct = xtfpga_pcm_new,
  409. };
  410. static const struct snd_soc_dai_ops xtfpga_i2s_dai_ops = {
  411. .startup = xtfpga_i2s_startup,
  412. .hw_params = xtfpga_i2s_hw_params,
  413. .set_fmt = xtfpga_i2s_set_fmt,
  414. };
  415. static struct snd_soc_dai_driver xtfpga_i2s_dai[] = {
  416. {
  417. .name = "xtfpga-i2s",
  418. .id = 0,
  419. .playback = {
  420. .channels_min = 1,
  421. .channels_max = 2,
  422. .rates = SNDRV_PCM_RATE_8000_96000,
  423. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  424. SNDRV_PCM_FMTBIT_S32_LE,
  425. },
  426. .ops = &xtfpga_i2s_dai_ops,
  427. },
  428. };
  429. static int xtfpga_i2s_runtime_suspend(struct device *dev)
  430. {
  431. struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
  432. clk_disable_unprepare(i2s->clk);
  433. return 0;
  434. }
  435. static int xtfpga_i2s_runtime_resume(struct device *dev)
  436. {
  437. struct xtfpga_i2s *i2s = dev_get_drvdata(dev);
  438. int ret;
  439. ret = clk_prepare_enable(i2s->clk);
  440. if (ret) {
  441. dev_err(dev, "clk_prepare_enable failed: %d\n", ret);
  442. return ret;
  443. }
  444. return 0;
  445. }
  446. static int xtfpga_i2s_probe(struct platform_device *pdev)
  447. {
  448. struct xtfpga_i2s *i2s;
  449. int err, irq;
  450. i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
  451. if (!i2s) {
  452. err = -ENOMEM;
  453. goto err;
  454. }
  455. platform_set_drvdata(pdev, i2s);
  456. i2s->dev = &pdev->dev;
  457. dev_dbg(&pdev->dev, "dev: %p, i2s: %p\n", &pdev->dev, i2s);
  458. i2s->regs = devm_platform_ioremap_resource(pdev, 0);
  459. if (IS_ERR(i2s->regs)) {
  460. err = PTR_ERR(i2s->regs);
  461. goto err;
  462. }
  463. i2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,
  464. &xtfpga_i2s_regmap_config);
  465. if (IS_ERR(i2s->regmap)) {
  466. dev_err(&pdev->dev, "regmap init failed\n");
  467. err = PTR_ERR(i2s->regmap);
  468. goto err;
  469. }
  470. i2s->clk = devm_clk_get(&pdev->dev, NULL);
  471. if (IS_ERR(i2s->clk)) {
  472. dev_err(&pdev->dev, "couldn't get clock\n");
  473. err = PTR_ERR(i2s->clk);
  474. goto err;
  475. }
  476. regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG,
  477. (0x1 << XTFPGA_I2S_CONFIG_CHANNEL_BASE));
  478. regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS, XTFPGA_I2S_INT_VALID);
  479. regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, XTFPGA_I2S_INT_UNDERRUN);
  480. irq = platform_get_irq(pdev, 0);
  481. if (irq < 0) {
  482. err = irq;
  483. goto err;
  484. }
  485. err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  486. xtfpga_i2s_threaded_irq_handler,
  487. IRQF_SHARED | IRQF_ONESHOT,
  488. pdev->name, i2s);
  489. if (err < 0) {
  490. dev_err(&pdev->dev, "request_irq failed\n");
  491. goto err;
  492. }
  493. err = devm_snd_soc_register_component(&pdev->dev,
  494. &xtfpga_i2s_component,
  495. xtfpga_i2s_dai,
  496. ARRAY_SIZE(xtfpga_i2s_dai));
  497. if (err < 0) {
  498. dev_err(&pdev->dev, "couldn't register component\n");
  499. goto err;
  500. }
  501. pm_runtime_enable(&pdev->dev);
  502. if (!pm_runtime_enabled(&pdev->dev)) {
  503. err = xtfpga_i2s_runtime_resume(&pdev->dev);
  504. if (err)
  505. goto err_pm_disable;
  506. }
  507. return 0;
  508. err_pm_disable:
  509. pm_runtime_disable(&pdev->dev);
  510. err:
  511. dev_err(&pdev->dev, "%s: err = %d\n", __func__, err);
  512. return err;
  513. }
  514. static int xtfpga_i2s_remove(struct platform_device *pdev)
  515. {
  516. struct xtfpga_i2s *i2s = dev_get_drvdata(&pdev->dev);
  517. if (i2s->regmap && !IS_ERR(i2s->regmap)) {
  518. regmap_write(i2s->regmap, XTFPGA_I2S_CONFIG, 0);
  519. regmap_write(i2s->regmap, XTFPGA_I2S_INT_MASK, 0);
  520. regmap_write(i2s->regmap, XTFPGA_I2S_INT_STATUS,
  521. XTFPGA_I2S_INT_VALID);
  522. }
  523. pm_runtime_disable(&pdev->dev);
  524. if (!pm_runtime_status_suspended(&pdev->dev))
  525. xtfpga_i2s_runtime_suspend(&pdev->dev);
  526. return 0;
  527. }
  528. #ifdef CONFIG_OF
  529. static const struct of_device_id xtfpga_i2s_of_match[] = {
  530. { .compatible = "cdns,xtfpga-i2s", },
  531. {},
  532. };
  533. MODULE_DEVICE_TABLE(of, xtfpga_i2s_of_match);
  534. #endif
  535. static const struct dev_pm_ops xtfpga_i2s_pm_ops = {
  536. SET_RUNTIME_PM_OPS(xtfpga_i2s_runtime_suspend,
  537. xtfpga_i2s_runtime_resume, NULL)
  538. };
  539. static struct platform_driver xtfpga_i2s_driver = {
  540. .probe = xtfpga_i2s_probe,
  541. .remove = xtfpga_i2s_remove,
  542. .driver = {
  543. .name = "xtfpga-i2s",
  544. .of_match_table = of_match_ptr(xtfpga_i2s_of_match),
  545. .pm = &xtfpga_i2s_pm_ops,
  546. },
  547. };
  548. module_platform_driver(xtfpga_i2s_driver);
  549. MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
  550. MODULE_DESCRIPTION("xtfpga I2S controller driver");
  551. MODULE_LICENSE("GPL v2");