xlnx_spdif.c 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338
  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Xilinx ASoC SPDIF audio support
  4. //
  5. // Copyright (C) 2018 Xilinx, Inc.
  6. //
  7. // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
  8. //
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/platform_device.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/soc.h>
  17. #define XLNX_SPDIF_RATES \
  18. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
  19. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
  20. SNDRV_PCM_RATE_192000)
  21. #define XLNX_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
  22. #define XSPDIF_IRQ_STS_REG 0x20
  23. #define XSPDIF_IRQ_ENABLE_REG 0x28
  24. #define XSPDIF_SOFT_RESET_REG 0x40
  25. #define XSPDIF_CONTROL_REG 0x44
  26. #define XSPDIF_CHAN_0_STS_REG 0x4C
  27. #define XSPDIF_GLOBAL_IRQ_ENABLE_REG 0x1C
  28. #define XSPDIF_CH_A_USER_DATA_REG_0 0x64
  29. #define XSPDIF_CORE_ENABLE_MASK BIT(0)
  30. #define XSPDIF_FIFO_FLUSH_MASK BIT(1)
  31. #define XSPDIF_CH_STS_MASK BIT(5)
  32. #define XSPDIF_GLOBAL_IRQ_ENABLE BIT(31)
  33. #define XSPDIF_CLOCK_CONFIG_BITS_MASK GENMASK(5, 2)
  34. #define XSPDIF_CLOCK_CONFIG_BITS_SHIFT 2
  35. #define XSPDIF_SOFT_RESET_VALUE 0xA
  36. #define MAX_CHANNELS 2
  37. #define AES_SAMPLE_WIDTH 32
  38. #define CH_STATUS_UPDATE_TIMEOUT 40
  39. struct spdif_dev_data {
  40. u32 mode;
  41. u32 aclk;
  42. bool rx_chsts_updated;
  43. void __iomem *base;
  44. struct clk *axi_clk;
  45. wait_queue_head_t chsts_q;
  46. };
  47. static irqreturn_t xlnx_spdifrx_irq_handler(int irq, void *arg)
  48. {
  49. u32 val;
  50. struct spdif_dev_data *ctx = arg;
  51. val = readl(ctx->base + XSPDIF_IRQ_STS_REG);
  52. if (val & XSPDIF_CH_STS_MASK) {
  53. writel(val & XSPDIF_CH_STS_MASK,
  54. ctx->base + XSPDIF_IRQ_STS_REG);
  55. val = readl(ctx->base +
  56. XSPDIF_IRQ_ENABLE_REG);
  57. writel(val & ~XSPDIF_CH_STS_MASK,
  58. ctx->base + XSPDIF_IRQ_ENABLE_REG);
  59. ctx->rx_chsts_updated = true;
  60. wake_up_interruptible(&ctx->chsts_q);
  61. return IRQ_HANDLED;
  62. }
  63. return IRQ_NONE;
  64. }
  65. static int xlnx_spdif_startup(struct snd_pcm_substream *substream,
  66. struct snd_soc_dai *dai)
  67. {
  68. u32 val;
  69. struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
  70. val = readl(ctx->base + XSPDIF_CONTROL_REG);
  71. val |= XSPDIF_FIFO_FLUSH_MASK;
  72. writel(val, ctx->base + XSPDIF_CONTROL_REG);
  73. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  74. writel(XSPDIF_CH_STS_MASK,
  75. ctx->base + XSPDIF_IRQ_ENABLE_REG);
  76. writel(XSPDIF_GLOBAL_IRQ_ENABLE,
  77. ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG);
  78. }
  79. return 0;
  80. }
  81. static void xlnx_spdif_shutdown(struct snd_pcm_substream *substream,
  82. struct snd_soc_dai *dai)
  83. {
  84. struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
  85. writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
  86. }
  87. static int xlnx_spdif_hw_params(struct snd_pcm_substream *substream,
  88. struct snd_pcm_hw_params *params,
  89. struct snd_soc_dai *dai)
  90. {
  91. u32 val, clk_div, clk_cfg;
  92. struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
  93. clk_div = DIV_ROUND_CLOSEST(ctx->aclk, MAX_CHANNELS * AES_SAMPLE_WIDTH *
  94. params_rate(params));
  95. switch (clk_div) {
  96. case 4:
  97. clk_cfg = 0;
  98. break;
  99. case 8:
  100. clk_cfg = 1;
  101. break;
  102. case 16:
  103. clk_cfg = 2;
  104. break;
  105. case 24:
  106. clk_cfg = 3;
  107. break;
  108. case 32:
  109. clk_cfg = 4;
  110. break;
  111. case 48:
  112. clk_cfg = 5;
  113. break;
  114. case 64:
  115. clk_cfg = 6;
  116. break;
  117. default:
  118. return -EINVAL;
  119. }
  120. val = readl(ctx->base + XSPDIF_CONTROL_REG);
  121. val &= ~XSPDIF_CLOCK_CONFIG_BITS_MASK;
  122. val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT;
  123. writel(val, ctx->base + XSPDIF_CONTROL_REG);
  124. return 0;
  125. }
  126. static int rx_stream_detect(struct snd_soc_dai *dai)
  127. {
  128. int err;
  129. struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
  130. unsigned long jiffies = msecs_to_jiffies(CH_STATUS_UPDATE_TIMEOUT);
  131. /* start capture only if stream is detected within 40ms timeout */
  132. err = wait_event_interruptible_timeout(ctx->chsts_q,
  133. ctx->rx_chsts_updated,
  134. jiffies);
  135. if (!err) {
  136. dev_err(dai->dev, "No streaming audio detected!\n");
  137. return -EINVAL;
  138. }
  139. ctx->rx_chsts_updated = false;
  140. return 0;
  141. }
  142. static int xlnx_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
  143. struct snd_soc_dai *dai)
  144. {
  145. u32 val;
  146. int ret = 0;
  147. struct spdif_dev_data *ctx = dev_get_drvdata(dai->dev);
  148. val = readl(ctx->base + XSPDIF_CONTROL_REG);
  149. switch (cmd) {
  150. case SNDRV_PCM_TRIGGER_START:
  151. case SNDRV_PCM_TRIGGER_RESUME:
  152. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  153. val |= XSPDIF_CORE_ENABLE_MASK;
  154. writel(val, ctx->base + XSPDIF_CONTROL_REG);
  155. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  156. ret = rx_stream_detect(dai);
  157. break;
  158. case SNDRV_PCM_TRIGGER_STOP:
  159. case SNDRV_PCM_TRIGGER_SUSPEND:
  160. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  161. val &= ~XSPDIF_CORE_ENABLE_MASK;
  162. writel(val, ctx->base + XSPDIF_CONTROL_REG);
  163. break;
  164. default:
  165. ret = -EINVAL;
  166. }
  167. return ret;
  168. }
  169. static const struct snd_soc_dai_ops xlnx_spdif_dai_ops = {
  170. .startup = xlnx_spdif_startup,
  171. .shutdown = xlnx_spdif_shutdown,
  172. .trigger = xlnx_spdif_trigger,
  173. .hw_params = xlnx_spdif_hw_params,
  174. };
  175. static struct snd_soc_dai_driver xlnx_spdif_tx_dai = {
  176. .name = "xlnx_spdif_tx",
  177. .playback = {
  178. .channels_min = 2,
  179. .channels_max = 2,
  180. .rates = XLNX_SPDIF_RATES,
  181. .formats = XLNX_SPDIF_FORMATS,
  182. },
  183. .ops = &xlnx_spdif_dai_ops,
  184. };
  185. static struct snd_soc_dai_driver xlnx_spdif_rx_dai = {
  186. .name = "xlnx_spdif_rx",
  187. .capture = {
  188. .channels_min = 2,
  189. .channels_max = 2,
  190. .rates = XLNX_SPDIF_RATES,
  191. .formats = XLNX_SPDIF_FORMATS,
  192. },
  193. .ops = &xlnx_spdif_dai_ops,
  194. };
  195. static const struct snd_soc_component_driver xlnx_spdif_component = {
  196. .name = "xlnx-spdif",
  197. };
  198. static const struct of_device_id xlnx_spdif_of_match[] = {
  199. { .compatible = "xlnx,spdif-2.0", },
  200. {},
  201. };
  202. MODULE_DEVICE_TABLE(of, xlnx_spdif_of_match);
  203. static int xlnx_spdif_probe(struct platform_device *pdev)
  204. {
  205. int ret;
  206. struct resource *res;
  207. struct snd_soc_dai_driver *dai_drv;
  208. struct spdif_dev_data *ctx;
  209. struct device *dev = &pdev->dev;
  210. struct device_node *node = dev->of_node;
  211. ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
  212. if (!ctx)
  213. return -ENOMEM;
  214. ctx->axi_clk = devm_clk_get(dev, "s_axi_aclk");
  215. if (IS_ERR(ctx->axi_clk)) {
  216. ret = PTR_ERR(ctx->axi_clk);
  217. dev_err(dev, "failed to get s_axi_aclk(%d)\n", ret);
  218. return ret;
  219. }
  220. ret = clk_prepare_enable(ctx->axi_clk);
  221. if (ret) {
  222. dev_err(dev, "failed to enable s_axi_aclk(%d)\n", ret);
  223. return ret;
  224. }
  225. ctx->base = devm_platform_ioremap_resource(pdev, 0);
  226. if (IS_ERR(ctx->base)) {
  227. ret = PTR_ERR(ctx->base);
  228. goto clk_err;
  229. }
  230. ret = of_property_read_u32(node, "xlnx,spdif-mode", &ctx->mode);
  231. if (ret < 0) {
  232. dev_err(dev, "cannot get SPDIF mode\n");
  233. goto clk_err;
  234. }
  235. if (ctx->mode) {
  236. dai_drv = &xlnx_spdif_tx_dai;
  237. } else {
  238. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  239. if (!res) {
  240. dev_err(dev, "No IRQ resource found\n");
  241. ret = -ENODEV;
  242. goto clk_err;
  243. }
  244. ret = devm_request_irq(dev, res->start,
  245. xlnx_spdifrx_irq_handler,
  246. 0, "XLNX_SPDIF_RX", ctx);
  247. if (ret) {
  248. dev_err(dev, "spdif rx irq request failed\n");
  249. ret = -ENODEV;
  250. goto clk_err;
  251. }
  252. init_waitqueue_head(&ctx->chsts_q);
  253. dai_drv = &xlnx_spdif_rx_dai;
  254. }
  255. ret = of_property_read_u32(node, "xlnx,aud_clk_i", &ctx->aclk);
  256. if (ret < 0) {
  257. dev_err(dev, "cannot get aud_clk_i value\n");
  258. goto clk_err;
  259. }
  260. dev_set_drvdata(dev, ctx);
  261. ret = devm_snd_soc_register_component(dev, &xlnx_spdif_component,
  262. dai_drv, 1);
  263. if (ret) {
  264. dev_err(dev, "SPDIF component registration failed\n");
  265. goto clk_err;
  266. }
  267. writel(XSPDIF_SOFT_RESET_VALUE, ctx->base + XSPDIF_SOFT_RESET_REG);
  268. dev_info(dev, "%s DAI registered\n", dai_drv->name);
  269. clk_err:
  270. clk_disable_unprepare(ctx->axi_clk);
  271. return ret;
  272. }
  273. static int xlnx_spdif_remove(struct platform_device *pdev)
  274. {
  275. struct spdif_dev_data *ctx = dev_get_drvdata(&pdev->dev);
  276. clk_disable_unprepare(ctx->axi_clk);
  277. return 0;
  278. }
  279. static struct platform_driver xlnx_spdif_driver = {
  280. .driver = {
  281. .name = "xlnx-spdif",
  282. .of_match_table = xlnx_spdif_of_match,
  283. },
  284. .probe = xlnx_spdif_probe,
  285. .remove = xlnx_spdif_remove,
  286. };
  287. module_platform_driver(xlnx_spdif_driver);
  288. MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
  289. MODULE_DESCRIPTION("XILINX SPDIF driver");
  290. MODULE_LICENSE("GPL v2");