ux500_msp_i2s.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2012
  4. *
  5. * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
  6. * for ST-Ericsson.
  7. *
  8. * License terms:
  9. */
  10. #ifndef UX500_MSP_I2S_H
  11. #define UX500_MSP_I2S_H
  12. #include <linux/platform_device.h>
  13. #include <linux/platform_data/asoc-ux500-msp.h>
  14. #define MSP_INPUT_FREQ_APB 48000000
  15. /*** Stereo mode. Used for APB data accesses as 16 bits accesses (mono),
  16. * 32 bits accesses (stereo).
  17. ***/
  18. enum msp_stereo_mode {
  19. MSP_MONO,
  20. MSP_STEREO
  21. };
  22. /* Direction (Transmit/Receive mode) */
  23. enum msp_direction {
  24. MSP_TX = 1,
  25. MSP_RX = 2
  26. };
  27. /* Transmit and receive configuration register */
  28. #define MSP_BIG_ENDIAN 0x00000000
  29. #define MSP_LITTLE_ENDIAN 0x00001000
  30. #define MSP_UNEXPECTED_FS_ABORT 0x00000000
  31. #define MSP_UNEXPECTED_FS_IGNORE 0x00008000
  32. #define MSP_NON_MODE_BIT_MASK 0x00009000
  33. /* Global configuration register */
  34. #define RX_ENABLE 0x00000001
  35. #define RX_FIFO_ENABLE 0x00000002
  36. #define RX_SYNC_SRG 0x00000010
  37. #define RX_CLK_POL_RISING 0x00000020
  38. #define RX_CLK_SEL_SRG 0x00000040
  39. #define TX_ENABLE 0x00000100
  40. #define TX_FIFO_ENABLE 0x00000200
  41. #define TX_SYNC_SRG_PROG 0x00001800
  42. #define TX_SYNC_SRG_AUTO 0x00001000
  43. #define TX_CLK_POL_RISING 0x00002000
  44. #define TX_CLK_SEL_SRG 0x00004000
  45. #define TX_EXTRA_DELAY_ENABLE 0x00008000
  46. #define SRG_ENABLE 0x00010000
  47. #define FRAME_GEN_ENABLE 0x00100000
  48. #define SRG_CLK_SEL_APB 0x00000000
  49. #define RX_FIFO_SYNC_HI 0x00000000
  50. #define TX_FIFO_SYNC_HI 0x00000000
  51. #define SPI_CLK_MODE_NORMAL 0x00000000
  52. #define MSP_FRAME_SIZE_AUTO -1
  53. #define MSP_DR 0x00
  54. #define MSP_GCR 0x04
  55. #define MSP_TCF 0x08
  56. #define MSP_RCF 0x0c
  57. #define MSP_SRG 0x10
  58. #define MSP_FLR 0x14
  59. #define MSP_DMACR 0x18
  60. #define MSP_IMSC 0x20
  61. #define MSP_RIS 0x24
  62. #define MSP_MIS 0x28
  63. #define MSP_ICR 0x2c
  64. #define MSP_MCR 0x30
  65. #define MSP_RCV 0x34
  66. #define MSP_RCM 0x38
  67. #define MSP_TCE0 0x40
  68. #define MSP_TCE1 0x44
  69. #define MSP_TCE2 0x48
  70. #define MSP_TCE3 0x4c
  71. #define MSP_RCE0 0x60
  72. #define MSP_RCE1 0x64
  73. #define MSP_RCE2 0x68
  74. #define MSP_RCE3 0x6c
  75. #define MSP_IODLY 0x70
  76. #define MSP_ITCR 0x80
  77. #define MSP_ITIP 0x84
  78. #define MSP_ITOP 0x88
  79. #define MSP_TSTDR 0x8c
  80. #define MSP_PID0 0xfe0
  81. #define MSP_PID1 0xfe4
  82. #define MSP_PID2 0xfe8
  83. #define MSP_PID3 0xfec
  84. #define MSP_CID0 0xff0
  85. #define MSP_CID1 0xff4
  86. #define MSP_CID2 0xff8
  87. #define MSP_CID3 0xffc
  88. /* Protocol dependant parameters list */
  89. #define RX_ENABLE_MASK BIT(0)
  90. #define RX_FIFO_ENABLE_MASK BIT(1)
  91. #define RX_FSYNC_MASK BIT(2)
  92. #define DIRECT_COMPANDING_MASK BIT(3)
  93. #define RX_SYNC_SEL_MASK BIT(4)
  94. #define RX_CLK_POL_MASK BIT(5)
  95. #define RX_CLK_SEL_MASK BIT(6)
  96. #define LOOPBACK_MASK BIT(7)
  97. #define TX_ENABLE_MASK BIT(8)
  98. #define TX_FIFO_ENABLE_MASK BIT(9)
  99. #define TX_FSYNC_MASK BIT(10)
  100. #define TX_MSP_TDR_TSR BIT(11)
  101. #define TX_SYNC_SEL_MASK (BIT(12) | BIT(11))
  102. #define TX_CLK_POL_MASK BIT(13)
  103. #define TX_CLK_SEL_MASK BIT(14)
  104. #define TX_EXTRA_DELAY_MASK BIT(15)
  105. #define SRG_ENABLE_MASK BIT(16)
  106. #define SRG_CLK_POL_MASK BIT(17)
  107. #define SRG_CLK_SEL_MASK (BIT(19) | BIT(18))
  108. #define FRAME_GEN_EN_MASK BIT(20)
  109. #define SPI_CLK_MODE_MASK (BIT(22) | BIT(21))
  110. #define SPI_BURST_MODE_MASK BIT(23)
  111. #define RXEN_SHIFT 0
  112. #define RFFEN_SHIFT 1
  113. #define RFSPOL_SHIFT 2
  114. #define DCM_SHIFT 3
  115. #define RFSSEL_SHIFT 4
  116. #define RCKPOL_SHIFT 5
  117. #define RCKSEL_SHIFT 6
  118. #define LBM_SHIFT 7
  119. #define TXEN_SHIFT 8
  120. #define TFFEN_SHIFT 9
  121. #define TFSPOL_SHIFT 10
  122. #define TFSSEL_SHIFT 11
  123. #define TCKPOL_SHIFT 13
  124. #define TCKSEL_SHIFT 14
  125. #define TXDDL_SHIFT 15
  126. #define SGEN_SHIFT 16
  127. #define SCKPOL_SHIFT 17
  128. #define SCKSEL_SHIFT 18
  129. #define FGEN_SHIFT 20
  130. #define SPICKM_SHIFT 21
  131. #define TBSWAP_SHIFT 28
  132. #define RCKPOL_MASK BIT(0)
  133. #define TCKPOL_MASK BIT(0)
  134. #define SPICKM_MASK (BIT(1) | BIT(0))
  135. #define MSP_RX_CLKPOL_BIT(n) ((n & RCKPOL_MASK) << RCKPOL_SHIFT)
  136. #define MSP_TX_CLKPOL_BIT(n) ((n & TCKPOL_MASK) << TCKPOL_SHIFT)
  137. #define P1ELEN_SHIFT 0
  138. #define P1FLEN_SHIFT 3
  139. #define DTYP_SHIFT 10
  140. #define ENDN_SHIFT 12
  141. #define DDLY_SHIFT 13
  142. #define FSIG_SHIFT 15
  143. #define P2ELEN_SHIFT 16
  144. #define P2FLEN_SHIFT 19
  145. #define P2SM_SHIFT 26
  146. #define P2EN_SHIFT 27
  147. #define FSYNC_SHIFT 15
  148. #define P1ELEN_MASK 0x00000007
  149. #define P2ELEN_MASK 0x00070000
  150. #define P1FLEN_MASK 0x00000378
  151. #define P2FLEN_MASK 0x03780000
  152. #define DDLY_MASK 0x00003000
  153. #define DTYP_MASK 0x00000600
  154. #define P2SM_MASK 0x04000000
  155. #define P2EN_MASK 0x08000000
  156. #define ENDN_MASK 0x00001000
  157. #define TFSPOL_MASK 0x00000400
  158. #define TBSWAP_MASK 0x30000000
  159. #define COMPANDING_MODE_MASK 0x00000c00
  160. #define FSYNC_MASK 0x00008000
  161. #define MSP_P1_ELEM_LEN_BITS(n) (n & P1ELEN_MASK)
  162. #define MSP_P2_ELEM_LEN_BITS(n) (((n) << P2ELEN_SHIFT) & P2ELEN_MASK)
  163. #define MSP_P1_FRAME_LEN_BITS(n) (((n) << P1FLEN_SHIFT) & P1FLEN_MASK)
  164. #define MSP_P2_FRAME_LEN_BITS(n) (((n) << P2FLEN_SHIFT) & P2FLEN_MASK)
  165. #define MSP_DATA_DELAY_BITS(n) (((n) << DDLY_SHIFT) & DDLY_MASK)
  166. #define MSP_DATA_TYPE_BITS(n) (((n) << DTYP_SHIFT) & DTYP_MASK)
  167. #define MSP_P2_START_MODE_BIT(n) ((n << P2SM_SHIFT) & P2SM_MASK)
  168. #define MSP_P2_ENABLE_BIT(n) ((n << P2EN_SHIFT) & P2EN_MASK)
  169. #define MSP_SET_ENDIANNES_BIT(n) ((n << ENDN_SHIFT) & ENDN_MASK)
  170. #define MSP_FSYNC_POL(n) ((n << TFSPOL_SHIFT) & TFSPOL_MASK)
  171. #define MSP_DATA_WORD_SWAP(n) ((n << TBSWAP_SHIFT) & TBSWAP_MASK)
  172. #define MSP_SET_COMPANDING_MODE(n) ((n << DTYP_SHIFT) & \
  173. COMPANDING_MODE_MASK)
  174. #define MSP_SET_FSYNC_IGNORE(n) ((n << FSYNC_SHIFT) & FSYNC_MASK)
  175. /* Flag register */
  176. #define RX_BUSY BIT(0)
  177. #define RX_FIFO_EMPTY BIT(1)
  178. #define RX_FIFO_FULL BIT(2)
  179. #define TX_BUSY BIT(3)
  180. #define TX_FIFO_EMPTY BIT(4)
  181. #define TX_FIFO_FULL BIT(5)
  182. #define RBUSY_SHIFT 0
  183. #define RFE_SHIFT 1
  184. #define RFU_SHIFT 2
  185. #define TBUSY_SHIFT 3
  186. #define TFE_SHIFT 4
  187. #define TFU_SHIFT 5
  188. /* Multichannel control register */
  189. #define RMCEN_SHIFT 0
  190. #define RMCSF_SHIFT 1
  191. #define RCMPM_SHIFT 3
  192. #define TMCEN_SHIFT 5
  193. #define TNCSF_SHIFT 6
  194. /* Sample rate generator register */
  195. #define SCKDIV_SHIFT 0
  196. #define FRWID_SHIFT 10
  197. #define FRPER_SHIFT 16
  198. #define SCK_DIV_MASK 0x0000003FF
  199. #define FRAME_WIDTH_BITS(n) (((n) << FRWID_SHIFT) & 0x0000FC00)
  200. #define FRAME_PERIOD_BITS(n) (((n) << FRPER_SHIFT) & 0x1FFF0000)
  201. /* DMA controller register */
  202. #define RX_DMA_ENABLE BIT(0)
  203. #define TX_DMA_ENABLE BIT(1)
  204. #define RDMAE_SHIFT 0
  205. #define TDMAE_SHIFT 1
  206. /* Interrupt Register */
  207. #define RX_SERVICE_INT BIT(0)
  208. #define RX_OVERRUN_ERROR_INT BIT(1)
  209. #define RX_FSYNC_ERR_INT BIT(2)
  210. #define RX_FSYNC_INT BIT(3)
  211. #define TX_SERVICE_INT BIT(4)
  212. #define TX_UNDERRUN_ERR_INT BIT(5)
  213. #define TX_FSYNC_ERR_INT BIT(6)
  214. #define TX_FSYNC_INT BIT(7)
  215. #define ALL_INT 0x000000ff
  216. /* MSP test control register */
  217. #define MSP_ITCR_ITEN BIT(0)
  218. #define MSP_ITCR_TESTFIFO BIT(1)
  219. #define RMCEN_BIT 0
  220. #define RMCSF_BIT 1
  221. #define RCMPM_BIT 3
  222. #define TMCEN_BIT 5
  223. #define TNCSF_BIT 6
  224. /* Single or dual phase mode */
  225. enum msp_phase_mode {
  226. MSP_SINGLE_PHASE,
  227. MSP_DUAL_PHASE
  228. };
  229. /* Frame length */
  230. enum msp_frame_length {
  231. MSP_FRAME_LEN_1 = 0,
  232. MSP_FRAME_LEN_2 = 1,
  233. MSP_FRAME_LEN_4 = 3,
  234. MSP_FRAME_LEN_8 = 7,
  235. MSP_FRAME_LEN_12 = 11,
  236. MSP_FRAME_LEN_16 = 15,
  237. MSP_FRAME_LEN_20 = 19,
  238. MSP_FRAME_LEN_32 = 31,
  239. MSP_FRAME_LEN_48 = 47,
  240. MSP_FRAME_LEN_64 = 63
  241. };
  242. /* Element length */
  243. enum msp_elem_length {
  244. MSP_ELEM_LEN_8 = 0,
  245. MSP_ELEM_LEN_10 = 1,
  246. MSP_ELEM_LEN_12 = 2,
  247. MSP_ELEM_LEN_14 = 3,
  248. MSP_ELEM_LEN_16 = 4,
  249. MSP_ELEM_LEN_20 = 5,
  250. MSP_ELEM_LEN_24 = 6,
  251. MSP_ELEM_LEN_32 = 7
  252. };
  253. enum msp_data_xfer_width {
  254. MSP_DATA_TRANSFER_WIDTH_BYTE,
  255. MSP_DATA_TRANSFER_WIDTH_HALFWORD,
  256. MSP_DATA_TRANSFER_WIDTH_WORD
  257. };
  258. enum msp_frame_sync {
  259. MSP_FSYNC_UNIGNORE = 0,
  260. MSP_FSYNC_IGNORE = 1,
  261. };
  262. enum msp_phase2_start_mode {
  263. MSP_PHASE2_START_MODE_IMEDIATE,
  264. MSP_PHASE2_START_MODE_FSYNC
  265. };
  266. enum msp_btf {
  267. MSP_BTF_MS_BIT_FIRST = 0,
  268. MSP_BTF_LS_BIT_FIRST = 1
  269. };
  270. enum msp_fsync_pol {
  271. MSP_FSYNC_POL_ACT_HI = 0,
  272. MSP_FSYNC_POL_ACT_LO = 1
  273. };
  274. /* Data delay (in bit clock cycles) */
  275. enum msp_delay {
  276. MSP_DELAY_0 = 0,
  277. MSP_DELAY_1 = 1,
  278. MSP_DELAY_2 = 2,
  279. MSP_DELAY_3 = 3
  280. };
  281. /* Configurations of clocks (transmit, receive or sample rate generator) */
  282. enum msp_edge {
  283. MSP_FALLING_EDGE = 0,
  284. MSP_RISING_EDGE = 1,
  285. };
  286. enum msp_hws {
  287. MSP_SWAP_NONE = 0,
  288. MSP_SWAP_BYTE_PER_WORD = 1,
  289. MSP_SWAP_BYTE_PER_HALF_WORD = 2,
  290. MSP_SWAP_HALF_WORD_PER_WORD = 3
  291. };
  292. enum msp_compress_mode {
  293. MSP_COMPRESS_MODE_LINEAR = 0,
  294. MSP_COMPRESS_MODE_MU_LAW = 2,
  295. MSP_COMPRESS_MODE_A_LAW = 3
  296. };
  297. enum msp_expand_mode {
  298. MSP_EXPAND_MODE_LINEAR = 0,
  299. MSP_EXPAND_MODE_LINEAR_SIGNED = 1,
  300. MSP_EXPAND_MODE_MU_LAW = 2,
  301. MSP_EXPAND_MODE_A_LAW = 3
  302. };
  303. #define MSP_FRAME_PERIOD_IN_MONO_MODE 256
  304. #define MSP_FRAME_PERIOD_IN_STEREO_MODE 32
  305. #define MSP_FRAME_WIDTH_IN_STEREO_MODE 16
  306. enum msp_protocol {
  307. MSP_I2S_PROTOCOL,
  308. MSP_PCM_PROTOCOL,
  309. MSP_PCM_COMPAND_PROTOCOL,
  310. MSP_INVALID_PROTOCOL
  311. };
  312. /*
  313. * No of registers to backup during
  314. * suspend resume
  315. */
  316. #define MAX_MSP_BACKUP_REGS 36
  317. enum i2s_direction_t {
  318. MSP_DIR_TX = 0x01,
  319. MSP_DIR_RX = 0x02,
  320. };
  321. enum msp_data_size {
  322. MSP_DATA_BITS_DEFAULT = -1,
  323. MSP_DATA_BITS_8 = 0x00,
  324. MSP_DATA_BITS_10,
  325. MSP_DATA_BITS_12,
  326. MSP_DATA_BITS_14,
  327. MSP_DATA_BITS_16,
  328. MSP_DATA_BITS_20,
  329. MSP_DATA_BITS_24,
  330. MSP_DATA_BITS_32,
  331. };
  332. enum msp_state {
  333. MSP_STATE_IDLE = 0,
  334. MSP_STATE_CONFIGURED = 1,
  335. MSP_STATE_RUNNING = 2,
  336. };
  337. enum msp_rx_comparison_enable_mode {
  338. MSP_COMPARISON_DISABLED = 0,
  339. MSP_COMPARISON_NONEQUAL_ENABLED = 2,
  340. MSP_COMPARISON_EQUAL_ENABLED = 3
  341. };
  342. struct msp_multichannel_config {
  343. bool rx_multichannel_enable;
  344. bool tx_multichannel_enable;
  345. enum msp_rx_comparison_enable_mode rx_comparison_enable_mode;
  346. u8 padding;
  347. u32 comparison_value;
  348. u32 comparison_mask;
  349. u32 rx_channel_0_enable;
  350. u32 rx_channel_1_enable;
  351. u32 rx_channel_2_enable;
  352. u32 rx_channel_3_enable;
  353. u32 tx_channel_0_enable;
  354. u32 tx_channel_1_enable;
  355. u32 tx_channel_2_enable;
  356. u32 tx_channel_3_enable;
  357. };
  358. struct msp_protdesc {
  359. u32 rx_phase_mode;
  360. u32 tx_phase_mode;
  361. u32 rx_phase2_start_mode;
  362. u32 tx_phase2_start_mode;
  363. u32 rx_byte_order;
  364. u32 tx_byte_order;
  365. u32 rx_frame_len_1;
  366. u32 rx_frame_len_2;
  367. u32 tx_frame_len_1;
  368. u32 tx_frame_len_2;
  369. u32 rx_elem_len_1;
  370. u32 rx_elem_len_2;
  371. u32 tx_elem_len_1;
  372. u32 tx_elem_len_2;
  373. u32 rx_data_delay;
  374. u32 tx_data_delay;
  375. u32 rx_clk_pol;
  376. u32 tx_clk_pol;
  377. u32 rx_fsync_pol;
  378. u32 tx_fsync_pol;
  379. u32 rx_half_word_swap;
  380. u32 tx_half_word_swap;
  381. u32 compression_mode;
  382. u32 expansion_mode;
  383. u32 frame_sync_ignore;
  384. u32 frame_period;
  385. u32 frame_width;
  386. u32 clocks_per_frame;
  387. };
  388. struct ux500_msp_config {
  389. unsigned int f_inputclk;
  390. unsigned int rx_clk_sel;
  391. unsigned int tx_clk_sel;
  392. unsigned int srg_clk_sel;
  393. unsigned int rx_fsync_pol;
  394. unsigned int tx_fsync_pol;
  395. unsigned int rx_fsync_sel;
  396. unsigned int tx_fsync_sel;
  397. unsigned int rx_fifo_config;
  398. unsigned int tx_fifo_config;
  399. unsigned int loopback_enable;
  400. unsigned int tx_data_enable;
  401. unsigned int default_protdesc;
  402. struct msp_protdesc protdesc;
  403. int multichannel_configured;
  404. struct msp_multichannel_config multichannel_config;
  405. unsigned int direction;
  406. unsigned int protocol;
  407. unsigned int frame_freq;
  408. enum msp_data_size data_size;
  409. unsigned int def_elem_len;
  410. unsigned int iodelay;
  411. };
  412. struct ux500_msp_dma_params {
  413. unsigned int data_size;
  414. dma_addr_t tx_rx_addr;
  415. struct stedma40_chan_cfg *dma_cfg;
  416. };
  417. struct ux500_msp {
  418. int id;
  419. void __iomem *registers;
  420. struct device *dev;
  421. struct ux500_msp_dma_params playback_dma_data;
  422. struct ux500_msp_dma_params capture_dma_data;
  423. enum msp_state msp_state;
  424. int def_elem_len;
  425. unsigned int dir_busy;
  426. int loopback_enable;
  427. unsigned int f_bitclk;
  428. };
  429. struct msp_i2s_platform_data;
  430. int ux500_msp_i2s_init_msp(struct platform_device *pdev,
  431. struct ux500_msp **msp_p,
  432. struct msp_i2s_platform_data *platform_data);
  433. void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
  434. struct ux500_msp *msp);
  435. int ux500_msp_i2s_open(struct ux500_msp *msp, struct ux500_msp_config *config);
  436. int ux500_msp_i2s_close(struct ux500_msp *msp,
  437. unsigned int dir);
  438. int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd,
  439. int direction);
  440. #endif