ux500_msp_i2s.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2012
  4. *
  5. * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
  6. * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
  7. * Sandeep Kaushik <sandeep.kaushik@st.com>
  8. * for ST-Ericsson.
  9. *
  10. * License terms:
  11. */
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/delay.h>
  15. #include <linux/slab.h>
  16. #include <linux/io.h>
  17. #include <linux/of.h>
  18. #include <linux/platform_data/asoc-ux500-msp.h>
  19. #include <sound/soc.h>
  20. #include "ux500_msp_i2s.h"
  21. /* Protocol desciptors */
  22. static const struct msp_protdesc prot_descs[] = {
  23. { /* I2S */
  24. MSP_SINGLE_PHASE,
  25. MSP_SINGLE_PHASE,
  26. MSP_PHASE2_START_MODE_IMEDIATE,
  27. MSP_PHASE2_START_MODE_IMEDIATE,
  28. MSP_BTF_MS_BIT_FIRST,
  29. MSP_BTF_MS_BIT_FIRST,
  30. MSP_FRAME_LEN_1,
  31. MSP_FRAME_LEN_1,
  32. MSP_FRAME_LEN_1,
  33. MSP_FRAME_LEN_1,
  34. MSP_ELEM_LEN_32,
  35. MSP_ELEM_LEN_32,
  36. MSP_ELEM_LEN_32,
  37. MSP_ELEM_LEN_32,
  38. MSP_DELAY_1,
  39. MSP_DELAY_1,
  40. MSP_RISING_EDGE,
  41. MSP_FALLING_EDGE,
  42. MSP_FSYNC_POL_ACT_LO,
  43. MSP_FSYNC_POL_ACT_LO,
  44. MSP_SWAP_NONE,
  45. MSP_SWAP_NONE,
  46. MSP_COMPRESS_MODE_LINEAR,
  47. MSP_EXPAND_MODE_LINEAR,
  48. MSP_FSYNC_IGNORE,
  49. 31,
  50. 15,
  51. 32,
  52. }, { /* PCM */
  53. MSP_DUAL_PHASE,
  54. MSP_DUAL_PHASE,
  55. MSP_PHASE2_START_MODE_FSYNC,
  56. MSP_PHASE2_START_MODE_FSYNC,
  57. MSP_BTF_MS_BIT_FIRST,
  58. MSP_BTF_MS_BIT_FIRST,
  59. MSP_FRAME_LEN_1,
  60. MSP_FRAME_LEN_1,
  61. MSP_FRAME_LEN_1,
  62. MSP_FRAME_LEN_1,
  63. MSP_ELEM_LEN_16,
  64. MSP_ELEM_LEN_16,
  65. MSP_ELEM_LEN_16,
  66. MSP_ELEM_LEN_16,
  67. MSP_DELAY_0,
  68. MSP_DELAY_0,
  69. MSP_RISING_EDGE,
  70. MSP_FALLING_EDGE,
  71. MSP_FSYNC_POL_ACT_HI,
  72. MSP_FSYNC_POL_ACT_HI,
  73. MSP_SWAP_NONE,
  74. MSP_SWAP_NONE,
  75. MSP_COMPRESS_MODE_LINEAR,
  76. MSP_EXPAND_MODE_LINEAR,
  77. MSP_FSYNC_IGNORE,
  78. 255,
  79. 0,
  80. 256,
  81. }, { /* Companded PCM */
  82. MSP_SINGLE_PHASE,
  83. MSP_SINGLE_PHASE,
  84. MSP_PHASE2_START_MODE_FSYNC,
  85. MSP_PHASE2_START_MODE_FSYNC,
  86. MSP_BTF_MS_BIT_FIRST,
  87. MSP_BTF_MS_BIT_FIRST,
  88. MSP_FRAME_LEN_1,
  89. MSP_FRAME_LEN_1,
  90. MSP_FRAME_LEN_1,
  91. MSP_FRAME_LEN_1,
  92. MSP_ELEM_LEN_8,
  93. MSP_ELEM_LEN_8,
  94. MSP_ELEM_LEN_8,
  95. MSP_ELEM_LEN_8,
  96. MSP_DELAY_0,
  97. MSP_DELAY_0,
  98. MSP_RISING_EDGE,
  99. MSP_RISING_EDGE,
  100. MSP_FSYNC_POL_ACT_HI,
  101. MSP_FSYNC_POL_ACT_HI,
  102. MSP_SWAP_NONE,
  103. MSP_SWAP_NONE,
  104. MSP_COMPRESS_MODE_LINEAR,
  105. MSP_EXPAND_MODE_LINEAR,
  106. MSP_FSYNC_IGNORE,
  107. 255,
  108. 0,
  109. 256,
  110. },
  111. };
  112. static void set_prot_desc_tx(struct ux500_msp *msp,
  113. struct msp_protdesc *protdesc,
  114. enum msp_data_size data_size)
  115. {
  116. u32 temp_reg = 0;
  117. temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);
  118. temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);
  119. temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);
  120. temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);
  121. if (msp->def_elem_len) {
  122. temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);
  123. temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);
  124. } else {
  125. temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
  126. temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
  127. }
  128. temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);
  129. temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);
  130. temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);
  131. temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);
  132. temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);
  133. temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
  134. writel(temp_reg, msp->registers + MSP_TCF);
  135. }
  136. static void set_prot_desc_rx(struct ux500_msp *msp,
  137. struct msp_protdesc *protdesc,
  138. enum msp_data_size data_size)
  139. {
  140. u32 temp_reg = 0;
  141. temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);
  142. temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);
  143. temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);
  144. temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);
  145. if (msp->def_elem_len) {
  146. temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);
  147. temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);
  148. } else {
  149. temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
  150. temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
  151. }
  152. temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);
  153. temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);
  154. temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);
  155. temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);
  156. temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);
  157. temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
  158. writel(temp_reg, msp->registers + MSP_RCF);
  159. }
  160. static int configure_protocol(struct ux500_msp *msp,
  161. struct ux500_msp_config *config)
  162. {
  163. struct msp_protdesc *protdesc;
  164. enum msp_data_size data_size;
  165. u32 temp_reg = 0;
  166. data_size = config->data_size;
  167. msp->def_elem_len = config->def_elem_len;
  168. if (config->default_protdesc == 1) {
  169. if (config->protocol >= MSP_INVALID_PROTOCOL) {
  170. dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
  171. __func__);
  172. return -EINVAL;
  173. }
  174. protdesc =
  175. (struct msp_protdesc *)&prot_descs[config->protocol];
  176. } else {
  177. protdesc = (struct msp_protdesc *)&config->protdesc;
  178. }
  179. if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) {
  180. dev_err(msp->dev,
  181. "%s: ERROR: Invalid data-size requested (data_size = %d)!\n",
  182. __func__, data_size);
  183. return -EINVAL;
  184. }
  185. if (config->direction & MSP_DIR_TX)
  186. set_prot_desc_tx(msp, protdesc, data_size);
  187. if (config->direction & MSP_DIR_RX)
  188. set_prot_desc_rx(msp, protdesc, data_size);
  189. /* The code below should not be separated. */
  190. temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
  191. temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);
  192. writel(temp_reg, msp->registers + MSP_GCR);
  193. temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
  194. temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);
  195. writel(temp_reg, msp->registers + MSP_GCR);
  196. return 0;
  197. }
  198. static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
  199. {
  200. u32 reg_val_GCR;
  201. u32 frame_per = 0;
  202. u32 sck_div = 0;
  203. u32 frame_width = 0;
  204. u32 temp_reg = 0;
  205. struct msp_protdesc *protdesc = NULL;
  206. reg_val_GCR = readl(msp->registers + MSP_GCR);
  207. writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
  208. if (config->default_protdesc)
  209. protdesc =
  210. (struct msp_protdesc *)&prot_descs[config->protocol];
  211. else
  212. protdesc = (struct msp_protdesc *)&config->protdesc;
  213. switch (config->protocol) {
  214. case MSP_PCM_PROTOCOL:
  215. case MSP_PCM_COMPAND_PROTOCOL:
  216. frame_width = protdesc->frame_width;
  217. sck_div = config->f_inputclk / (config->frame_freq *
  218. (protdesc->clocks_per_frame));
  219. frame_per = protdesc->frame_period;
  220. break;
  221. case MSP_I2S_PROTOCOL:
  222. frame_width = protdesc->frame_width;
  223. sck_div = config->f_inputclk / (config->frame_freq *
  224. (protdesc->clocks_per_frame));
  225. frame_per = protdesc->frame_period;
  226. break;
  227. default:
  228. dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
  229. __func__,
  230. config->protocol);
  231. return -EINVAL;
  232. }
  233. temp_reg = (sck_div - 1) & SCK_DIV_MASK;
  234. temp_reg |= FRAME_WIDTH_BITS(frame_width);
  235. temp_reg |= FRAME_PERIOD_BITS(frame_per);
  236. writel(temp_reg, msp->registers + MSP_SRG);
  237. msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
  238. /* Enable bit-clock */
  239. udelay(100);
  240. reg_val_GCR = readl(msp->registers + MSP_GCR);
  241. writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
  242. udelay(100);
  243. return 0;
  244. }
  245. static int configure_multichannel(struct ux500_msp *msp,
  246. struct ux500_msp_config *config)
  247. {
  248. struct msp_protdesc *protdesc;
  249. struct msp_multichannel_config *mcfg;
  250. u32 reg_val_MCR;
  251. if (config->default_protdesc == 1) {
  252. if (config->protocol >= MSP_INVALID_PROTOCOL) {
  253. dev_err(msp->dev,
  254. "%s: ERROR: Invalid protocol (%d)!\n",
  255. __func__, config->protocol);
  256. return -EINVAL;
  257. }
  258. protdesc = (struct msp_protdesc *)
  259. &prot_descs[config->protocol];
  260. } else {
  261. protdesc = (struct msp_protdesc *)&config->protdesc;
  262. }
  263. mcfg = &config->multichannel_config;
  264. if (mcfg->tx_multichannel_enable) {
  265. if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) {
  266. reg_val_MCR = readl(msp->registers + MSP_MCR);
  267. writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
  268. 1 << TMCEN_BIT : 0),
  269. msp->registers + MSP_MCR);
  270. writel(mcfg->tx_channel_0_enable,
  271. msp->registers + MSP_TCE0);
  272. writel(mcfg->tx_channel_1_enable,
  273. msp->registers + MSP_TCE1);
  274. writel(mcfg->tx_channel_2_enable,
  275. msp->registers + MSP_TCE2);
  276. writel(mcfg->tx_channel_3_enable,
  277. msp->registers + MSP_TCE3);
  278. } else {
  279. dev_err(msp->dev,
  280. "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n",
  281. __func__, protdesc->tx_phase_mode);
  282. return -EINVAL;
  283. }
  284. }
  285. if (mcfg->rx_multichannel_enable) {
  286. if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) {
  287. reg_val_MCR = readl(msp->registers + MSP_MCR);
  288. writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
  289. 1 << RMCEN_BIT : 0),
  290. msp->registers + MSP_MCR);
  291. writel(mcfg->rx_channel_0_enable,
  292. msp->registers + MSP_RCE0);
  293. writel(mcfg->rx_channel_1_enable,
  294. msp->registers + MSP_RCE1);
  295. writel(mcfg->rx_channel_2_enable,
  296. msp->registers + MSP_RCE2);
  297. writel(mcfg->rx_channel_3_enable,
  298. msp->registers + MSP_RCE3);
  299. } else {
  300. dev_err(msp->dev,
  301. "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n",
  302. __func__, protdesc->rx_phase_mode);
  303. return -EINVAL;
  304. }
  305. if (mcfg->rx_comparison_enable_mode) {
  306. reg_val_MCR = readl(msp->registers + MSP_MCR);
  307. writel(reg_val_MCR |
  308. (mcfg->rx_comparison_enable_mode << RCMPM_BIT),
  309. msp->registers + MSP_MCR);
  310. writel(mcfg->comparison_mask,
  311. msp->registers + MSP_RCM);
  312. writel(mcfg->comparison_value,
  313. msp->registers + MSP_RCV);
  314. }
  315. }
  316. return 0;
  317. }
  318. static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
  319. {
  320. int status = 0;
  321. u32 reg_val_DMACR, reg_val_GCR;
  322. /* Configure msp with protocol dependent settings */
  323. configure_protocol(msp, config);
  324. setup_bitclk(msp, config);
  325. if (config->multichannel_configured == 1) {
  326. status = configure_multichannel(msp, config);
  327. if (status)
  328. dev_warn(msp->dev,
  329. "%s: WARN: configure_multichannel failed (%d)!\n",
  330. __func__, status);
  331. }
  332. /* Make sure the correct DMA-directions are configured */
  333. if ((config->direction & MSP_DIR_RX) &&
  334. !msp->capture_dma_data.dma_cfg) {
  335. dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
  336. __func__);
  337. return -EINVAL;
  338. }
  339. if ((config->direction == MSP_DIR_TX) &&
  340. !msp->playback_dma_data.dma_cfg) {
  341. dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
  342. __func__);
  343. return -EINVAL;
  344. }
  345. reg_val_DMACR = readl(msp->registers + MSP_DMACR);
  346. if (config->direction & MSP_DIR_RX)
  347. reg_val_DMACR |= RX_DMA_ENABLE;
  348. if (config->direction & MSP_DIR_TX)
  349. reg_val_DMACR |= TX_DMA_ENABLE;
  350. writel(reg_val_DMACR, msp->registers + MSP_DMACR);
  351. writel(config->iodelay, msp->registers + MSP_IODLY);
  352. /* Enable frame generation logic */
  353. reg_val_GCR = readl(msp->registers + MSP_GCR);
  354. writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
  355. return status;
  356. }
  357. static void flush_fifo_rx(struct ux500_msp *msp)
  358. {
  359. u32 reg_val_GCR, reg_val_FLR;
  360. u32 limit = 32;
  361. reg_val_GCR = readl(msp->registers + MSP_GCR);
  362. writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
  363. reg_val_FLR = readl(msp->registers + MSP_FLR);
  364. while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
  365. readl(msp->registers + MSP_DR);
  366. reg_val_FLR = readl(msp->registers + MSP_FLR);
  367. }
  368. writel(reg_val_GCR, msp->registers + MSP_GCR);
  369. }
  370. static void flush_fifo_tx(struct ux500_msp *msp)
  371. {
  372. u32 reg_val_GCR, reg_val_FLR;
  373. u32 limit = 32;
  374. reg_val_GCR = readl(msp->registers + MSP_GCR);
  375. writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
  376. writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
  377. reg_val_FLR = readl(msp->registers + MSP_FLR);
  378. while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
  379. readl(msp->registers + MSP_TSTDR);
  380. reg_val_FLR = readl(msp->registers + MSP_FLR);
  381. }
  382. writel(0x0, msp->registers + MSP_ITCR);
  383. writel(reg_val_GCR, msp->registers + MSP_GCR);
  384. }
  385. int ux500_msp_i2s_open(struct ux500_msp *msp,
  386. struct ux500_msp_config *config)
  387. {
  388. u32 old_reg, new_reg, mask;
  389. int res;
  390. unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
  391. if (in_interrupt()) {
  392. dev_err(msp->dev,
  393. "%s: ERROR: Open called in interrupt context!\n",
  394. __func__);
  395. return -1;
  396. }
  397. tx_sel = (config->direction & MSP_DIR_TX) > 0;
  398. rx_sel = (config->direction & MSP_DIR_RX) > 0;
  399. if (!tx_sel && !rx_sel) {
  400. dev_err(msp->dev, "%s: Error: No direction selected!\n",
  401. __func__);
  402. return -EINVAL;
  403. }
  404. tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
  405. rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
  406. if (tx_busy && tx_sel) {
  407. dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
  408. return -EBUSY;
  409. }
  410. if (rx_busy && rx_sel) {
  411. dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
  412. return -EBUSY;
  413. }
  414. msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
  415. /* First do the global config register */
  416. mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
  417. TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
  418. RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
  419. LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
  420. new_reg = (config->tx_clk_sel | config->rx_clk_sel |
  421. config->rx_fsync_pol | config->tx_fsync_pol |
  422. config->rx_fsync_sel | config->tx_fsync_sel |
  423. config->rx_fifo_config | config->tx_fifo_config |
  424. config->srg_clk_sel | config->loopback_enable |
  425. config->tx_data_enable);
  426. old_reg = readl(msp->registers + MSP_GCR);
  427. old_reg &= ~mask;
  428. new_reg |= old_reg;
  429. writel(new_reg, msp->registers + MSP_GCR);
  430. res = enable_msp(msp, config);
  431. if (res < 0) {
  432. dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
  433. __func__, res);
  434. return -EBUSY;
  435. }
  436. if (config->loopback_enable & 0x80)
  437. msp->loopback_enable = 1;
  438. /* Flush FIFOs */
  439. flush_fifo_tx(msp);
  440. flush_fifo_rx(msp);
  441. msp->msp_state = MSP_STATE_CONFIGURED;
  442. return 0;
  443. }
  444. static void disable_msp_rx(struct ux500_msp *msp)
  445. {
  446. u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
  447. reg_val_GCR = readl(msp->registers + MSP_GCR);
  448. writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
  449. reg_val_DMACR = readl(msp->registers + MSP_DMACR);
  450. writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
  451. reg_val_IMSC = readl(msp->registers + MSP_IMSC);
  452. writel(reg_val_IMSC &
  453. ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
  454. msp->registers + MSP_IMSC);
  455. msp->dir_busy &= ~MSP_DIR_RX;
  456. }
  457. static void disable_msp_tx(struct ux500_msp *msp)
  458. {
  459. u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
  460. reg_val_GCR = readl(msp->registers + MSP_GCR);
  461. writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
  462. reg_val_DMACR = readl(msp->registers + MSP_DMACR);
  463. writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
  464. reg_val_IMSC = readl(msp->registers + MSP_IMSC);
  465. writel(reg_val_IMSC &
  466. ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
  467. msp->registers + MSP_IMSC);
  468. msp->dir_busy &= ~MSP_DIR_TX;
  469. }
  470. static int disable_msp(struct ux500_msp *msp, unsigned int dir)
  471. {
  472. u32 reg_val_GCR;
  473. unsigned int disable_tx, disable_rx;
  474. reg_val_GCR = readl(msp->registers + MSP_GCR);
  475. disable_tx = dir & MSP_DIR_TX;
  476. disable_rx = dir & MSP_DIR_TX;
  477. if (disable_tx && disable_rx) {
  478. reg_val_GCR = readl(msp->registers + MSP_GCR);
  479. writel(reg_val_GCR | LOOPBACK_MASK,
  480. msp->registers + MSP_GCR);
  481. /* Flush TX-FIFO */
  482. flush_fifo_tx(msp);
  483. /* Disable TX-channel */
  484. writel((readl(msp->registers + MSP_GCR) &
  485. (~TX_ENABLE)), msp->registers + MSP_GCR);
  486. /* Flush RX-FIFO */
  487. flush_fifo_rx(msp);
  488. /* Disable Loopback and Receive channel */
  489. writel((readl(msp->registers + MSP_GCR) &
  490. (~(RX_ENABLE | LOOPBACK_MASK))),
  491. msp->registers + MSP_GCR);
  492. disable_msp_tx(msp);
  493. disable_msp_rx(msp);
  494. } else if (disable_tx)
  495. disable_msp_tx(msp);
  496. else if (disable_rx)
  497. disable_msp_rx(msp);
  498. return 0;
  499. }
  500. int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
  501. {
  502. u32 reg_val_GCR, enable_bit;
  503. if (msp->msp_state == MSP_STATE_IDLE) {
  504. dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
  505. __func__);
  506. return -EINVAL;
  507. }
  508. switch (cmd) {
  509. case SNDRV_PCM_TRIGGER_START:
  510. case SNDRV_PCM_TRIGGER_RESUME:
  511. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  512. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  513. enable_bit = TX_ENABLE;
  514. else
  515. enable_bit = RX_ENABLE;
  516. reg_val_GCR = readl(msp->registers + MSP_GCR);
  517. writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
  518. break;
  519. case SNDRV_PCM_TRIGGER_STOP:
  520. case SNDRV_PCM_TRIGGER_SUSPEND:
  521. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  522. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  523. disable_msp_tx(msp);
  524. else
  525. disable_msp_rx(msp);
  526. break;
  527. default:
  528. return -EINVAL;
  529. }
  530. return 0;
  531. }
  532. int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
  533. {
  534. int status = 0;
  535. dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
  536. status = disable_msp(msp, dir);
  537. if (msp->dir_busy == 0) {
  538. /* disable sample rate and frame generators */
  539. msp->msp_state = MSP_STATE_IDLE;
  540. writel((readl(msp->registers + MSP_GCR) &
  541. (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
  542. msp->registers + MSP_GCR);
  543. writel(0, msp->registers + MSP_GCR);
  544. writel(0, msp->registers + MSP_TCF);
  545. writel(0, msp->registers + MSP_RCF);
  546. writel(0, msp->registers + MSP_DMACR);
  547. writel(0, msp->registers + MSP_SRG);
  548. writel(0, msp->registers + MSP_MCR);
  549. writel(0, msp->registers + MSP_RCM);
  550. writel(0, msp->registers + MSP_RCV);
  551. writel(0, msp->registers + MSP_TCE0);
  552. writel(0, msp->registers + MSP_TCE1);
  553. writel(0, msp->registers + MSP_TCE2);
  554. writel(0, msp->registers + MSP_TCE3);
  555. writel(0, msp->registers + MSP_RCE0);
  556. writel(0, msp->registers + MSP_RCE1);
  557. writel(0, msp->registers + MSP_RCE2);
  558. writel(0, msp->registers + MSP_RCE3);
  559. }
  560. return status;
  561. }
  562. static int ux500_msp_i2s_of_init_msp(struct platform_device *pdev,
  563. struct ux500_msp *msp,
  564. struct msp_i2s_platform_data **platform_data)
  565. {
  566. struct msp_i2s_platform_data *pdata;
  567. *platform_data = devm_kzalloc(&pdev->dev,
  568. sizeof(struct msp_i2s_platform_data),
  569. GFP_KERNEL);
  570. pdata = *platform_data;
  571. if (!pdata)
  572. return -ENOMEM;
  573. msp->playback_dma_data.dma_cfg = devm_kzalloc(&pdev->dev,
  574. sizeof(struct stedma40_chan_cfg),
  575. GFP_KERNEL);
  576. if (!msp->playback_dma_data.dma_cfg)
  577. return -ENOMEM;
  578. msp->capture_dma_data.dma_cfg = devm_kzalloc(&pdev->dev,
  579. sizeof(struct stedma40_chan_cfg),
  580. GFP_KERNEL);
  581. if (!msp->capture_dma_data.dma_cfg)
  582. return -ENOMEM;
  583. return 0;
  584. }
  585. int ux500_msp_i2s_init_msp(struct platform_device *pdev,
  586. struct ux500_msp **msp_p,
  587. struct msp_i2s_platform_data *platform_data)
  588. {
  589. struct resource *res = NULL;
  590. struct device_node *np = pdev->dev.of_node;
  591. struct ux500_msp *msp;
  592. int ret;
  593. *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
  594. msp = *msp_p;
  595. if (!msp)
  596. return -ENOMEM;
  597. if (!platform_data) {
  598. if (np) {
  599. ret = ux500_msp_i2s_of_init_msp(pdev, msp,
  600. &platform_data);
  601. if (ret)
  602. return ret;
  603. } else
  604. return -EINVAL;
  605. } else {
  606. msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx;
  607. msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx;
  608. msp->id = platform_data->id;
  609. }
  610. msp->dev = &pdev->dev;
  611. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  612. if (res == NULL) {
  613. dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n",
  614. __func__);
  615. return -ENOMEM;
  616. }
  617. msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR;
  618. msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR;
  619. msp->registers = devm_ioremap(&pdev->dev, res->start,
  620. resource_size(res));
  621. if (msp->registers == NULL) {
  622. dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__);
  623. return -ENOMEM;
  624. }
  625. msp->msp_state = MSP_STATE_IDLE;
  626. msp->loopback_enable = 0;
  627. return 0;
  628. }
  629. void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
  630. struct ux500_msp *msp)
  631. {
  632. dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);
  633. }
  634. MODULE_LICENSE("GPL v2");