omap-mcpdm.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
  4. *
  5. * Copyright (C) 2009 - 2011 Texas Instruments
  6. *
  7. * Author: Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
  9. * Margarita Olaya <magi.olaya@ti.com>
  10. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/slab.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/of_device.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/dmaengine_pcm.h>
  27. #include "omap-mcpdm.h"
  28. #include "sdma-pcm.h"
  29. struct mcpdm_link_config {
  30. u32 link_mask; /* channel mask for the direction */
  31. u32 threshold; /* FIFO threshold */
  32. };
  33. struct omap_mcpdm {
  34. struct device *dev;
  35. unsigned long phys_base;
  36. void __iomem *io_base;
  37. int irq;
  38. struct pm_qos_request pm_qos_req;
  39. int latency[2];
  40. struct mutex mutex;
  41. /* Playback/Capture configuration */
  42. struct mcpdm_link_config config[2];
  43. /* McPDM dn offsets for rx1, and 2 channels */
  44. u32 dn_rx_offset;
  45. /* McPDM needs to be restarted due to runtime reconfiguration */
  46. bool restart;
  47. /* pm state for suspend/resume handling */
  48. int pm_active_count;
  49. struct snd_dmaengine_dai_dma_data dma_data[2];
  50. };
  51. /*
  52. * Stream DMA parameters
  53. */
  54. static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  55. {
  56. writel_relaxed(val, mcpdm->io_base + reg);
  57. }
  58. static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  59. {
  60. return readl_relaxed(mcpdm->io_base + reg);
  61. }
  62. #ifdef DEBUG
  63. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  64. {
  65. dev_dbg(mcpdm->dev, "***********************\n");
  66. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  67. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  68. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  69. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  70. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  71. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  72. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  73. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
  74. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  75. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
  76. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  77. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
  78. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  79. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
  80. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  81. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
  82. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  83. omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
  84. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  85. omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
  86. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  87. omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
  88. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  89. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
  90. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  91. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
  92. dev_dbg(mcpdm->dev, "***********************\n");
  93. }
  94. #else
  95. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
  96. #endif
  97. /*
  98. * Enables the transfer through the PDM interface to/from the Phoenix
  99. * codec by enabling the corresponding UP or DN channels.
  100. */
  101. static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
  102. {
  103. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  104. u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
  105. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  106. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  107. ctrl |= link_mask;
  108. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  109. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  110. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  111. }
  112. /*
  113. * Disables the transfer through the PDM interface to/from the Phoenix
  114. * codec by disabling the corresponding UP or DN channels.
  115. */
  116. static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
  117. {
  118. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  119. u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
  120. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  121. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  122. ctrl &= ~(link_mask);
  123. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  124. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  125. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  126. }
  127. /*
  128. * Is the physical McPDM interface active.
  129. */
  130. static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
  131. {
  132. return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
  133. (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
  134. }
  135. /*
  136. * Configures McPDM uplink, and downlink for audio.
  137. * This function should be called before omap_mcpdm_start.
  138. */
  139. static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
  140. {
  141. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  142. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
  143. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
  144. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
  145. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  146. /* Enable DN RX1/2 offset cancellation feature, if configured */
  147. if (mcpdm->dn_rx_offset) {
  148. u32 dn_offset = mcpdm->dn_rx_offset;
  149. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  150. dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
  151. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  152. }
  153. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
  154. mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
  155. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
  156. mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
  157. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
  158. MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
  159. }
  160. /*
  161. * Cleans McPDM uplink, and downlink configuration.
  162. * This function should be called when the stream is closed.
  163. */
  164. static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
  165. {
  166. /* Disable irq request generation for downlink */
  167. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  168. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
  169. /* Disable DMA request generation for downlink */
  170. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
  171. /* Disable irq request generation for uplink */
  172. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  173. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  174. /* Disable DMA request generation for uplink */
  175. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
  176. /* Disable RX1/2 offset cancellation */
  177. if (mcpdm->dn_rx_offset)
  178. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
  179. }
  180. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  181. {
  182. struct omap_mcpdm *mcpdm = dev_id;
  183. int irq_status;
  184. irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
  185. /* Acknowledge irq event */
  186. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
  187. if (irq_status & MCPDM_DN_IRQ_FULL)
  188. dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
  189. if (irq_status & MCPDM_DN_IRQ_EMPTY)
  190. dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
  191. if (irq_status & MCPDM_DN_IRQ)
  192. dev_dbg(mcpdm->dev, "DN (playback) write request\n");
  193. if (irq_status & MCPDM_UP_IRQ_FULL)
  194. dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
  195. if (irq_status & MCPDM_UP_IRQ_EMPTY)
  196. dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
  197. if (irq_status & MCPDM_UP_IRQ)
  198. dev_dbg(mcpdm->dev, "UP (capture) write request\n");
  199. return IRQ_HANDLED;
  200. }
  201. static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
  202. struct snd_soc_dai *dai)
  203. {
  204. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  205. mutex_lock(&mcpdm->mutex);
  206. if (!snd_soc_dai_active(dai))
  207. omap_mcpdm_open_streams(mcpdm);
  208. mutex_unlock(&mcpdm->mutex);
  209. return 0;
  210. }
  211. static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
  212. struct snd_soc_dai *dai)
  213. {
  214. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  215. int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  216. int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
  217. int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
  218. mutex_lock(&mcpdm->mutex);
  219. if (!snd_soc_dai_active(dai)) {
  220. if (omap_mcpdm_active(mcpdm)) {
  221. omap_mcpdm_stop(mcpdm);
  222. omap_mcpdm_close_streams(mcpdm);
  223. mcpdm->config[0].link_mask = 0;
  224. mcpdm->config[1].link_mask = 0;
  225. }
  226. }
  227. if (mcpdm->latency[stream2])
  228. cpu_latency_qos_update_request(&mcpdm->pm_qos_req,
  229. mcpdm->latency[stream2]);
  230. else if (mcpdm->latency[stream1])
  231. cpu_latency_qos_remove_request(&mcpdm->pm_qos_req);
  232. mcpdm->latency[stream1] = 0;
  233. mutex_unlock(&mcpdm->mutex);
  234. }
  235. static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
  236. struct snd_pcm_hw_params *params,
  237. struct snd_soc_dai *dai)
  238. {
  239. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  240. int stream = substream->stream;
  241. struct snd_dmaengine_dai_dma_data *dma_data;
  242. u32 threshold;
  243. int channels, latency;
  244. int link_mask = 0;
  245. channels = params_channels(params);
  246. switch (channels) {
  247. case 5:
  248. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  249. /* up to 3 channels for capture */
  250. return -EINVAL;
  251. link_mask |= 1 << 4;
  252. fallthrough;
  253. case 4:
  254. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  255. /* up to 3 channels for capture */
  256. return -EINVAL;
  257. link_mask |= 1 << 3;
  258. fallthrough;
  259. case 3:
  260. link_mask |= 1 << 2;
  261. fallthrough;
  262. case 2:
  263. link_mask |= 1 << 1;
  264. fallthrough;
  265. case 1:
  266. link_mask |= 1 << 0;
  267. break;
  268. default:
  269. /* unsupported number of channels */
  270. return -EINVAL;
  271. }
  272. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  273. threshold = mcpdm->config[stream].threshold;
  274. /* Configure McPDM channels, and DMA packet size */
  275. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  276. link_mask <<= 3;
  277. /* If capture is not running assume a stereo stream to come */
  278. if (!mcpdm->config[!stream].link_mask)
  279. mcpdm->config[!stream].link_mask = 0x3;
  280. dma_data->maxburst =
  281. (MCPDM_DN_THRES_MAX - threshold) * channels;
  282. latency = threshold;
  283. } else {
  284. /* If playback is not running assume a stereo stream to come */
  285. if (!mcpdm->config[!stream].link_mask)
  286. mcpdm->config[!stream].link_mask = (0x3 << 3);
  287. dma_data->maxburst = threshold * channels;
  288. latency = (MCPDM_DN_THRES_MAX - threshold);
  289. }
  290. /*
  291. * The DMA must act to a DMA request within latency time (usec) to avoid
  292. * under/overflow
  293. */
  294. mcpdm->latency[stream] = latency * USEC_PER_SEC / params_rate(params);
  295. if (!mcpdm->latency[stream])
  296. mcpdm->latency[stream] = 10;
  297. /* Check if we need to restart McPDM with this stream */
  298. if (mcpdm->config[stream].link_mask &&
  299. mcpdm->config[stream].link_mask != link_mask)
  300. mcpdm->restart = true;
  301. mcpdm->config[stream].link_mask = link_mask;
  302. return 0;
  303. }
  304. static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
  305. struct snd_soc_dai *dai)
  306. {
  307. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  308. struct pm_qos_request *pm_qos_req = &mcpdm->pm_qos_req;
  309. int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  310. int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
  311. int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
  312. int latency = mcpdm->latency[stream2];
  313. /* Prevent omap hardware from hitting off between FIFO fills */
  314. if (!latency || mcpdm->latency[stream1] < latency)
  315. latency = mcpdm->latency[stream1];
  316. if (cpu_latency_qos_request_active(pm_qos_req))
  317. cpu_latency_qos_update_request(pm_qos_req, latency);
  318. else if (latency)
  319. cpu_latency_qos_add_request(pm_qos_req, latency);
  320. if (!omap_mcpdm_active(mcpdm)) {
  321. omap_mcpdm_start(mcpdm);
  322. omap_mcpdm_reg_dump(mcpdm);
  323. } else if (mcpdm->restart) {
  324. omap_mcpdm_stop(mcpdm);
  325. omap_mcpdm_start(mcpdm);
  326. mcpdm->restart = false;
  327. omap_mcpdm_reg_dump(mcpdm);
  328. }
  329. return 0;
  330. }
  331. static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
  332. .startup = omap_mcpdm_dai_startup,
  333. .shutdown = omap_mcpdm_dai_shutdown,
  334. .hw_params = omap_mcpdm_dai_hw_params,
  335. .prepare = omap_mcpdm_prepare,
  336. };
  337. static int omap_mcpdm_probe(struct snd_soc_dai *dai)
  338. {
  339. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  340. int ret;
  341. pm_runtime_enable(mcpdm->dev);
  342. /* Disable lines while request is ongoing */
  343. pm_runtime_get_sync(mcpdm->dev);
  344. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
  345. ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
  346. (void *)mcpdm);
  347. pm_runtime_put_sync(mcpdm->dev);
  348. if (ret) {
  349. dev_err(mcpdm->dev, "Request for IRQ failed\n");
  350. pm_runtime_disable(mcpdm->dev);
  351. }
  352. /* Configure McPDM threshold values */
  353. mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
  354. mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
  355. MCPDM_UP_THRES_MAX - 3;
  356. snd_soc_dai_init_dma_data(dai,
  357. &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
  358. &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
  359. return ret;
  360. }
  361. static int omap_mcpdm_remove(struct snd_soc_dai *dai)
  362. {
  363. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  364. free_irq(mcpdm->irq, (void *)mcpdm);
  365. pm_runtime_disable(mcpdm->dev);
  366. if (cpu_latency_qos_request_active(&mcpdm->pm_qos_req))
  367. cpu_latency_qos_remove_request(&mcpdm->pm_qos_req);
  368. return 0;
  369. }
  370. #ifdef CONFIG_PM_SLEEP
  371. static int omap_mcpdm_suspend(struct snd_soc_component *component)
  372. {
  373. struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component);
  374. if (snd_soc_component_active(component)) {
  375. omap_mcpdm_stop(mcpdm);
  376. omap_mcpdm_close_streams(mcpdm);
  377. }
  378. mcpdm->pm_active_count = 0;
  379. while (pm_runtime_active(mcpdm->dev)) {
  380. pm_runtime_put_sync(mcpdm->dev);
  381. mcpdm->pm_active_count++;
  382. }
  383. return 0;
  384. }
  385. static int omap_mcpdm_resume(struct snd_soc_component *component)
  386. {
  387. struct omap_mcpdm *mcpdm = snd_soc_component_get_drvdata(component);
  388. if (mcpdm->pm_active_count) {
  389. while (mcpdm->pm_active_count--)
  390. pm_runtime_get_sync(mcpdm->dev);
  391. if (snd_soc_component_active(component)) {
  392. omap_mcpdm_open_streams(mcpdm);
  393. omap_mcpdm_start(mcpdm);
  394. }
  395. }
  396. return 0;
  397. }
  398. #else
  399. #define omap_mcpdm_suspend NULL
  400. #define omap_mcpdm_resume NULL
  401. #endif
  402. #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  403. #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
  404. static struct snd_soc_dai_driver omap_mcpdm_dai = {
  405. .probe = omap_mcpdm_probe,
  406. .remove = omap_mcpdm_remove,
  407. .probe_order = SND_SOC_COMP_ORDER_LATE,
  408. .remove_order = SND_SOC_COMP_ORDER_EARLY,
  409. .playback = {
  410. .channels_min = 1,
  411. .channels_max = 5,
  412. .rates = OMAP_MCPDM_RATES,
  413. .formats = OMAP_MCPDM_FORMATS,
  414. .sig_bits = 24,
  415. },
  416. .capture = {
  417. .channels_min = 1,
  418. .channels_max = 3,
  419. .rates = OMAP_MCPDM_RATES,
  420. .formats = OMAP_MCPDM_FORMATS,
  421. .sig_bits = 24,
  422. },
  423. .ops = &omap_mcpdm_dai_ops,
  424. };
  425. static const struct snd_soc_component_driver omap_mcpdm_component = {
  426. .name = "omap-mcpdm",
  427. .suspend = omap_mcpdm_suspend,
  428. .resume = omap_mcpdm_resume,
  429. };
  430. void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
  431. u8 rx1, u8 rx2)
  432. {
  433. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
  434. mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
  435. }
  436. EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
  437. static int asoc_mcpdm_probe(struct platform_device *pdev)
  438. {
  439. struct omap_mcpdm *mcpdm;
  440. struct resource *res;
  441. int ret;
  442. mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
  443. if (!mcpdm)
  444. return -ENOMEM;
  445. platform_set_drvdata(pdev, mcpdm);
  446. mutex_init(&mcpdm->mutex);
  447. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  448. if (res == NULL)
  449. return -ENOMEM;
  450. mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
  451. mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
  452. mcpdm->dma_data[0].filter_data = "dn_link";
  453. mcpdm->dma_data[1].filter_data = "up_link";
  454. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  455. mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
  456. if (IS_ERR(mcpdm->io_base))
  457. return PTR_ERR(mcpdm->io_base);
  458. mcpdm->irq = platform_get_irq(pdev, 0);
  459. if (mcpdm->irq < 0)
  460. return mcpdm->irq;
  461. mcpdm->dev = &pdev->dev;
  462. ret = devm_snd_soc_register_component(&pdev->dev,
  463. &omap_mcpdm_component,
  464. &omap_mcpdm_dai, 1);
  465. if (ret)
  466. return ret;
  467. return sdma_pcm_platform_register(&pdev->dev, "dn_link", "up_link");
  468. }
  469. static const struct of_device_id omap_mcpdm_of_match[] = {
  470. { .compatible = "ti,omap4-mcpdm", },
  471. { }
  472. };
  473. MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
  474. static struct platform_driver asoc_mcpdm_driver = {
  475. .driver = {
  476. .name = "omap-mcpdm",
  477. .of_match_table = omap_mcpdm_of_match,
  478. },
  479. .probe = asoc_mcpdm_probe,
  480. };
  481. module_platform_driver(asoc_mcpdm_driver);
  482. MODULE_ALIAS("platform:omap-mcpdm");
  483. MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
  484. MODULE_DESCRIPTION("OMAP PDM SoC Interface");
  485. MODULE_LICENSE("GPL");