omap-mcbsp.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
  4. *
  5. * Copyright (C) 2008 Nokia Corporation
  6. *
  7. * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  8. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/device.h>
  13. #include <linux/pm_runtime.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <sound/core.h>
  17. #include <sound/pcm.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/initval.h>
  20. #include <sound/soc.h>
  21. #include <sound/dmaengine_pcm.h>
  22. #include "omap-mcbsp-priv.h"
  23. #include "omap-mcbsp.h"
  24. #include "sdma-pcm.h"
  25. #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
  26. enum {
  27. OMAP_MCBSP_WORD_8 = 0,
  28. OMAP_MCBSP_WORD_12,
  29. OMAP_MCBSP_WORD_16,
  30. OMAP_MCBSP_WORD_20,
  31. OMAP_MCBSP_WORD_24,
  32. OMAP_MCBSP_WORD_32,
  33. };
  34. static void omap_mcbsp_dump_reg(struct omap_mcbsp *mcbsp)
  35. {
  36. dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  37. dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n", MCBSP_READ(mcbsp, DRR2));
  38. dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n", MCBSP_READ(mcbsp, DRR1));
  39. dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n", MCBSP_READ(mcbsp, DXR2));
  40. dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n", MCBSP_READ(mcbsp, DXR1));
  41. dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n", MCBSP_READ(mcbsp, SPCR2));
  42. dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n", MCBSP_READ(mcbsp, SPCR1));
  43. dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2));
  44. dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n", MCBSP_READ(mcbsp, RCR1));
  45. dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n", MCBSP_READ(mcbsp, XCR2));
  46. dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n", MCBSP_READ(mcbsp, XCR1));
  47. dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n", MCBSP_READ(mcbsp, SRGR2));
  48. dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n", MCBSP_READ(mcbsp, SRGR1));
  49. dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n", MCBSP_READ(mcbsp, PCR0));
  50. dev_dbg(mcbsp->dev, "***********************\n");
  51. }
  52. static int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id)
  53. {
  54. struct clk *fck_src;
  55. const char *src;
  56. int r;
  57. if (fck_src_id == MCBSP_CLKS_PAD_SRC)
  58. src = "pad_fck";
  59. else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
  60. src = "prcm_fck";
  61. else
  62. return -EINVAL;
  63. fck_src = clk_get(mcbsp->dev, src);
  64. if (IS_ERR(fck_src)) {
  65. dev_err(mcbsp->dev, "CLKS: could not clk_get() %s\n", src);
  66. return -EINVAL;
  67. }
  68. pm_runtime_put_sync(mcbsp->dev);
  69. r = clk_set_parent(mcbsp->fclk, fck_src);
  70. if (r)
  71. dev_err(mcbsp->dev, "CLKS: could not clk_set_parent() to %s\n",
  72. src);
  73. pm_runtime_get_sync(mcbsp->dev);
  74. clk_put(fck_src);
  75. return r;
  76. }
  77. static irqreturn_t omap_mcbsp_irq_handler(int irq, void *data)
  78. {
  79. struct omap_mcbsp *mcbsp = data;
  80. u16 irqst;
  81. irqst = MCBSP_READ(mcbsp, IRQST);
  82. dev_dbg(mcbsp->dev, "IRQ callback : 0x%x\n", irqst);
  83. if (irqst & RSYNCERREN)
  84. dev_err(mcbsp->dev, "RX Frame Sync Error!\n");
  85. if (irqst & RFSREN)
  86. dev_dbg(mcbsp->dev, "RX Frame Sync\n");
  87. if (irqst & REOFEN)
  88. dev_dbg(mcbsp->dev, "RX End Of Frame\n");
  89. if (irqst & RRDYEN)
  90. dev_dbg(mcbsp->dev, "RX Buffer Threshold Reached\n");
  91. if (irqst & RUNDFLEN)
  92. dev_err(mcbsp->dev, "RX Buffer Underflow!\n");
  93. if (irqst & ROVFLEN)
  94. dev_err(mcbsp->dev, "RX Buffer Overflow!\n");
  95. if (irqst & XSYNCERREN)
  96. dev_err(mcbsp->dev, "TX Frame Sync Error!\n");
  97. if (irqst & XFSXEN)
  98. dev_dbg(mcbsp->dev, "TX Frame Sync\n");
  99. if (irqst & XEOFEN)
  100. dev_dbg(mcbsp->dev, "TX End Of Frame\n");
  101. if (irqst & XRDYEN)
  102. dev_dbg(mcbsp->dev, "TX Buffer threshold Reached\n");
  103. if (irqst & XUNDFLEN)
  104. dev_err(mcbsp->dev, "TX Buffer Underflow!\n");
  105. if (irqst & XOVFLEN)
  106. dev_err(mcbsp->dev, "TX Buffer Overflow!\n");
  107. if (irqst & XEMPTYEOFEN)
  108. dev_dbg(mcbsp->dev, "TX Buffer empty at end of frame\n");
  109. MCBSP_WRITE(mcbsp, IRQST, irqst);
  110. return IRQ_HANDLED;
  111. }
  112. static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *data)
  113. {
  114. struct omap_mcbsp *mcbsp = data;
  115. u16 irqst_spcr2;
  116. irqst_spcr2 = MCBSP_READ(mcbsp, SPCR2);
  117. dev_dbg(mcbsp->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  118. if (irqst_spcr2 & XSYNC_ERR) {
  119. dev_err(mcbsp->dev, "TX Frame Sync Error! : 0x%x\n",
  120. irqst_spcr2);
  121. /* Writing zero to XSYNC_ERR clears the IRQ */
  122. MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
  123. }
  124. return IRQ_HANDLED;
  125. }
  126. static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *data)
  127. {
  128. struct omap_mcbsp *mcbsp = data;
  129. u16 irqst_spcr1;
  130. irqst_spcr1 = MCBSP_READ(mcbsp, SPCR1);
  131. dev_dbg(mcbsp->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
  132. if (irqst_spcr1 & RSYNC_ERR) {
  133. dev_err(mcbsp->dev, "RX Frame Sync Error! : 0x%x\n",
  134. irqst_spcr1);
  135. /* Writing zero to RSYNC_ERR clears the IRQ */
  136. MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
  137. }
  138. return IRQ_HANDLED;
  139. }
  140. /*
  141. * omap_mcbsp_config simply write a config to the
  142. * appropriate McBSP.
  143. * You either call this function or set the McBSP registers
  144. * by yourself before calling omap_mcbsp_start().
  145. */
  146. static void omap_mcbsp_config(struct omap_mcbsp *mcbsp,
  147. const struct omap_mcbsp_reg_cfg *config)
  148. {
  149. dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
  150. mcbsp->id, mcbsp->phys_base);
  151. /* We write the given config */
  152. MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
  153. MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
  154. MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
  155. MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
  156. MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
  157. MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
  158. MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
  159. MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
  160. MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
  161. MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
  162. MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
  163. if (mcbsp->pdata->has_ccr) {
  164. MCBSP_WRITE(mcbsp, XCCR, config->xccr);
  165. MCBSP_WRITE(mcbsp, RCCR, config->rccr);
  166. }
  167. /* Enable wakeup behavior */
  168. if (mcbsp->pdata->has_wakeup)
  169. MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
  170. /* Enable TX/RX sync error interrupts by default */
  171. if (mcbsp->irq)
  172. MCBSP_WRITE(mcbsp, IRQEN, RSYNCERREN | XSYNCERREN |
  173. RUNDFLEN | ROVFLEN | XUNDFLEN | XOVFLEN);
  174. }
  175. /**
  176. * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
  177. * @mcbsp: omap_mcbsp struct for the McBSP instance
  178. * @stream: Stream direction (playback/capture)
  179. *
  180. * Returns the address of mcbsp data transmit register or data receive register
  181. * to be used by DMA for transferring/receiving data
  182. */
  183. static int omap_mcbsp_dma_reg_params(struct omap_mcbsp *mcbsp,
  184. unsigned int stream)
  185. {
  186. int data_reg;
  187. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  188. if (mcbsp->pdata->reg_size == 2)
  189. data_reg = OMAP_MCBSP_REG_DXR1;
  190. else
  191. data_reg = OMAP_MCBSP_REG_DXR;
  192. } else {
  193. if (mcbsp->pdata->reg_size == 2)
  194. data_reg = OMAP_MCBSP_REG_DRR1;
  195. else
  196. data_reg = OMAP_MCBSP_REG_DRR;
  197. }
  198. return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
  199. }
  200. /*
  201. * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
  202. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  203. * for the THRSH2 register.
  204. */
  205. static void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
  206. {
  207. if (threshold && threshold <= mcbsp->max_tx_thres)
  208. MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
  209. }
  210. /*
  211. * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
  212. * The threshold parameter is 1 based, and it is converted (threshold - 1)
  213. * for the THRSH1 register.
  214. */
  215. static void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold)
  216. {
  217. if (threshold && threshold <= mcbsp->max_rx_thres)
  218. MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
  219. }
  220. /*
  221. * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
  222. */
  223. static u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp)
  224. {
  225. u16 buffstat;
  226. /* Returns the number of free locations in the buffer */
  227. buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
  228. /* Number of slots are different in McBSP ports */
  229. return mcbsp->pdata->buffer_size - buffstat;
  230. }
  231. /*
  232. * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
  233. * to reach the threshold value (when the DMA will be triggered to read it)
  234. */
  235. static u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp)
  236. {
  237. u16 buffstat, threshold;
  238. /* Returns the number of used locations in the buffer */
  239. buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
  240. /* RX threshold */
  241. threshold = MCBSP_READ(mcbsp, THRSH1);
  242. /* Return the number of location till we reach the threshold limit */
  243. if (threshold <= buffstat)
  244. return 0;
  245. else
  246. return threshold - buffstat;
  247. }
  248. static int omap_mcbsp_request(struct omap_mcbsp *mcbsp)
  249. {
  250. void *reg_cache;
  251. int err;
  252. reg_cache = kzalloc(mcbsp->reg_cache_size, GFP_KERNEL);
  253. if (!reg_cache)
  254. return -ENOMEM;
  255. spin_lock(&mcbsp->lock);
  256. if (!mcbsp->free) {
  257. dev_err(mcbsp->dev, "McBSP%d is currently in use\n", mcbsp->id);
  258. err = -EBUSY;
  259. goto err_kfree;
  260. }
  261. mcbsp->free = false;
  262. mcbsp->reg_cache = reg_cache;
  263. spin_unlock(&mcbsp->lock);
  264. if(mcbsp->pdata->ops && mcbsp->pdata->ops->request)
  265. mcbsp->pdata->ops->request(mcbsp->id - 1);
  266. /*
  267. * Make sure that transmitter, receiver and sample-rate generator are
  268. * not running before activating IRQs.
  269. */
  270. MCBSP_WRITE(mcbsp, SPCR1, 0);
  271. MCBSP_WRITE(mcbsp, SPCR2, 0);
  272. if (mcbsp->irq) {
  273. err = request_irq(mcbsp->irq, omap_mcbsp_irq_handler, 0,
  274. "McBSP", (void *)mcbsp);
  275. if (err != 0) {
  276. dev_err(mcbsp->dev, "Unable to request IRQ\n");
  277. goto err_clk_disable;
  278. }
  279. } else {
  280. err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler, 0,
  281. "McBSP TX", (void *)mcbsp);
  282. if (err != 0) {
  283. dev_err(mcbsp->dev, "Unable to request TX IRQ\n");
  284. goto err_clk_disable;
  285. }
  286. err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler, 0,
  287. "McBSP RX", (void *)mcbsp);
  288. if (err != 0) {
  289. dev_err(mcbsp->dev, "Unable to request RX IRQ\n");
  290. goto err_free_irq;
  291. }
  292. }
  293. return 0;
  294. err_free_irq:
  295. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  296. err_clk_disable:
  297. if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  298. mcbsp->pdata->ops->free(mcbsp->id - 1);
  299. /* Disable wakeup behavior */
  300. if (mcbsp->pdata->has_wakeup)
  301. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  302. spin_lock(&mcbsp->lock);
  303. mcbsp->free = true;
  304. mcbsp->reg_cache = NULL;
  305. err_kfree:
  306. spin_unlock(&mcbsp->lock);
  307. kfree(reg_cache);
  308. return err;
  309. }
  310. static void omap_mcbsp_free(struct omap_mcbsp *mcbsp)
  311. {
  312. void *reg_cache;
  313. if(mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  314. mcbsp->pdata->ops->free(mcbsp->id - 1);
  315. /* Disable wakeup behavior */
  316. if (mcbsp->pdata->has_wakeup)
  317. MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
  318. /* Disable interrupt requests */
  319. if (mcbsp->irq)
  320. MCBSP_WRITE(mcbsp, IRQEN, 0);
  321. if (mcbsp->irq) {
  322. free_irq(mcbsp->irq, (void *)mcbsp);
  323. } else {
  324. free_irq(mcbsp->rx_irq, (void *)mcbsp);
  325. free_irq(mcbsp->tx_irq, (void *)mcbsp);
  326. }
  327. reg_cache = mcbsp->reg_cache;
  328. /*
  329. * Select CLKS source from internal source unconditionally before
  330. * marking the McBSP port as free.
  331. * If the external clock source via MCBSP_CLKS pin has been selected the
  332. * system will refuse to enter idle if the CLKS pin source is not reset
  333. * back to internal source.
  334. */
  335. if (!mcbsp_omap1())
  336. omap2_mcbsp_set_clks_src(mcbsp, MCBSP_CLKS_PRCM_SRC);
  337. spin_lock(&mcbsp->lock);
  338. if (mcbsp->free)
  339. dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
  340. else
  341. mcbsp->free = true;
  342. mcbsp->reg_cache = NULL;
  343. spin_unlock(&mcbsp->lock);
  344. kfree(reg_cache);
  345. }
  346. /*
  347. * Here we start the McBSP, by enabling transmitter, receiver or both.
  348. * If no transmitter or receiver is active prior calling, then sample-rate
  349. * generator and frame sync are started.
  350. */
  351. static void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int stream)
  352. {
  353. int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
  354. int rx = !tx;
  355. int enable_srg = 0;
  356. u16 w;
  357. if (mcbsp->st_data)
  358. omap_mcbsp_st_start(mcbsp);
  359. /* Only enable SRG, if McBSP is master */
  360. w = MCBSP_READ_CACHE(mcbsp, PCR0);
  361. if (w & (FSXM | FSRM | CLKXM | CLKRM))
  362. enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  363. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  364. if (enable_srg) {
  365. /* Start the sample generator */
  366. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  367. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
  368. }
  369. /* Enable transmitter and receiver */
  370. tx &= 1;
  371. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  372. MCBSP_WRITE(mcbsp, SPCR2, w | tx);
  373. rx &= 1;
  374. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  375. MCBSP_WRITE(mcbsp, SPCR1, w | rx);
  376. /*
  377. * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
  378. * REVISIT: 100us may give enough time for two CLKSRG, however
  379. * due to some unknown PM related, clock gating etc. reason it
  380. * is now at 500us.
  381. */
  382. udelay(500);
  383. if (enable_srg) {
  384. /* Start frame sync */
  385. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  386. MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
  387. }
  388. if (mcbsp->pdata->has_ccr) {
  389. /* Release the transmitter and receiver */
  390. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  391. w &= ~(tx ? XDISABLE : 0);
  392. MCBSP_WRITE(mcbsp, XCCR, w);
  393. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  394. w &= ~(rx ? RDISABLE : 0);
  395. MCBSP_WRITE(mcbsp, RCCR, w);
  396. }
  397. /* Dump McBSP Regs */
  398. omap_mcbsp_dump_reg(mcbsp);
  399. }
  400. static void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int stream)
  401. {
  402. int tx = (stream == SNDRV_PCM_STREAM_PLAYBACK);
  403. int rx = !tx;
  404. int idle;
  405. u16 w;
  406. /* Reset transmitter */
  407. tx &= 1;
  408. if (mcbsp->pdata->has_ccr) {
  409. w = MCBSP_READ_CACHE(mcbsp, XCCR);
  410. w |= (tx ? XDISABLE : 0);
  411. MCBSP_WRITE(mcbsp, XCCR, w);
  412. }
  413. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  414. MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
  415. /* Reset receiver */
  416. rx &= 1;
  417. if (mcbsp->pdata->has_ccr) {
  418. w = MCBSP_READ_CACHE(mcbsp, RCCR);
  419. w |= (rx ? RDISABLE : 0);
  420. MCBSP_WRITE(mcbsp, RCCR, w);
  421. }
  422. w = MCBSP_READ_CACHE(mcbsp, SPCR1);
  423. MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
  424. idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
  425. MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
  426. if (idle) {
  427. /* Reset the sample rate generator */
  428. w = MCBSP_READ_CACHE(mcbsp, SPCR2);
  429. MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
  430. }
  431. if (mcbsp->st_data)
  432. omap_mcbsp_st_stop(mcbsp);
  433. }
  434. #define max_thres(m) (mcbsp->pdata->buffer_size)
  435. #define valid_threshold(m, val) ((val) <= max_thres(m))
  436. #define THRESHOLD_PROP_BUILDER(prop) \
  437. static ssize_t prop##_show(struct device *dev, \
  438. struct device_attribute *attr, char *buf) \
  439. { \
  440. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  441. \
  442. return sprintf(buf, "%u\n", mcbsp->prop); \
  443. } \
  444. \
  445. static ssize_t prop##_store(struct device *dev, \
  446. struct device_attribute *attr, \
  447. const char *buf, size_t size) \
  448. { \
  449. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
  450. unsigned long val; \
  451. int status; \
  452. \
  453. status = kstrtoul(buf, 0, &val); \
  454. if (status) \
  455. return status; \
  456. \
  457. if (!valid_threshold(mcbsp, val)) \
  458. return -EDOM; \
  459. \
  460. mcbsp->prop = val; \
  461. return size; \
  462. } \
  463. \
  464. static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store)
  465. THRESHOLD_PROP_BUILDER(max_tx_thres);
  466. THRESHOLD_PROP_BUILDER(max_rx_thres);
  467. static const char * const dma_op_modes[] = {
  468. "element", "threshold",
  469. };
  470. static ssize_t dma_op_mode_show(struct device *dev,
  471. struct device_attribute *attr, char *buf)
  472. {
  473. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  474. int dma_op_mode, i = 0;
  475. ssize_t len = 0;
  476. const char * const *s;
  477. dma_op_mode = mcbsp->dma_op_mode;
  478. for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
  479. if (dma_op_mode == i)
  480. len += sprintf(buf + len, "[%s] ", *s);
  481. else
  482. len += sprintf(buf + len, "%s ", *s);
  483. }
  484. len += sprintf(buf + len, "\n");
  485. return len;
  486. }
  487. static ssize_t dma_op_mode_store(struct device *dev,
  488. struct device_attribute *attr, const char *buf,
  489. size_t size)
  490. {
  491. struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
  492. int i;
  493. i = sysfs_match_string(dma_op_modes, buf);
  494. if (i < 0)
  495. return i;
  496. spin_lock_irq(&mcbsp->lock);
  497. if (!mcbsp->free) {
  498. size = -EBUSY;
  499. goto unlock;
  500. }
  501. mcbsp->dma_op_mode = i;
  502. unlock:
  503. spin_unlock_irq(&mcbsp->lock);
  504. return size;
  505. }
  506. static DEVICE_ATTR_RW(dma_op_mode);
  507. static const struct attribute *additional_attrs[] = {
  508. &dev_attr_max_tx_thres.attr,
  509. &dev_attr_max_rx_thres.attr,
  510. &dev_attr_dma_op_mode.attr,
  511. NULL,
  512. };
  513. static const struct attribute_group additional_attr_group = {
  514. .attrs = (struct attribute **)additional_attrs,
  515. };
  516. /*
  517. * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
  518. * 730 has only 2 McBSP, and both of them are MPU peripherals.
  519. */
  520. static int omap_mcbsp_init(struct platform_device *pdev)
  521. {
  522. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  523. struct resource *res;
  524. int ret = 0;
  525. spin_lock_init(&mcbsp->lock);
  526. mcbsp->free = true;
  527. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  528. if (!res)
  529. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  530. mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
  531. if (IS_ERR(mcbsp->io_base))
  532. return PTR_ERR(mcbsp->io_base);
  533. mcbsp->phys_base = res->start;
  534. mcbsp->reg_cache_size = resource_size(res);
  535. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  536. if (!res)
  537. mcbsp->phys_dma_base = mcbsp->phys_base;
  538. else
  539. mcbsp->phys_dma_base = res->start;
  540. /*
  541. * OMAP1, 2 uses two interrupt lines: TX, RX
  542. * OMAP2430, OMAP3 SoC have combined IRQ line as well.
  543. * OMAP4 and newer SoC only have the combined IRQ line.
  544. * Use the combined IRQ if available since it gives better debugging
  545. * possibilities.
  546. */
  547. mcbsp->irq = platform_get_irq_byname(pdev, "common");
  548. if (mcbsp->irq == -ENXIO) {
  549. mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
  550. if (mcbsp->tx_irq == -ENXIO) {
  551. mcbsp->irq = platform_get_irq(pdev, 0);
  552. mcbsp->tx_irq = 0;
  553. } else {
  554. mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
  555. mcbsp->irq = 0;
  556. }
  557. }
  558. if (!pdev->dev.of_node) {
  559. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  560. if (!res) {
  561. dev_err(&pdev->dev, "invalid tx DMA channel\n");
  562. return -ENODEV;
  563. }
  564. mcbsp->dma_req[0] = res->start;
  565. mcbsp->dma_data[0].filter_data = &mcbsp->dma_req[0];
  566. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  567. if (!res) {
  568. dev_err(&pdev->dev, "invalid rx DMA channel\n");
  569. return -ENODEV;
  570. }
  571. mcbsp->dma_req[1] = res->start;
  572. mcbsp->dma_data[1].filter_data = &mcbsp->dma_req[1];
  573. } else {
  574. mcbsp->dma_data[0].filter_data = "tx";
  575. mcbsp->dma_data[1].filter_data = "rx";
  576. }
  577. mcbsp->dma_data[0].addr = omap_mcbsp_dma_reg_params(mcbsp,
  578. SNDRV_PCM_STREAM_PLAYBACK);
  579. mcbsp->dma_data[1].addr = omap_mcbsp_dma_reg_params(mcbsp,
  580. SNDRV_PCM_STREAM_CAPTURE);
  581. mcbsp->fclk = devm_clk_get(&pdev->dev, "fck");
  582. if (IS_ERR(mcbsp->fclk)) {
  583. ret = PTR_ERR(mcbsp->fclk);
  584. dev_err(mcbsp->dev, "unable to get fck: %d\n", ret);
  585. return ret;
  586. }
  587. mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
  588. if (mcbsp->pdata->buffer_size) {
  589. /*
  590. * Initially configure the maximum thresholds to a safe value.
  591. * The McBSP FIFO usage with these values should not go under
  592. * 16 locations.
  593. * If the whole FIFO without safety buffer is used, than there
  594. * is a possibility that the DMA will be not able to push the
  595. * new data on time, causing channel shifts in runtime.
  596. */
  597. mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
  598. mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
  599. ret = sysfs_create_group(&mcbsp->dev->kobj,
  600. &additional_attr_group);
  601. if (ret) {
  602. dev_err(mcbsp->dev,
  603. "Unable to create additional controls\n");
  604. return ret;
  605. }
  606. }
  607. ret = omap_mcbsp_st_init(pdev);
  608. if (ret)
  609. goto err_st;
  610. return 0;
  611. err_st:
  612. if (mcbsp->pdata->buffer_size)
  613. sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
  614. return ret;
  615. }
  616. /*
  617. * Stream DMA parameters. DMA request line and port address are set runtime
  618. * since they are different between OMAP1 and later OMAPs
  619. */
  620. static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream,
  621. unsigned int packet_size)
  622. {
  623. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  624. struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
  625. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  626. int words;
  627. /* No need to proceed further if McBSP does not have FIFO */
  628. if (mcbsp->pdata->buffer_size == 0)
  629. return;
  630. /*
  631. * Configure McBSP threshold based on either:
  632. * packet_size, when the sDMA is in packet mode, or based on the
  633. * period size in THRESHOLD mode, otherwise use McBSP threshold = 1
  634. * for mono streams.
  635. */
  636. if (packet_size)
  637. words = packet_size;
  638. else
  639. words = 1;
  640. /* Configure McBSP internal buffer usage */
  641. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  642. omap_mcbsp_set_tx_threshold(mcbsp, words);
  643. else
  644. omap_mcbsp_set_rx_threshold(mcbsp, words);
  645. }
  646. static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  647. struct snd_pcm_hw_rule *rule)
  648. {
  649. struct snd_interval *buffer_size = hw_param_interval(params,
  650. SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
  651. struct snd_interval *channels = hw_param_interval(params,
  652. SNDRV_PCM_HW_PARAM_CHANNELS);
  653. struct omap_mcbsp *mcbsp = rule->private;
  654. struct snd_interval frames;
  655. int size;
  656. snd_interval_any(&frames);
  657. size = mcbsp->pdata->buffer_size;
  658. frames.min = size / channels->min;
  659. frames.integer = 1;
  660. return snd_interval_refine(buffer_size, &frames);
  661. }
  662. static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
  663. struct snd_soc_dai *cpu_dai)
  664. {
  665. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  666. int err = 0;
  667. if (!snd_soc_dai_active(cpu_dai))
  668. err = omap_mcbsp_request(mcbsp);
  669. /*
  670. * OMAP3 McBSP FIFO is word structured.
  671. * McBSP2 has 1024 + 256 = 1280 word long buffer,
  672. * McBSP1,3,4,5 has 128 word long buffer
  673. * This means that the size of the FIFO depends on the sample format.
  674. * For example on McBSP3:
  675. * 16bit samples: size is 128 * 2 = 256 bytes
  676. * 32bit samples: size is 128 * 4 = 512 bytes
  677. * It is simpler to place constraint for buffer and period based on
  678. * channels.
  679. * McBSP3 as example again (16 or 32 bit samples):
  680. * 1 channel (mono): size is 128 frames (128 words)
  681. * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
  682. * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
  683. */
  684. if (mcbsp->pdata->buffer_size) {
  685. /*
  686. * Rule for the buffer size. We should not allow
  687. * smaller buffer than the FIFO size to avoid underruns.
  688. * This applies only for the playback stream.
  689. */
  690. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  691. snd_pcm_hw_rule_add(substream->runtime, 0,
  692. SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
  693. omap_mcbsp_hwrule_min_buffersize,
  694. mcbsp,
  695. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  696. /* Make sure, that the period size is always even */
  697. snd_pcm_hw_constraint_step(substream->runtime, 0,
  698. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
  699. }
  700. return err;
  701. }
  702. static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
  703. struct snd_soc_dai *cpu_dai)
  704. {
  705. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  706. int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  707. int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
  708. int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
  709. if (mcbsp->latency[stream2])
  710. cpu_latency_qos_update_request(&mcbsp->pm_qos_req,
  711. mcbsp->latency[stream2]);
  712. else if (mcbsp->latency[stream1])
  713. cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
  714. mcbsp->latency[stream1] = 0;
  715. if (!snd_soc_dai_active(cpu_dai)) {
  716. omap_mcbsp_free(mcbsp);
  717. mcbsp->configured = 0;
  718. }
  719. }
  720. static int omap_mcbsp_dai_prepare(struct snd_pcm_substream *substream,
  721. struct snd_soc_dai *cpu_dai)
  722. {
  723. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  724. struct pm_qos_request *pm_qos_req = &mcbsp->pm_qos_req;
  725. int tx = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  726. int stream1 = tx ? SNDRV_PCM_STREAM_PLAYBACK : SNDRV_PCM_STREAM_CAPTURE;
  727. int stream2 = tx ? SNDRV_PCM_STREAM_CAPTURE : SNDRV_PCM_STREAM_PLAYBACK;
  728. int latency = mcbsp->latency[stream2];
  729. /* Prevent omap hardware from hitting off between FIFO fills */
  730. if (!latency || mcbsp->latency[stream1] < latency)
  731. latency = mcbsp->latency[stream1];
  732. if (cpu_latency_qos_request_active(pm_qos_req))
  733. cpu_latency_qos_update_request(pm_qos_req, latency);
  734. else if (latency)
  735. cpu_latency_qos_add_request(pm_qos_req, latency);
  736. return 0;
  737. }
  738. static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  739. struct snd_soc_dai *cpu_dai)
  740. {
  741. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  742. switch (cmd) {
  743. case SNDRV_PCM_TRIGGER_START:
  744. case SNDRV_PCM_TRIGGER_RESUME:
  745. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  746. mcbsp->active++;
  747. omap_mcbsp_start(mcbsp, substream->stream);
  748. break;
  749. case SNDRV_PCM_TRIGGER_STOP:
  750. case SNDRV_PCM_TRIGGER_SUSPEND:
  751. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  752. omap_mcbsp_stop(mcbsp, substream->stream);
  753. mcbsp->active--;
  754. break;
  755. default:
  756. return -EINVAL;
  757. }
  758. return 0;
  759. }
  760. static snd_pcm_sframes_t omap_mcbsp_dai_delay(
  761. struct snd_pcm_substream *substream,
  762. struct snd_soc_dai *dai)
  763. {
  764. struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
  765. struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
  766. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  767. u16 fifo_use;
  768. snd_pcm_sframes_t delay;
  769. /* No need to proceed further if McBSP does not have FIFO */
  770. if (mcbsp->pdata->buffer_size == 0)
  771. return 0;
  772. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  773. fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
  774. else
  775. fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
  776. /*
  777. * Divide the used locations with the channel count to get the
  778. * FIFO usage in samples (don't care about partial samples in the
  779. * buffer).
  780. */
  781. delay = fifo_use / substream->runtime->channels;
  782. return delay;
  783. }
  784. static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
  785. struct snd_pcm_hw_params *params,
  786. struct snd_soc_dai *cpu_dai)
  787. {
  788. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  789. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  790. struct snd_dmaengine_dai_dma_data *dma_data;
  791. int wlen, channels, wpf;
  792. int pkt_size = 0;
  793. unsigned int format, div, framesize, master;
  794. unsigned int buffer_size = mcbsp->pdata->buffer_size;
  795. dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
  796. channels = params_channels(params);
  797. switch (params_format(params)) {
  798. case SNDRV_PCM_FORMAT_S16_LE:
  799. wlen = 16;
  800. break;
  801. case SNDRV_PCM_FORMAT_S32_LE:
  802. wlen = 32;
  803. break;
  804. default:
  805. return -EINVAL;
  806. }
  807. if (buffer_size) {
  808. int latency;
  809. if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
  810. int period_words, max_thrsh;
  811. int divider = 0;
  812. period_words = params_period_bytes(params) / (wlen / 8);
  813. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  814. max_thrsh = mcbsp->max_tx_thres;
  815. else
  816. max_thrsh = mcbsp->max_rx_thres;
  817. /*
  818. * Use sDMA packet mode if McBSP is in threshold mode:
  819. * If period words less than the FIFO size the packet
  820. * size is set to the number of period words, otherwise
  821. * Look for the biggest threshold value which divides
  822. * the period size evenly.
  823. */
  824. divider = period_words / max_thrsh;
  825. if (period_words % max_thrsh)
  826. divider++;
  827. while (period_words % divider &&
  828. divider < period_words)
  829. divider++;
  830. if (divider == period_words)
  831. return -EINVAL;
  832. pkt_size = period_words / divider;
  833. } else if (channels > 1) {
  834. /* Use packet mode for non mono streams */
  835. pkt_size = channels;
  836. }
  837. latency = (buffer_size - pkt_size) / channels;
  838. latency = latency * USEC_PER_SEC /
  839. (params->rate_num / params->rate_den);
  840. mcbsp->latency[substream->stream] = latency;
  841. omap_mcbsp_set_threshold(substream, pkt_size);
  842. }
  843. dma_data->maxburst = pkt_size;
  844. if (mcbsp->configured) {
  845. /* McBSP already configured by another stream */
  846. return 0;
  847. }
  848. regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
  849. regs->xcr2 &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
  850. regs->rcr1 &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
  851. regs->xcr1 &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
  852. format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  853. wpf = channels;
  854. if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
  855. format == SND_SOC_DAIFMT_LEFT_J)) {
  856. /* Use dual-phase frames */
  857. regs->rcr2 |= RPHASE;
  858. regs->xcr2 |= XPHASE;
  859. /* Set 1 word per (McBSP) frame for phase1 and phase2 */
  860. wpf--;
  861. regs->rcr2 |= RFRLEN2(wpf - 1);
  862. regs->xcr2 |= XFRLEN2(wpf - 1);
  863. }
  864. regs->rcr1 |= RFRLEN1(wpf - 1);
  865. regs->xcr1 |= XFRLEN1(wpf - 1);
  866. switch (params_format(params)) {
  867. case SNDRV_PCM_FORMAT_S16_LE:
  868. /* Set word lengths */
  869. regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
  870. regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
  871. regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
  872. regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
  873. break;
  874. case SNDRV_PCM_FORMAT_S32_LE:
  875. /* Set word lengths */
  876. regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32);
  877. regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_32);
  878. regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_32);
  879. regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_32);
  880. break;
  881. default:
  882. /* Unsupported PCM format */
  883. return -EINVAL;
  884. }
  885. /* In McBSP master modes, FRAME (i.e. sample rate) is generated
  886. * by _counting_ BCLKs. Calculate frame size in BCLKs */
  887. master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
  888. if (master == SND_SOC_DAIFMT_CBS_CFS) {
  889. div = mcbsp->clk_div ? mcbsp->clk_div : 1;
  890. framesize = (mcbsp->in_freq / div) / params_rate(params);
  891. if (framesize < wlen * channels) {
  892. printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
  893. "channels\n", __func__);
  894. return -EINVAL;
  895. }
  896. } else
  897. framesize = wlen * channels;
  898. /* Set FS period and length in terms of bit clock periods */
  899. regs->srgr2 &= ~FPER(0xfff);
  900. regs->srgr1 &= ~FWID(0xff);
  901. switch (format) {
  902. case SND_SOC_DAIFMT_I2S:
  903. case SND_SOC_DAIFMT_LEFT_J:
  904. regs->srgr2 |= FPER(framesize - 1);
  905. regs->srgr1 |= FWID((framesize >> 1) - 1);
  906. break;
  907. case SND_SOC_DAIFMT_DSP_A:
  908. case SND_SOC_DAIFMT_DSP_B:
  909. regs->srgr2 |= FPER(framesize - 1);
  910. regs->srgr1 |= FWID(0);
  911. break;
  912. }
  913. omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
  914. mcbsp->wlen = wlen;
  915. mcbsp->configured = 1;
  916. return 0;
  917. }
  918. /*
  919. * This must be called before _set_clkdiv and _set_sysclk since McBSP register
  920. * cache is initialized here
  921. */
  922. static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  923. unsigned int fmt)
  924. {
  925. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  926. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  927. bool inv_fs = false;
  928. if (mcbsp->configured)
  929. return 0;
  930. mcbsp->fmt = fmt;
  931. memset(regs, 0, sizeof(*regs));
  932. /* Generic McBSP register settings */
  933. regs->spcr2 |= XINTM(3) | FREE;
  934. regs->spcr1 |= RINTM(3);
  935. /* RFIG and XFIG are not defined in 2430 and on OMAP3+ */
  936. if (!mcbsp->pdata->has_ccr) {
  937. regs->rcr2 |= RFIG;
  938. regs->xcr2 |= XFIG;
  939. }
  940. /* Configure XCCR/RCCR only for revisions which have ccr registers */
  941. if (mcbsp->pdata->has_ccr) {
  942. regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
  943. regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
  944. }
  945. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  946. case SND_SOC_DAIFMT_I2S:
  947. /* 1-bit data delay */
  948. regs->rcr2 |= RDATDLY(1);
  949. regs->xcr2 |= XDATDLY(1);
  950. break;
  951. case SND_SOC_DAIFMT_LEFT_J:
  952. /* 0-bit data delay */
  953. regs->rcr2 |= RDATDLY(0);
  954. regs->xcr2 |= XDATDLY(0);
  955. regs->spcr1 |= RJUST(2);
  956. /* Invert FS polarity configuration */
  957. inv_fs = true;
  958. break;
  959. case SND_SOC_DAIFMT_DSP_A:
  960. /* 1-bit data delay */
  961. regs->rcr2 |= RDATDLY(1);
  962. regs->xcr2 |= XDATDLY(1);
  963. /* Invert FS polarity configuration */
  964. inv_fs = true;
  965. break;
  966. case SND_SOC_DAIFMT_DSP_B:
  967. /* 0-bit data delay */
  968. regs->rcr2 |= RDATDLY(0);
  969. regs->xcr2 |= XDATDLY(0);
  970. /* Invert FS polarity configuration */
  971. inv_fs = true;
  972. break;
  973. default:
  974. /* Unsupported data format */
  975. return -EINVAL;
  976. }
  977. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  978. case SND_SOC_DAIFMT_CBS_CFS:
  979. /* McBSP master. Set FS and bit clocks as outputs */
  980. regs->pcr0 |= FSXM | FSRM |
  981. CLKXM | CLKRM;
  982. /* Sample rate generator drives the FS */
  983. regs->srgr2 |= FSGM;
  984. break;
  985. case SND_SOC_DAIFMT_CBM_CFS:
  986. /* McBSP slave. FS clock as output */
  987. regs->srgr2 |= FSGM;
  988. regs->pcr0 |= FSXM | FSRM;
  989. break;
  990. case SND_SOC_DAIFMT_CBM_CFM:
  991. /* McBSP slave */
  992. break;
  993. default:
  994. /* Unsupported master/slave configuration */
  995. return -EINVAL;
  996. }
  997. /* Set bit clock (CLKX/CLKR) and FS polarities */
  998. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  999. case SND_SOC_DAIFMT_NB_NF:
  1000. /*
  1001. * Normal BCLK + FS.
  1002. * FS active low. TX data driven on falling edge of bit clock
  1003. * and RX data sampled on rising edge of bit clock.
  1004. */
  1005. regs->pcr0 |= FSXP | FSRP |
  1006. CLKXP | CLKRP;
  1007. break;
  1008. case SND_SOC_DAIFMT_NB_IF:
  1009. regs->pcr0 |= CLKXP | CLKRP;
  1010. break;
  1011. case SND_SOC_DAIFMT_IB_NF:
  1012. regs->pcr0 |= FSXP | FSRP;
  1013. break;
  1014. case SND_SOC_DAIFMT_IB_IF:
  1015. break;
  1016. default:
  1017. return -EINVAL;
  1018. }
  1019. if (inv_fs)
  1020. regs->pcr0 ^= FSXP | FSRP;
  1021. return 0;
  1022. }
  1023. static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
  1024. int div_id, int div)
  1025. {
  1026. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  1027. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  1028. if (div_id != OMAP_MCBSP_CLKGDV)
  1029. return -ENODEV;
  1030. mcbsp->clk_div = div;
  1031. regs->srgr1 &= ~CLKGDV(0xff);
  1032. regs->srgr1 |= CLKGDV(div - 1);
  1033. return 0;
  1034. }
  1035. static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  1036. int clk_id, unsigned int freq,
  1037. int dir)
  1038. {
  1039. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  1040. struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
  1041. int err = 0;
  1042. if (mcbsp->active) {
  1043. if (freq == mcbsp->in_freq)
  1044. return 0;
  1045. else
  1046. return -EBUSY;
  1047. }
  1048. mcbsp->in_freq = freq;
  1049. regs->srgr2 &= ~CLKSM;
  1050. regs->pcr0 &= ~SCLKME;
  1051. switch (clk_id) {
  1052. case OMAP_MCBSP_SYSCLK_CLK:
  1053. regs->srgr2 |= CLKSM;
  1054. break;
  1055. case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
  1056. if (mcbsp_omap1()) {
  1057. err = -EINVAL;
  1058. break;
  1059. }
  1060. err = omap2_mcbsp_set_clks_src(mcbsp,
  1061. MCBSP_CLKS_PRCM_SRC);
  1062. break;
  1063. case OMAP_MCBSP_SYSCLK_CLKS_EXT:
  1064. if (mcbsp_omap1()) {
  1065. err = 0;
  1066. break;
  1067. }
  1068. err = omap2_mcbsp_set_clks_src(mcbsp,
  1069. MCBSP_CLKS_PAD_SRC);
  1070. break;
  1071. case OMAP_MCBSP_SYSCLK_CLKX_EXT:
  1072. regs->srgr2 |= CLKSM;
  1073. regs->pcr0 |= SCLKME;
  1074. /*
  1075. * If McBSP is master but yet the CLKX/CLKR pin drives the SRG,
  1076. * disable output on those pins. This enables to inject the
  1077. * reference clock through CLKX/CLKR. For this to work
  1078. * set_dai_sysclk() _needs_ to be called after set_dai_fmt().
  1079. */
  1080. regs->pcr0 &= ~CLKXM;
  1081. break;
  1082. case OMAP_MCBSP_SYSCLK_CLKR_EXT:
  1083. regs->pcr0 |= SCLKME;
  1084. /* Disable ouput on CLKR pin in master mode */
  1085. regs->pcr0 &= ~CLKRM;
  1086. break;
  1087. default:
  1088. err = -ENODEV;
  1089. }
  1090. return err;
  1091. }
  1092. static const struct snd_soc_dai_ops mcbsp_dai_ops = {
  1093. .startup = omap_mcbsp_dai_startup,
  1094. .shutdown = omap_mcbsp_dai_shutdown,
  1095. .prepare = omap_mcbsp_dai_prepare,
  1096. .trigger = omap_mcbsp_dai_trigger,
  1097. .delay = omap_mcbsp_dai_delay,
  1098. .hw_params = omap_mcbsp_dai_hw_params,
  1099. .set_fmt = omap_mcbsp_dai_set_dai_fmt,
  1100. .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
  1101. .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
  1102. };
  1103. static int omap_mcbsp_probe(struct snd_soc_dai *dai)
  1104. {
  1105. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
  1106. pm_runtime_enable(mcbsp->dev);
  1107. snd_soc_dai_init_dma_data(dai,
  1108. &mcbsp->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
  1109. &mcbsp->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
  1110. return 0;
  1111. }
  1112. static int omap_mcbsp_remove(struct snd_soc_dai *dai)
  1113. {
  1114. struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
  1115. pm_runtime_disable(mcbsp->dev);
  1116. return 0;
  1117. }
  1118. static struct snd_soc_dai_driver omap_mcbsp_dai = {
  1119. .probe = omap_mcbsp_probe,
  1120. .remove = omap_mcbsp_remove,
  1121. .playback = {
  1122. .channels_min = 1,
  1123. .channels_max = 16,
  1124. .rates = OMAP_MCBSP_RATES,
  1125. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
  1126. },
  1127. .capture = {
  1128. .channels_min = 1,
  1129. .channels_max = 16,
  1130. .rates = OMAP_MCBSP_RATES,
  1131. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
  1132. },
  1133. .ops = &mcbsp_dai_ops,
  1134. };
  1135. static const struct snd_soc_component_driver omap_mcbsp_component = {
  1136. .name = "omap-mcbsp",
  1137. };
  1138. static struct omap_mcbsp_platform_data omap2420_pdata = {
  1139. .reg_step = 4,
  1140. .reg_size = 2,
  1141. };
  1142. static struct omap_mcbsp_platform_data omap2430_pdata = {
  1143. .reg_step = 4,
  1144. .reg_size = 4,
  1145. .has_ccr = true,
  1146. };
  1147. static struct omap_mcbsp_platform_data omap3_pdata = {
  1148. .reg_step = 4,
  1149. .reg_size = 4,
  1150. .has_ccr = true,
  1151. .has_wakeup = true,
  1152. };
  1153. static struct omap_mcbsp_platform_data omap4_pdata = {
  1154. .reg_step = 4,
  1155. .reg_size = 4,
  1156. .has_ccr = true,
  1157. .has_wakeup = true,
  1158. };
  1159. static const struct of_device_id omap_mcbsp_of_match[] = {
  1160. {
  1161. .compatible = "ti,omap2420-mcbsp",
  1162. .data = &omap2420_pdata,
  1163. },
  1164. {
  1165. .compatible = "ti,omap2430-mcbsp",
  1166. .data = &omap2430_pdata,
  1167. },
  1168. {
  1169. .compatible = "ti,omap3-mcbsp",
  1170. .data = &omap3_pdata,
  1171. },
  1172. {
  1173. .compatible = "ti,omap4-mcbsp",
  1174. .data = &omap4_pdata,
  1175. },
  1176. { },
  1177. };
  1178. MODULE_DEVICE_TABLE(of, omap_mcbsp_of_match);
  1179. static int asoc_mcbsp_probe(struct platform_device *pdev)
  1180. {
  1181. struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1182. struct omap_mcbsp *mcbsp;
  1183. const struct of_device_id *match;
  1184. int ret;
  1185. match = of_match_device(omap_mcbsp_of_match, &pdev->dev);
  1186. if (match) {
  1187. struct device_node *node = pdev->dev.of_node;
  1188. struct omap_mcbsp_platform_data *pdata_quirk = pdata;
  1189. int buffer_size;
  1190. pdata = devm_kzalloc(&pdev->dev,
  1191. sizeof(struct omap_mcbsp_platform_data),
  1192. GFP_KERNEL);
  1193. if (!pdata)
  1194. return -ENOMEM;
  1195. memcpy(pdata, match->data, sizeof(*pdata));
  1196. if (!of_property_read_u32(node, "ti,buffer-size", &buffer_size))
  1197. pdata->buffer_size = buffer_size;
  1198. if (pdata_quirk)
  1199. pdata->force_ick_on = pdata_quirk->force_ick_on;
  1200. } else if (!pdata) {
  1201. dev_err(&pdev->dev, "missing platform data.\n");
  1202. return -EINVAL;
  1203. }
  1204. mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
  1205. if (!mcbsp)
  1206. return -ENOMEM;
  1207. mcbsp->id = pdev->id;
  1208. mcbsp->pdata = pdata;
  1209. mcbsp->dev = &pdev->dev;
  1210. platform_set_drvdata(pdev, mcbsp);
  1211. ret = omap_mcbsp_init(pdev);
  1212. if (ret)
  1213. return ret;
  1214. if (mcbsp->pdata->reg_size == 2) {
  1215. omap_mcbsp_dai.playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
  1216. omap_mcbsp_dai.capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
  1217. }
  1218. ret = devm_snd_soc_register_component(&pdev->dev,
  1219. &omap_mcbsp_component,
  1220. &omap_mcbsp_dai, 1);
  1221. if (ret)
  1222. return ret;
  1223. return sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
  1224. }
  1225. static int asoc_mcbsp_remove(struct platform_device *pdev)
  1226. {
  1227. struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
  1228. if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
  1229. mcbsp->pdata->ops->free(mcbsp->id);
  1230. if (cpu_latency_qos_request_active(&mcbsp->pm_qos_req))
  1231. cpu_latency_qos_remove_request(&mcbsp->pm_qos_req);
  1232. if (mcbsp->pdata->buffer_size)
  1233. sysfs_remove_group(&mcbsp->dev->kobj, &additional_attr_group);
  1234. omap_mcbsp_st_cleanup(pdev);
  1235. return 0;
  1236. }
  1237. static struct platform_driver asoc_mcbsp_driver = {
  1238. .driver = {
  1239. .name = "omap-mcbsp",
  1240. .of_match_table = omap_mcbsp_of_match,
  1241. },
  1242. .probe = asoc_mcbsp_probe,
  1243. .remove = asoc_mcbsp_remove,
  1244. };
  1245. module_platform_driver(asoc_mcbsp_driver);
  1246. MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
  1247. MODULE_DESCRIPTION("OMAP I2S SoC Interface");
  1248. MODULE_LICENSE("GPL");
  1249. MODULE_ALIAS("platform:omap-mcbsp");