omap-mcbsp-priv.h 8.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * OMAP Multi-Channel Buffered Serial Port
  4. *
  5. * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
  6. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  7. */
  8. #ifndef __OMAP_MCBSP_PRIV_H__
  9. #define __OMAP_MCBSP_PRIV_H__
  10. #include <linux/platform_data/asoc-ti-mcbsp.h>
  11. #ifdef CONFIG_ARCH_OMAP1
  12. #define mcbsp_omap1() 1
  13. #else
  14. #define mcbsp_omap1() 0
  15. #endif
  16. /* McBSP register numbers. Register address offset = num * reg_step */
  17. enum {
  18. /* Common registers */
  19. OMAP_MCBSP_REG_SPCR2 = 4,
  20. OMAP_MCBSP_REG_SPCR1,
  21. OMAP_MCBSP_REG_RCR2,
  22. OMAP_MCBSP_REG_RCR1,
  23. OMAP_MCBSP_REG_XCR2,
  24. OMAP_MCBSP_REG_XCR1,
  25. OMAP_MCBSP_REG_SRGR2,
  26. OMAP_MCBSP_REG_SRGR1,
  27. OMAP_MCBSP_REG_MCR2,
  28. OMAP_MCBSP_REG_MCR1,
  29. OMAP_MCBSP_REG_RCERA,
  30. OMAP_MCBSP_REG_RCERB,
  31. OMAP_MCBSP_REG_XCERA,
  32. OMAP_MCBSP_REG_XCERB,
  33. OMAP_MCBSP_REG_PCR0,
  34. OMAP_MCBSP_REG_RCERC,
  35. OMAP_MCBSP_REG_RCERD,
  36. OMAP_MCBSP_REG_XCERC,
  37. OMAP_MCBSP_REG_XCERD,
  38. OMAP_MCBSP_REG_RCERE,
  39. OMAP_MCBSP_REG_RCERF,
  40. OMAP_MCBSP_REG_XCERE,
  41. OMAP_MCBSP_REG_XCERF,
  42. OMAP_MCBSP_REG_RCERG,
  43. OMAP_MCBSP_REG_RCERH,
  44. OMAP_MCBSP_REG_XCERG,
  45. OMAP_MCBSP_REG_XCERH,
  46. /* OMAP1-OMAP2420 registers */
  47. OMAP_MCBSP_REG_DRR2 = 0,
  48. OMAP_MCBSP_REG_DRR1,
  49. OMAP_MCBSP_REG_DXR2,
  50. OMAP_MCBSP_REG_DXR1,
  51. /* OMAP2430 and onwards */
  52. OMAP_MCBSP_REG_DRR = 0,
  53. OMAP_MCBSP_REG_DXR = 2,
  54. OMAP_MCBSP_REG_SYSCON = 35,
  55. OMAP_MCBSP_REG_THRSH2,
  56. OMAP_MCBSP_REG_THRSH1,
  57. OMAP_MCBSP_REG_IRQST = 40,
  58. OMAP_MCBSP_REG_IRQEN,
  59. OMAP_MCBSP_REG_WAKEUPEN,
  60. OMAP_MCBSP_REG_XCCR,
  61. OMAP_MCBSP_REG_RCCR,
  62. OMAP_MCBSP_REG_XBUFFSTAT,
  63. OMAP_MCBSP_REG_RBUFFSTAT,
  64. OMAP_MCBSP_REG_SSELCR,
  65. };
  66. /************************** McBSP SPCR1 bit definitions ***********************/
  67. #define RRST BIT(0)
  68. #define RRDY BIT(1)
  69. #define RFULL BIT(2)
  70. #define RSYNC_ERR BIT(3)
  71. #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
  72. #define ABIS BIT(6)
  73. #define DXENA BIT(7)
  74. #define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */
  75. #define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */
  76. #define ALB BIT(15)
  77. #define DLB BIT(15)
  78. /************************** McBSP SPCR2 bit definitions ***********************/
  79. #define XRST BIT(0)
  80. #define XRDY BIT(1)
  81. #define XEMPTY BIT(2)
  82. #define XSYNC_ERR BIT(3)
  83. #define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */
  84. #define GRST BIT(6)
  85. #define FRST BIT(7)
  86. #define SOFT BIT(8)
  87. #define FREE BIT(9)
  88. /************************** McBSP PCR bit definitions *************************/
  89. #define CLKRP BIT(0)
  90. #define CLKXP BIT(1)
  91. #define FSRP BIT(2)
  92. #define FSXP BIT(3)
  93. #define DR_STAT BIT(4)
  94. #define DX_STAT BIT(5)
  95. #define CLKS_STAT BIT(6)
  96. #define SCLKME BIT(7)
  97. #define CLKRM BIT(8)
  98. #define CLKXM BIT(9)
  99. #define FSRM BIT(10)
  100. #define FSXM BIT(11)
  101. #define RIOEN BIT(12)
  102. #define XIOEN BIT(13)
  103. #define IDLE_EN BIT(14)
  104. /************************** McBSP RCR1 bit definitions ************************/
  105. #define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
  106. #define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
  107. /************************** McBSP XCR1 bit definitions ************************/
  108. #define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */
  109. #define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
  110. /*************************** McBSP RCR2 bit definitions ***********************/
  111. #define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
  112. #define RFIG BIT(2)
  113. #define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
  114. #define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
  115. #define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
  116. #define RPHASE BIT(15)
  117. /*************************** McBSP XCR2 bit definitions ***********************/
  118. #define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */
  119. #define XFIG BIT(2)
  120. #define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */
  121. #define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */
  122. #define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */
  123. #define XPHASE BIT(15)
  124. /************************* McBSP SRGR1 bit definitions ************************/
  125. #define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */
  126. #define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */
  127. /************************* McBSP SRGR2 bit definitions ************************/
  128. #define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */
  129. #define FSGM BIT(12)
  130. #define CLKSM BIT(13)
  131. #define CLKSP BIT(14)
  132. #define GSYNC BIT(15)
  133. /************************* McBSP MCR1 bit definitions *************************/
  134. #define RMCM BIT(0)
  135. #define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
  136. #define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
  137. #define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
  138. /************************* McBSP MCR2 bit definitions *************************/
  139. #define XMCM(value) ((value) & 0x3) /* Bits 0:1 */
  140. #define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */
  141. #define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */
  142. #define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */
  143. /*********************** McBSP XCCR bit definitions *************************/
  144. #define XDISABLE BIT(0)
  145. #define XDMAEN BIT(3)
  146. #define DILB BIT(5)
  147. #define XFULL_CYCLE BIT(11)
  148. #define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */
  149. #define PPCONNECT BIT(14)
  150. #define EXTCLKGATE BIT(15)
  151. /********************** McBSP RCCR bit definitions *************************/
  152. #define RDISABLE BIT(0)
  153. #define RDMAEN BIT(3)
  154. #define RFULL_CYCLE BIT(11)
  155. /********************** McBSP SYSCONFIG bit definitions ********************/
  156. #define SOFTRST BIT(1)
  157. #define ENAWAKEUP BIT(2)
  158. #define SIDLEMODE(value) (((value) & 0x3) << 3)
  159. #define CLOCKACTIVITY(value) (((value) & 0x3) << 8)
  160. /********************** McBSP DMA operating modes **************************/
  161. #define MCBSP_DMA_MODE_ELEMENT 0
  162. #define MCBSP_DMA_MODE_THRESHOLD 1
  163. /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/
  164. #define RSYNCERREN BIT(0)
  165. #define RFSREN BIT(1)
  166. #define REOFEN BIT(2)
  167. #define RRDYEN BIT(3)
  168. #define RUNDFLEN BIT(4)
  169. #define ROVFLEN BIT(5)
  170. #define XSYNCERREN BIT(7)
  171. #define XFSXEN BIT(8)
  172. #define XEOFEN BIT(9)
  173. #define XRDYEN BIT(10)
  174. #define XUNDFLEN BIT(11)
  175. #define XOVFLEN BIT(12)
  176. #define XEMPTYEOFEN BIT(14)
  177. /* Clock signal muxing options */
  178. #define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */
  179. #define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */
  180. #define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */
  181. #define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */
  182. /* McBSP functional clock sources */
  183. #define MCBSP_CLKS_PRCM_SRC 0
  184. #define MCBSP_CLKS_PAD_SRC 1
  185. /* we don't do multichannel for now */
  186. struct omap_mcbsp_reg_cfg {
  187. u16 spcr2;
  188. u16 spcr1;
  189. u16 rcr2;
  190. u16 rcr1;
  191. u16 xcr2;
  192. u16 xcr1;
  193. u16 srgr2;
  194. u16 srgr1;
  195. u16 mcr2;
  196. u16 mcr1;
  197. u16 pcr0;
  198. u16 rcerc;
  199. u16 rcerd;
  200. u16 xcerc;
  201. u16 xcerd;
  202. u16 rcere;
  203. u16 rcerf;
  204. u16 xcere;
  205. u16 xcerf;
  206. u16 rcerg;
  207. u16 rcerh;
  208. u16 xcerg;
  209. u16 xcerh;
  210. u16 xccr;
  211. u16 rccr;
  212. };
  213. struct omap_mcbsp_st_data;
  214. struct omap_mcbsp {
  215. struct device *dev;
  216. struct clk *fclk;
  217. spinlock_t lock;
  218. unsigned long phys_base;
  219. unsigned long phys_dma_base;
  220. void __iomem *io_base;
  221. u8 id;
  222. /*
  223. * Flags indicating is the bus already activated and configured by
  224. * another substream
  225. */
  226. int active;
  227. int configured;
  228. u8 free;
  229. int irq;
  230. int rx_irq;
  231. int tx_irq;
  232. /* Protect the field .free, while checking if the mcbsp is in use */
  233. struct omap_mcbsp_platform_data *pdata;
  234. struct omap_mcbsp_st_data *st_data;
  235. struct omap_mcbsp_reg_cfg cfg_regs;
  236. struct snd_dmaengine_dai_dma_data dma_data[2];
  237. unsigned int dma_req[2];
  238. int dma_op_mode;
  239. u16 max_tx_thres;
  240. u16 max_rx_thres;
  241. void *reg_cache;
  242. int reg_cache_size;
  243. unsigned int fmt;
  244. unsigned int in_freq;
  245. unsigned int latency[2];
  246. int clk_div;
  247. int wlen;
  248. struct pm_qos_request pm_qos_req;
  249. };
  250. static inline void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  251. {
  252. void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  253. if (mcbsp->pdata->reg_size == 2) {
  254. ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  255. writew_relaxed((u16)val, addr);
  256. } else {
  257. ((u32 *)mcbsp->reg_cache)[reg] = val;
  258. writel_relaxed(val, addr);
  259. }
  260. }
  261. static inline int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg,
  262. bool from_cache)
  263. {
  264. void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  265. if (mcbsp->pdata->reg_size == 2) {
  266. return !from_cache ? readw_relaxed(addr) :
  267. ((u16 *)mcbsp->reg_cache)[reg];
  268. } else {
  269. return !from_cache ? readl_relaxed(addr) :
  270. ((u32 *)mcbsp->reg_cache)[reg];
  271. }
  272. }
  273. #define MCBSP_READ(mcbsp, reg) \
  274. omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  275. #define MCBSP_WRITE(mcbsp, reg, val) \
  276. omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  277. #define MCBSP_READ_CACHE(mcbsp, reg) \
  278. omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  279. /* Sidetone specific API */
  280. int omap_mcbsp_st_init(struct platform_device *pdev);
  281. void omap_mcbsp_st_cleanup(struct platform_device *pdev);
  282. int omap_mcbsp_st_start(struct omap_mcbsp *mcbsp);
  283. int omap_mcbsp_st_stop(struct omap_mcbsp *mcbsp);
  284. #endif /* __OMAP_MCBSP_PRIV_H__ */