omap-dmic.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  4. *
  5. * Copyright (C) 2010 - 2011 Texas Instruments
  6. *
  7. * Author: David Lambert <dlambert@ti.com>
  8. * Misael Lopez Cruz <misael.lopez@ti.com>
  9. * Liam Girdwood <lrg@ti.com>
  10. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/io.h>
  18. #include <linux/slab.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/of_device.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/initval.h>
  25. #include <sound/soc.h>
  26. #include <sound/dmaengine_pcm.h>
  27. #include "omap-dmic.h"
  28. #include "sdma-pcm.h"
  29. struct omap_dmic {
  30. struct device *dev;
  31. void __iomem *io_base;
  32. struct clk *fclk;
  33. struct pm_qos_request pm_qos_req;
  34. int latency;
  35. int fclk_freq;
  36. int out_freq;
  37. int clk_div;
  38. int sysclk;
  39. int threshold;
  40. u32 ch_enabled;
  41. bool active;
  42. struct mutex mutex;
  43. struct snd_dmaengine_dai_dma_data dma_data;
  44. };
  45. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  46. {
  47. writel_relaxed(val, dmic->io_base + reg);
  48. }
  49. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  50. {
  51. return readl_relaxed(dmic->io_base + reg);
  52. }
  53. static inline void omap_dmic_start(struct omap_dmic *dmic)
  54. {
  55. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  56. /* Configure DMA controller */
  57. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  58. OMAP_DMIC_DMA_ENABLE);
  59. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  60. }
  61. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  62. {
  63. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  64. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  65. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  66. /* Disable DMA request generation */
  67. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  68. OMAP_DMIC_DMA_ENABLE);
  69. }
  70. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  71. {
  72. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  73. OMAP_DMIC_UP_ENABLE_MASK;
  74. }
  75. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  76. struct snd_soc_dai *dai)
  77. {
  78. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  79. int ret = 0;
  80. mutex_lock(&dmic->mutex);
  81. if (!snd_soc_dai_active(dai))
  82. dmic->active = 1;
  83. else
  84. ret = -EBUSY;
  85. mutex_unlock(&dmic->mutex);
  86. return ret;
  87. }
  88. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  89. struct snd_soc_dai *dai)
  90. {
  91. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  92. mutex_lock(&dmic->mutex);
  93. cpu_latency_qos_remove_request(&dmic->pm_qos_req);
  94. if (!snd_soc_dai_active(dai))
  95. dmic->active = 0;
  96. mutex_unlock(&dmic->mutex);
  97. }
  98. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  99. {
  100. int divider = -EINVAL;
  101. /*
  102. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  103. * configuration.
  104. */
  105. if (sample_rate == 192000) {
  106. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  107. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  108. else
  109. dev_err(dmic->dev,
  110. "invalid clock configuration for 192KHz\n");
  111. return divider;
  112. }
  113. switch (dmic->out_freq) {
  114. case 1536000:
  115. if (dmic->fclk_freq != 24576000)
  116. goto div_err;
  117. divider = 0x4; /* Divider: 16 */
  118. break;
  119. case 2400000:
  120. switch (dmic->fclk_freq) {
  121. case 12000000:
  122. divider = 0x5; /* Divider: 5 */
  123. break;
  124. case 19200000:
  125. divider = 0x0; /* Divider: 8 */
  126. break;
  127. case 24000000:
  128. divider = 0x2; /* Divider: 10 */
  129. break;
  130. default:
  131. goto div_err;
  132. }
  133. break;
  134. case 3072000:
  135. if (dmic->fclk_freq != 24576000)
  136. goto div_err;
  137. divider = 0x3; /* Divider: 8 */
  138. break;
  139. case 3840000:
  140. if (dmic->fclk_freq != 19200000)
  141. goto div_err;
  142. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  143. break;
  144. default:
  145. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  146. dmic->out_freq);
  147. break;
  148. }
  149. return divider;
  150. div_err:
  151. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  152. dmic->out_freq, dmic->fclk_freq);
  153. return -EINVAL;
  154. }
  155. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  156. struct snd_pcm_hw_params *params,
  157. struct snd_soc_dai *dai)
  158. {
  159. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  160. struct snd_dmaengine_dai_dma_data *dma_data;
  161. int channels;
  162. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  163. if (dmic->clk_div < 0) {
  164. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  165. dmic->out_freq, dmic->fclk_freq);
  166. return -EINVAL;
  167. }
  168. dmic->ch_enabled = 0;
  169. channels = params_channels(params);
  170. switch (channels) {
  171. case 6:
  172. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  173. fallthrough;
  174. case 4:
  175. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  176. fallthrough;
  177. case 2:
  178. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  179. break;
  180. default:
  181. dev_err(dmic->dev, "invalid number of legacy channels\n");
  182. return -EINVAL;
  183. }
  184. /* packet size is threshold * channels */
  185. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  186. dma_data->maxburst = dmic->threshold * channels;
  187. dmic->latency = (OMAP_DMIC_THRES_MAX - dmic->threshold) * USEC_PER_SEC /
  188. params_rate(params);
  189. return 0;
  190. }
  191. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  192. struct snd_soc_dai *dai)
  193. {
  194. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  195. u32 ctrl;
  196. if (cpu_latency_qos_request_active(&dmic->pm_qos_req))
  197. cpu_latency_qos_update_request(&dmic->pm_qos_req,
  198. dmic->latency);
  199. /* Configure uplink threshold */
  200. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  201. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  202. /* Set dmic out format */
  203. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  204. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  205. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  206. /* Configure dmic clock divider */
  207. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  208. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  209. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  210. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  211. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  212. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  213. return 0;
  214. }
  215. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  216. int cmd, struct snd_soc_dai *dai)
  217. {
  218. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  219. switch (cmd) {
  220. case SNDRV_PCM_TRIGGER_START:
  221. omap_dmic_start(dmic);
  222. break;
  223. case SNDRV_PCM_TRIGGER_STOP:
  224. omap_dmic_stop(dmic);
  225. break;
  226. default:
  227. break;
  228. }
  229. return 0;
  230. }
  231. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  232. unsigned int freq)
  233. {
  234. struct clk *parent_clk, *mux;
  235. char *parent_clk_name;
  236. int ret = 0;
  237. switch (freq) {
  238. case 12000000:
  239. case 19200000:
  240. case 24000000:
  241. case 24576000:
  242. break;
  243. default:
  244. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  245. dmic->fclk_freq = 0;
  246. return -EINVAL;
  247. }
  248. if (dmic->sysclk == clk_id) {
  249. dmic->fclk_freq = freq;
  250. return 0;
  251. }
  252. /* re-parent not allowed if a stream is ongoing */
  253. if (dmic->active && dmic_is_enabled(dmic)) {
  254. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  255. return -EBUSY;
  256. }
  257. switch (clk_id) {
  258. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  259. parent_clk_name = "pad_clks_ck";
  260. break;
  261. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  262. parent_clk_name = "slimbus_clk";
  263. break;
  264. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  265. parent_clk_name = "dmic_sync_mux_ck";
  266. break;
  267. default:
  268. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  269. return -EINVAL;
  270. }
  271. parent_clk = clk_get(dmic->dev, parent_clk_name);
  272. if (IS_ERR(parent_clk)) {
  273. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  274. return -ENODEV;
  275. }
  276. mux = clk_get_parent(dmic->fclk);
  277. if (IS_ERR(mux)) {
  278. dev_err(dmic->dev, "can't get fck mux parent\n");
  279. clk_put(parent_clk);
  280. return -ENODEV;
  281. }
  282. mutex_lock(&dmic->mutex);
  283. if (dmic->active) {
  284. /* disable clock while reparenting */
  285. pm_runtime_put_sync(dmic->dev);
  286. ret = clk_set_parent(mux, parent_clk);
  287. pm_runtime_get_sync(dmic->dev);
  288. } else {
  289. ret = clk_set_parent(mux, parent_clk);
  290. }
  291. mutex_unlock(&dmic->mutex);
  292. if (ret < 0) {
  293. dev_err(dmic->dev, "re-parent failed\n");
  294. goto err_busy;
  295. }
  296. dmic->sysclk = clk_id;
  297. dmic->fclk_freq = freq;
  298. err_busy:
  299. clk_put(mux);
  300. clk_put(parent_clk);
  301. return ret;
  302. }
  303. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  304. unsigned int freq)
  305. {
  306. int ret = 0;
  307. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  308. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  309. clk_id);
  310. return -EINVAL;
  311. }
  312. switch (freq) {
  313. case 1536000:
  314. case 2400000:
  315. case 3072000:
  316. case 3840000:
  317. dmic->out_freq = freq;
  318. break;
  319. default:
  320. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  321. dmic->out_freq = 0;
  322. ret = -EINVAL;
  323. }
  324. return ret;
  325. }
  326. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  327. unsigned int freq, int dir)
  328. {
  329. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  330. if (dir == SND_SOC_CLOCK_IN)
  331. return omap_dmic_select_fclk(dmic, clk_id, freq);
  332. else if (dir == SND_SOC_CLOCK_OUT)
  333. return omap_dmic_select_outclk(dmic, clk_id, freq);
  334. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  335. return -EINVAL;
  336. }
  337. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  338. .startup = omap_dmic_dai_startup,
  339. .shutdown = omap_dmic_dai_shutdown,
  340. .hw_params = omap_dmic_dai_hw_params,
  341. .prepare = omap_dmic_dai_prepare,
  342. .trigger = omap_dmic_dai_trigger,
  343. .set_sysclk = omap_dmic_set_dai_sysclk,
  344. };
  345. static int omap_dmic_probe(struct snd_soc_dai *dai)
  346. {
  347. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  348. pm_runtime_enable(dmic->dev);
  349. /* Disable lines while request is ongoing */
  350. pm_runtime_get_sync(dmic->dev);
  351. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  352. pm_runtime_put_sync(dmic->dev);
  353. /* Configure DMIC threshold value */
  354. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  355. snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
  356. return 0;
  357. }
  358. static int omap_dmic_remove(struct snd_soc_dai *dai)
  359. {
  360. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  361. pm_runtime_disable(dmic->dev);
  362. return 0;
  363. }
  364. static struct snd_soc_dai_driver omap_dmic_dai = {
  365. .name = "omap-dmic",
  366. .probe = omap_dmic_probe,
  367. .remove = omap_dmic_remove,
  368. .capture = {
  369. .channels_min = 2,
  370. .channels_max = 6,
  371. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  372. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  373. .sig_bits = 24,
  374. },
  375. .ops = &omap_dmic_dai_ops,
  376. };
  377. static const struct snd_soc_component_driver omap_dmic_component = {
  378. .name = "omap-dmic",
  379. };
  380. static int asoc_dmic_probe(struct platform_device *pdev)
  381. {
  382. struct omap_dmic *dmic;
  383. struct resource *res;
  384. int ret;
  385. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  386. if (!dmic)
  387. return -ENOMEM;
  388. platform_set_drvdata(pdev, dmic);
  389. dmic->dev = &pdev->dev;
  390. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  391. mutex_init(&dmic->mutex);
  392. dmic->fclk = devm_clk_get(dmic->dev, "fck");
  393. if (IS_ERR(dmic->fclk)) {
  394. dev_err(dmic->dev, "cant get fck\n");
  395. return -ENODEV;
  396. }
  397. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  398. if (!res) {
  399. dev_err(dmic->dev, "invalid dma memory resource\n");
  400. return -ENODEV;
  401. }
  402. dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
  403. dmic->dma_data.filter_data = "up_link";
  404. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  405. dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
  406. if (IS_ERR(dmic->io_base))
  407. return PTR_ERR(dmic->io_base);
  408. ret = devm_snd_soc_register_component(&pdev->dev,
  409. &omap_dmic_component,
  410. &omap_dmic_dai, 1);
  411. if (ret)
  412. return ret;
  413. ret = sdma_pcm_platform_register(&pdev->dev, NULL, "up_link");
  414. if (ret)
  415. return ret;
  416. return 0;
  417. }
  418. static const struct of_device_id omap_dmic_of_match[] = {
  419. { .compatible = "ti,omap4-dmic", },
  420. { }
  421. };
  422. MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
  423. static struct platform_driver asoc_dmic_driver = {
  424. .driver = {
  425. .name = "omap-dmic",
  426. .of_match_table = omap_dmic_of_match,
  427. },
  428. .probe = asoc_dmic_probe,
  429. };
  430. module_platform_driver(asoc_dmic_driver);
  431. MODULE_ALIAS("platform:omap-dmic");
  432. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  433. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  434. MODULE_LICENSE("GPL");