davinci-mcasp.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  4. *
  5. * MCASP related definitions
  6. *
  7. * Author: Nirmal Pandey <n-pandey@ti.com>,
  8. * Suresh Rajashekara <suresh.r@ti.com>
  9. * Steve Chen <schen@.mvista.com>
  10. *
  11. * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
  12. * Copyright: (C) 2009 Texas Instruments, India
  13. */
  14. #ifndef DAVINCI_MCASP_H
  15. #define DAVINCI_MCASP_H
  16. /*
  17. * McASP register definitions
  18. */
  19. #define DAVINCI_MCASP_PID_REG 0x00
  20. #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
  21. #define DAVINCI_MCASP_PFUNC_REG 0x10
  22. #define DAVINCI_MCASP_PDIR_REG 0x14
  23. #define DAVINCI_MCASP_PDOUT_REG 0x18
  24. #define DAVINCI_MCASP_PDSET_REG 0x1c
  25. #define DAVINCI_MCASP_PDCLR_REG 0x20
  26. #define DAVINCI_MCASP_TLGC_REG 0x30
  27. #define DAVINCI_MCASP_TLMR_REG 0x34
  28. #define DAVINCI_MCASP_GBLCTL_REG 0x44
  29. #define DAVINCI_MCASP_AMUTE_REG 0x48
  30. #define DAVINCI_MCASP_LBCTL_REG 0x4c
  31. #define DAVINCI_MCASP_TXDITCTL_REG 0x50
  32. #define DAVINCI_MCASP_GBLCTLR_REG 0x60
  33. #define DAVINCI_MCASP_RXMASK_REG 0x64
  34. #define DAVINCI_MCASP_RXFMT_REG 0x68
  35. #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
  36. #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
  37. #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
  38. #define DAVINCI_MCASP_RXTDM_REG 0x78
  39. #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
  40. #define DAVINCI_MCASP_RXSTAT_REG 0x80
  41. #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
  42. #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
  43. #define DAVINCI_MCASP_REVTCTL_REG 0x8c
  44. #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
  45. #define DAVINCI_MCASP_TXMASK_REG 0xa4
  46. #define DAVINCI_MCASP_TXFMT_REG 0xa8
  47. #define DAVINCI_MCASP_TXFMCTL_REG 0xac
  48. #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
  49. #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
  50. #define DAVINCI_MCASP_TXTDM_REG 0xb8
  51. #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
  52. #define DAVINCI_MCASP_TXSTAT_REG 0xc0
  53. #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
  54. #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
  55. #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
  56. /* Left(even TDM Slot) Channel Status Register File */
  57. #define DAVINCI_MCASP_DITCSRA_REG 0x100
  58. /* Right(odd TDM slot) Channel Status Register File */
  59. #define DAVINCI_MCASP_DITCSRB_REG 0x118
  60. /* Left(even TDM slot) User Data Register File */
  61. #define DAVINCI_MCASP_DITUDRA_REG 0x130
  62. /* Right(odd TDM Slot) User Data Register File */
  63. #define DAVINCI_MCASP_DITUDRB_REG 0x148
  64. /* Serializer n Control Register */
  65. #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
  66. #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
  67. (n << 2))
  68. /* Transmit Buffer for Serializer n */
  69. #define DAVINCI_MCASP_TXBUF_REG(n) (0x200 + (n << 2))
  70. /* Receive Buffer for Serializer n */
  71. #define DAVINCI_MCASP_RXBUF_REG(n) (0x280 + (n << 2))
  72. /* McASP FIFO Registers */
  73. #define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010)
  74. #define DAVINCI_MCASP_V3_AFIFO_BASE (0x1000)
  75. /* FIFO register offsets from AFIFO base */
  76. #define MCASP_WFIFOCTL_OFFSET (0x0)
  77. #define MCASP_WFIFOSTS_OFFSET (0x4)
  78. #define MCASP_RFIFOCTL_OFFSET (0x8)
  79. #define MCASP_RFIFOSTS_OFFSET (0xc)
  80. /*
  81. * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
  82. * Register Bits
  83. */
  84. #define MCASP_FREE BIT(0)
  85. #define MCASP_SOFT BIT(1)
  86. /*
  87. * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
  88. * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
  89. * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
  90. * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
  91. */
  92. #define PIN_BIT_AXR(n) (n)
  93. #define PIN_BIT_AMUTE 25
  94. #define PIN_BIT_ACLKX 26
  95. #define PIN_BIT_AHCLKX 27
  96. #define PIN_BIT_AFSX 28
  97. #define PIN_BIT_ACLKR 29
  98. #define PIN_BIT_AHCLKR 30
  99. #define PIN_BIT_AFSR 31
  100. /*
  101. * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
  102. */
  103. #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
  104. #define VA BIT(2)
  105. #define VB BIT(3)
  106. /*
  107. * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
  108. */
  109. #define TXROT(val) (val)
  110. #define TXSEL BIT(3)
  111. #define TXSSZ(val) (val<<4)
  112. #define TXPBIT(val) (val<<8)
  113. #define TXPAD(val) (val<<13)
  114. #define TXORD BIT(15)
  115. #define FSXDLY(val) (val<<16)
  116. /*
  117. * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
  118. */
  119. #define RXROT(val) (val)
  120. #define RXSEL BIT(3)
  121. #define RXSSZ(val) (val<<4)
  122. #define RXPBIT(val) (val<<8)
  123. #define RXPAD(val) (val<<13)
  124. #define RXORD BIT(15)
  125. #define FSRDLY(val) (val<<16)
  126. /*
  127. * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
  128. */
  129. #define FSXPOL BIT(0)
  130. #define AFSXE BIT(1)
  131. #define FSXDUR BIT(4)
  132. #define FSXMOD(val) (val<<7)
  133. /*
  134. * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
  135. */
  136. #define FSRPOL BIT(0)
  137. #define AFSRE BIT(1)
  138. #define FSRDUR BIT(4)
  139. #define FSRMOD(val) (val<<7)
  140. /*
  141. * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
  142. */
  143. #define ACLKXDIV(val) (val)
  144. #define ACLKXE BIT(5)
  145. #define TX_ASYNC BIT(6)
  146. #define ACLKXPOL BIT(7)
  147. #define ACLKXDIV_MASK 0x1f
  148. /*
  149. * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
  150. */
  151. #define ACLKRDIV(val) (val)
  152. #define ACLKRE BIT(5)
  153. #define RX_ASYNC BIT(6)
  154. #define ACLKRPOL BIT(7)
  155. #define ACLKRDIV_MASK 0x1f
  156. /*
  157. * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
  158. * Register Bits
  159. */
  160. #define AHCLKXDIV(val) (val)
  161. #define AHCLKXPOL BIT(14)
  162. #define AHCLKXE BIT(15)
  163. #define AHCLKXDIV_MASK 0xfff
  164. /*
  165. * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
  166. * Register Bits
  167. */
  168. #define AHCLKRDIV(val) (val)
  169. #define AHCLKRPOL BIT(14)
  170. #define AHCLKRE BIT(15)
  171. #define AHCLKRDIV_MASK 0xfff
  172. /*
  173. * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
  174. */
  175. #define MODE(val) (val)
  176. #define DISMOD_3STATE (0x0)
  177. #define DISMOD_LOW (0x2 << 2)
  178. #define DISMOD_HIGH (0x3 << 2)
  179. #define DISMOD_VAL(x) ((x) << 2)
  180. #define DISMOD_MASK DISMOD_HIGH
  181. #define TXSTATE BIT(4)
  182. #define RXSTATE BIT(5)
  183. #define SRMOD_MASK 3
  184. #define SRMOD_INACTIVE 0
  185. /*
  186. * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
  187. */
  188. #define LBEN BIT(0)
  189. #define LBORD BIT(1)
  190. #define LBGENMODE(val) (val<<2)
  191. /*
  192. * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
  193. */
  194. #define TXTDMS(n) (1<<n)
  195. /*
  196. * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
  197. */
  198. #define RXTDMS(n) (1<<n)
  199. /*
  200. * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
  201. */
  202. #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
  203. #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
  204. #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
  205. #define RXSMRST BIT(3) /* Receiver State Machine Reset */
  206. #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
  207. #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
  208. #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
  209. #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
  210. #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
  211. #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
  212. /*
  213. * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
  214. * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
  215. */
  216. #define XRERR BIT(8) /* Transmit/Receive error */
  217. #define XRDATA BIT(5) /* Transmit/Receive data ready */
  218. /*
  219. * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
  220. */
  221. #define MUTENA(val) (val)
  222. #define MUTEINPOL BIT(2)
  223. #define MUTEINENA BIT(3)
  224. #define MUTEIN BIT(4)
  225. #define MUTER BIT(5)
  226. #define MUTEX BIT(6)
  227. #define MUTEFSR BIT(7)
  228. #define MUTEFSX BIT(8)
  229. #define MUTEBADCLKR BIT(9)
  230. #define MUTEBADCLKX BIT(10)
  231. #define MUTERXDMAERR BIT(11)
  232. #define MUTETXDMAERR BIT(12)
  233. /*
  234. * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
  235. */
  236. #define RXDATADMADIS BIT(0)
  237. /*
  238. * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
  239. */
  240. #define TXDATADMADIS BIT(0)
  241. /*
  242. * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
  243. */
  244. #define ROVRN BIT(0)
  245. /*
  246. * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
  247. */
  248. #define XUNDRN BIT(0)
  249. /*
  250. * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
  251. */
  252. #define FIFO_ENABLE BIT(16)
  253. #define NUMEVT_MASK (0xFF << 8)
  254. #define NUMEVT(x) (((x) & 0xFF) << 8)
  255. #define NUMDMA_MASK (0xFF)
  256. /* Source of High-frequency transmit/receive clock */
  257. #define MCASP_CLK_HCLK_AHCLK 0 /* AHCLKX/R */
  258. #define MCASP_CLK_HCLK_AUXCLK 1 /* Internal functional clock */
  259. /* clock divider IDs */
  260. #define MCASP_CLKDIV_AUXCLK 0 /* HCLK divider from AUXCLK */
  261. #define MCASP_CLKDIV_BCLK 1 /* BCLK divider from HCLK */
  262. #define MCASP_CLKDIV_BCLK_FS_RATIO 2 /* to set BCLK FS ration */
  263. #endif /* DAVINCI_MCASP_H */