davinci-mcasp.c 64 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ALSA SoC McASP Audio Layer for TI DAVINCI processor
  4. *
  5. * Multi-channel Audio Serial Port Driver
  6. *
  7. * Author: Nirmal Pandey <n-pandey@ti.com>,
  8. * Suresh Rajashekara <suresh.r@ti.com>
  9. * Steve Chen <schen@.mvista.com>
  10. *
  11. * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
  12. * Copyright: (C) 2009 Texas Instruments, India
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/device.h>
  17. #include <linux/slab.h>
  18. #include <linux/delay.h>
  19. #include <linux/io.h>
  20. #include <linux/clk.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/of.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/of_device.h>
  25. #include <linux/platform_data/davinci_asp.h>
  26. #include <linux/math64.h>
  27. #include <linux/bitmap.h>
  28. #include <linux/gpio/driver.h>
  29. #include <sound/asoundef.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/initval.h>
  34. #include <sound/soc.h>
  35. #include <sound/dmaengine_pcm.h>
  36. #include "edma-pcm.h"
  37. #include "sdma-pcm.h"
  38. #include "udma-pcm.h"
  39. #include "davinci-mcasp.h"
  40. #define MCASP_MAX_AFIFO_DEPTH 64
  41. #ifdef CONFIG_PM
  42. static u32 context_regs[] = {
  43. DAVINCI_MCASP_TXFMCTL_REG,
  44. DAVINCI_MCASP_RXFMCTL_REG,
  45. DAVINCI_MCASP_TXFMT_REG,
  46. DAVINCI_MCASP_RXFMT_REG,
  47. DAVINCI_MCASP_ACLKXCTL_REG,
  48. DAVINCI_MCASP_ACLKRCTL_REG,
  49. DAVINCI_MCASP_AHCLKXCTL_REG,
  50. DAVINCI_MCASP_AHCLKRCTL_REG,
  51. DAVINCI_MCASP_PDIR_REG,
  52. DAVINCI_MCASP_PFUNC_REG,
  53. DAVINCI_MCASP_RXMASK_REG,
  54. DAVINCI_MCASP_TXMASK_REG,
  55. DAVINCI_MCASP_RXTDM_REG,
  56. DAVINCI_MCASP_TXTDM_REG,
  57. };
  58. struct davinci_mcasp_context {
  59. u32 config_regs[ARRAY_SIZE(context_regs)];
  60. u32 afifo_regs[2]; /* for read/write fifo control registers */
  61. u32 *xrsr_regs; /* for serializer configuration */
  62. bool pm_state;
  63. };
  64. #endif
  65. struct davinci_mcasp_ruledata {
  66. struct davinci_mcasp *mcasp;
  67. int serializers;
  68. };
  69. struct davinci_mcasp {
  70. struct snd_dmaengine_dai_dma_data dma_data[2];
  71. void __iomem *base;
  72. u32 fifo_base;
  73. struct device *dev;
  74. struct snd_pcm_substream *substreams[2];
  75. unsigned int dai_fmt;
  76. /* McASP specific data */
  77. int tdm_slots;
  78. u32 tdm_mask[2];
  79. int slot_width;
  80. u8 op_mode;
  81. u8 dismod;
  82. u8 num_serializer;
  83. u8 *serial_dir;
  84. u8 version;
  85. u8 bclk_div;
  86. int streams;
  87. u32 irq_request[2];
  88. int dma_request[2];
  89. int sysclk_freq;
  90. bool bclk_master;
  91. u32 auxclk_fs_ratio;
  92. unsigned long pdir; /* Pin direction bitfield */
  93. /* McASP FIFO related */
  94. u8 txnumevt;
  95. u8 rxnumevt;
  96. bool dat_port;
  97. /* Used for comstraint setting on the second stream */
  98. u32 channels;
  99. int max_format_width;
  100. u8 active_serializers[2];
  101. #ifdef CONFIG_GPIOLIB
  102. struct gpio_chip gpio_chip;
  103. #endif
  104. #ifdef CONFIG_PM
  105. struct davinci_mcasp_context context;
  106. #endif
  107. struct davinci_mcasp_ruledata ruledata[2];
  108. struct snd_pcm_hw_constraint_list chconstr[2];
  109. };
  110. static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
  111. u32 val)
  112. {
  113. void __iomem *reg = mcasp->base + offset;
  114. __raw_writel(__raw_readl(reg) | val, reg);
  115. }
  116. static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
  117. u32 val)
  118. {
  119. void __iomem *reg = mcasp->base + offset;
  120. __raw_writel((__raw_readl(reg) & ~(val)), reg);
  121. }
  122. static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
  123. u32 val, u32 mask)
  124. {
  125. void __iomem *reg = mcasp->base + offset;
  126. __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
  127. }
  128. static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
  129. u32 val)
  130. {
  131. __raw_writel(val, mcasp->base + offset);
  132. }
  133. static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
  134. {
  135. return (u32)__raw_readl(mcasp->base + offset);
  136. }
  137. static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
  138. {
  139. int i = 0;
  140. mcasp_set_bits(mcasp, ctl_reg, val);
  141. /* programming GBLCTL needs to read back from GBLCTL and verfiy */
  142. /* loop count is to avoid the lock-up */
  143. for (i = 0; i < 1000; i++) {
  144. if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
  145. break;
  146. }
  147. if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
  148. printk(KERN_ERR "GBLCTL write error\n");
  149. }
  150. static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
  151. {
  152. u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
  153. u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
  154. return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
  155. }
  156. static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
  157. {
  158. u32 bit = PIN_BIT_AMUTE;
  159. for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
  160. if (enable)
  161. mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
  162. else
  163. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
  164. }
  165. }
  166. static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
  167. {
  168. u32 bit;
  169. for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
  170. if (enable)
  171. mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
  172. else
  173. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
  174. }
  175. }
  176. static void mcasp_start_rx(struct davinci_mcasp *mcasp)
  177. {
  178. if (mcasp->rxnumevt) { /* enable FIFO */
  179. u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
  180. mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
  181. mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
  182. }
  183. /* Start clocks */
  184. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
  185. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
  186. /*
  187. * When ASYNC == 0 the transmit and receive sections operate
  188. * synchronously from the transmit clock and frame sync. We need to make
  189. * sure that the TX signlas are enabled when starting reception.
  190. */
  191. if (mcasp_is_synchronous(mcasp)) {
  192. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
  193. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
  194. mcasp_set_clk_pdir(mcasp, true);
  195. }
  196. /* Activate serializer(s) */
  197. mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
  198. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
  199. /* Release RX state machine */
  200. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
  201. /* Release Frame Sync generator */
  202. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
  203. if (mcasp_is_synchronous(mcasp))
  204. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
  205. /* enable receive IRQs */
  206. mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
  207. mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
  208. }
  209. static void mcasp_start_tx(struct davinci_mcasp *mcasp)
  210. {
  211. u32 cnt;
  212. if (mcasp->txnumevt) { /* enable FIFO */
  213. u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
  214. mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
  215. mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
  216. }
  217. /* Start clocks */
  218. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
  219. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
  220. mcasp_set_clk_pdir(mcasp, true);
  221. /* Activate serializer(s) */
  222. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
  223. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
  224. /* wait for XDATA to be cleared */
  225. cnt = 0;
  226. while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
  227. (cnt < 100000))
  228. cnt++;
  229. mcasp_set_axr_pdir(mcasp, true);
  230. /* Release TX state machine */
  231. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
  232. /* Release Frame Sync generator */
  233. mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
  234. /* enable transmit IRQs */
  235. mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
  236. mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
  237. }
  238. static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
  239. {
  240. mcasp->streams++;
  241. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  242. mcasp_start_tx(mcasp);
  243. else
  244. mcasp_start_rx(mcasp);
  245. }
  246. static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
  247. {
  248. /* disable IRQ sources */
  249. mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
  250. mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
  251. /*
  252. * In synchronous mode stop the TX clocks if no other stream is
  253. * running
  254. */
  255. if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
  256. mcasp_set_clk_pdir(mcasp, false);
  257. mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
  258. }
  259. mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
  260. mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
  261. if (mcasp->rxnumevt) { /* disable FIFO */
  262. u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
  263. mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
  264. }
  265. }
  266. static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
  267. {
  268. u32 val = 0;
  269. /* disable IRQ sources */
  270. mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
  271. mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
  272. /*
  273. * In synchronous mode keep TX clocks running if the capture stream is
  274. * still running.
  275. */
  276. if (mcasp_is_synchronous(mcasp) && mcasp->streams)
  277. val = TXHCLKRST | TXCLKRST | TXFSRST;
  278. else
  279. mcasp_set_clk_pdir(mcasp, false);
  280. mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
  281. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
  282. if (mcasp->txnumevt) { /* disable FIFO */
  283. u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
  284. mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
  285. }
  286. mcasp_set_axr_pdir(mcasp, false);
  287. }
  288. static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
  289. {
  290. mcasp->streams--;
  291. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  292. mcasp_stop_tx(mcasp);
  293. else
  294. mcasp_stop_rx(mcasp);
  295. }
  296. static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
  297. {
  298. struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
  299. struct snd_pcm_substream *substream;
  300. u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
  301. u32 handled_mask = 0;
  302. u32 stat;
  303. stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
  304. if (stat & XUNDRN & irq_mask) {
  305. dev_warn(mcasp->dev, "Transmit buffer underflow\n");
  306. handled_mask |= XUNDRN;
  307. substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
  308. if (substream)
  309. snd_pcm_stop_xrun(substream);
  310. }
  311. if (!handled_mask)
  312. dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
  313. stat);
  314. if (stat & XRERR)
  315. handled_mask |= XRERR;
  316. /* Ack the handled event only */
  317. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
  318. return IRQ_RETVAL(handled_mask);
  319. }
  320. static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
  321. {
  322. struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
  323. struct snd_pcm_substream *substream;
  324. u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
  325. u32 handled_mask = 0;
  326. u32 stat;
  327. stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
  328. if (stat & ROVRN & irq_mask) {
  329. dev_warn(mcasp->dev, "Receive buffer overflow\n");
  330. handled_mask |= ROVRN;
  331. substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
  332. if (substream)
  333. snd_pcm_stop_xrun(substream);
  334. }
  335. if (!handled_mask)
  336. dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
  337. stat);
  338. if (stat & XRERR)
  339. handled_mask |= XRERR;
  340. /* Ack the handled event only */
  341. mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
  342. return IRQ_RETVAL(handled_mask);
  343. }
  344. static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
  345. {
  346. struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
  347. irqreturn_t ret = IRQ_NONE;
  348. if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
  349. ret = davinci_mcasp_tx_irq_handler(irq, data);
  350. if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
  351. ret |= davinci_mcasp_rx_irq_handler(irq, data);
  352. return ret;
  353. }
  354. static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  355. unsigned int fmt)
  356. {
  357. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
  358. int ret = 0;
  359. u32 data_delay;
  360. bool fs_pol_rising;
  361. bool inv_fs = false;
  362. if (!fmt)
  363. return 0;
  364. pm_runtime_get_sync(mcasp->dev);
  365. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  366. case SND_SOC_DAIFMT_DSP_A:
  367. mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
  368. mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
  369. /* 1st data bit occur one ACLK cycle after the frame sync */
  370. data_delay = 1;
  371. break;
  372. case SND_SOC_DAIFMT_DSP_B:
  373. case SND_SOC_DAIFMT_AC97:
  374. mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
  375. mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
  376. /* No delay after FS */
  377. data_delay = 0;
  378. break;
  379. case SND_SOC_DAIFMT_I2S:
  380. /* configure a full-word SYNC pulse (LRCLK) */
  381. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
  382. mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
  383. /* 1st data bit occur one ACLK cycle after the frame sync */
  384. data_delay = 1;
  385. /* FS need to be inverted */
  386. inv_fs = true;
  387. break;
  388. case SND_SOC_DAIFMT_RIGHT_J:
  389. case SND_SOC_DAIFMT_LEFT_J:
  390. /* configure a full-word SYNC pulse (LRCLK) */
  391. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
  392. mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
  393. /* No delay after FS */
  394. data_delay = 0;
  395. break;
  396. default:
  397. ret = -EINVAL;
  398. goto out;
  399. }
  400. mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
  401. FSXDLY(3));
  402. mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
  403. FSRDLY(3));
  404. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  405. case SND_SOC_DAIFMT_CBS_CFS:
  406. /* codec is clock and frame slave */
  407. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  408. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  409. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  410. mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  411. /* BCLK */
  412. set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
  413. set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
  414. /* Frame Sync */
  415. set_bit(PIN_BIT_AFSX, &mcasp->pdir);
  416. set_bit(PIN_BIT_AFSR, &mcasp->pdir);
  417. mcasp->bclk_master = 1;
  418. break;
  419. case SND_SOC_DAIFMT_CBS_CFM:
  420. /* codec is clock slave and frame master */
  421. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  422. mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  423. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  424. mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  425. /* BCLK */
  426. set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
  427. set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
  428. /* Frame Sync */
  429. clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
  430. clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
  431. mcasp->bclk_master = 1;
  432. break;
  433. case SND_SOC_DAIFMT_CBM_CFS:
  434. /* codec is clock master and frame slave */
  435. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  436. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  437. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  438. mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  439. /* BCLK */
  440. clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
  441. clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
  442. /* Frame Sync */
  443. set_bit(PIN_BIT_AFSX, &mcasp->pdir);
  444. set_bit(PIN_BIT_AFSR, &mcasp->pdir);
  445. mcasp->bclk_master = 0;
  446. break;
  447. case SND_SOC_DAIFMT_CBM_CFM:
  448. /* codec is clock and frame master */
  449. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
  450. mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
  451. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
  452. mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
  453. /* BCLK */
  454. clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
  455. clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
  456. /* Frame Sync */
  457. clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
  458. clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
  459. mcasp->bclk_master = 0;
  460. break;
  461. default:
  462. ret = -EINVAL;
  463. goto out;
  464. }
  465. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  466. case SND_SOC_DAIFMT_IB_NF:
  467. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  468. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  469. fs_pol_rising = true;
  470. break;
  471. case SND_SOC_DAIFMT_NB_IF:
  472. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  473. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  474. fs_pol_rising = false;
  475. break;
  476. case SND_SOC_DAIFMT_IB_IF:
  477. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  478. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  479. fs_pol_rising = false;
  480. break;
  481. case SND_SOC_DAIFMT_NB_NF:
  482. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
  483. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
  484. fs_pol_rising = true;
  485. break;
  486. default:
  487. ret = -EINVAL;
  488. goto out;
  489. }
  490. if (inv_fs)
  491. fs_pol_rising = !fs_pol_rising;
  492. if (fs_pol_rising) {
  493. mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
  494. mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
  495. } else {
  496. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
  497. mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
  498. }
  499. mcasp->dai_fmt = fmt;
  500. out:
  501. pm_runtime_put(mcasp->dev);
  502. return ret;
  503. }
  504. static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
  505. int div, bool explicit)
  506. {
  507. pm_runtime_get_sync(mcasp->dev);
  508. switch (div_id) {
  509. case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
  510. mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
  511. AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
  512. mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
  513. AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
  514. break;
  515. case MCASP_CLKDIV_BCLK: /* BCLK divider */
  516. mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
  517. ACLKXDIV(div - 1), ACLKXDIV_MASK);
  518. mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
  519. ACLKRDIV(div - 1), ACLKRDIV_MASK);
  520. if (explicit)
  521. mcasp->bclk_div = div;
  522. break;
  523. case MCASP_CLKDIV_BCLK_FS_RATIO:
  524. /*
  525. * BCLK/LRCLK ratio descries how many bit-clock cycles
  526. * fit into one frame. The clock ratio is given for a
  527. * full period of data (for I2S format both left and
  528. * right channels), so it has to be divided by number
  529. * of tdm-slots (for I2S - divided by 2).
  530. * Instead of storing this ratio, we calculate a new
  531. * tdm_slot width by dividing the ratio by the
  532. * number of configured tdm slots.
  533. */
  534. mcasp->slot_width = div / mcasp->tdm_slots;
  535. if (div % mcasp->tdm_slots)
  536. dev_warn(mcasp->dev,
  537. "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
  538. __func__, div, mcasp->tdm_slots);
  539. break;
  540. default:
  541. return -EINVAL;
  542. }
  543. pm_runtime_put(mcasp->dev);
  544. return 0;
  545. }
  546. static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
  547. int div)
  548. {
  549. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
  550. return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
  551. }
  552. static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  553. unsigned int freq, int dir)
  554. {
  555. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
  556. pm_runtime_get_sync(mcasp->dev);
  557. if (dir == SND_SOC_CLOCK_IN) {
  558. switch (clk_id) {
  559. case MCASP_CLK_HCLK_AHCLK:
  560. mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
  561. AHCLKXE);
  562. mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
  563. AHCLKRE);
  564. clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
  565. break;
  566. case MCASP_CLK_HCLK_AUXCLK:
  567. mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
  568. AHCLKXE);
  569. mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
  570. AHCLKRE);
  571. set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
  572. break;
  573. default:
  574. dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
  575. goto out;
  576. }
  577. } else {
  578. /* Select AUXCLK as HCLK */
  579. mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
  580. mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
  581. set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
  582. }
  583. /*
  584. * When AHCLK X/R is selected to be output it means that the HCLK is
  585. * the same clock - coming via AUXCLK.
  586. */
  587. mcasp->sysclk_freq = freq;
  588. out:
  589. pm_runtime_put(mcasp->dev);
  590. return 0;
  591. }
  592. /* All serializers must have equal number of channels */
  593. static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
  594. int serializers)
  595. {
  596. struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
  597. unsigned int *list = (unsigned int *) cl->list;
  598. int slots = mcasp->tdm_slots;
  599. int i, count = 0;
  600. if (mcasp->tdm_mask[stream])
  601. slots = hweight32(mcasp->tdm_mask[stream]);
  602. for (i = 1; i <= slots; i++)
  603. list[count++] = i;
  604. for (i = 2; i <= serializers; i++)
  605. list[count++] = i*slots;
  606. cl->count = count;
  607. return 0;
  608. }
  609. static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
  610. {
  611. int rx_serializers = 0, tx_serializers = 0, ret, i;
  612. for (i = 0; i < mcasp->num_serializer; i++)
  613. if (mcasp->serial_dir[i] == TX_MODE)
  614. tx_serializers++;
  615. else if (mcasp->serial_dir[i] == RX_MODE)
  616. rx_serializers++;
  617. ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
  618. tx_serializers);
  619. if (ret)
  620. return ret;
  621. ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
  622. rx_serializers);
  623. return ret;
  624. }
  625. static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
  626. unsigned int tx_mask,
  627. unsigned int rx_mask,
  628. int slots, int slot_width)
  629. {
  630. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
  631. dev_dbg(mcasp->dev,
  632. "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
  633. __func__, tx_mask, rx_mask, slots, slot_width);
  634. if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
  635. dev_err(mcasp->dev,
  636. "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
  637. tx_mask, rx_mask, slots);
  638. return -EINVAL;
  639. }
  640. if (slot_width &&
  641. (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
  642. dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
  643. __func__, slot_width);
  644. return -EINVAL;
  645. }
  646. mcasp->tdm_slots = slots;
  647. mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
  648. mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
  649. mcasp->slot_width = slot_width;
  650. return davinci_mcasp_set_ch_constraints(mcasp);
  651. }
  652. static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
  653. int sample_width)
  654. {
  655. u32 fmt;
  656. u32 tx_rotate, rx_rotate, slot_width;
  657. u32 mask = (1ULL << sample_width) - 1;
  658. if (mcasp->slot_width)
  659. slot_width = mcasp->slot_width;
  660. else if (mcasp->max_format_width)
  661. slot_width = mcasp->max_format_width;
  662. else
  663. slot_width = sample_width;
  664. /*
  665. * TX rotation:
  666. * right aligned formats: rotate w/ slot_width
  667. * left aligned formats: rotate w/ sample_width
  668. *
  669. * RX rotation:
  670. * right aligned formats: no rotation needed
  671. * left aligned formats: rotate w/ (slot_width - sample_width)
  672. */
  673. if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
  674. SND_SOC_DAIFMT_RIGHT_J) {
  675. tx_rotate = (slot_width / 4) & 0x7;
  676. rx_rotate = 0;
  677. } else {
  678. tx_rotate = (sample_width / 4) & 0x7;
  679. rx_rotate = (slot_width - sample_width) / 4;
  680. }
  681. /* mapping of the XSSZ bit-field as described in the datasheet */
  682. fmt = (slot_width >> 1) - 1;
  683. if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
  684. mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
  685. RXSSZ(0x0F));
  686. mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
  687. TXSSZ(0x0F));
  688. mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
  689. TXROT(7));
  690. mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
  691. RXROT(7));
  692. mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
  693. }
  694. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
  695. return 0;
  696. }
  697. static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
  698. int period_words, int channels)
  699. {
  700. struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
  701. int i;
  702. u8 tx_ser = 0;
  703. u8 rx_ser = 0;
  704. u8 slots = mcasp->tdm_slots;
  705. u8 max_active_serializers = (channels + slots - 1) / slots;
  706. u8 max_rx_serializers, max_tx_serializers;
  707. int active_serializers, numevt;
  708. u32 reg;
  709. /* Default configuration */
  710. if (mcasp->version < MCASP_VERSION_3)
  711. mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
  712. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  713. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
  714. mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
  715. max_tx_serializers = max_active_serializers;
  716. max_rx_serializers =
  717. mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
  718. } else {
  719. mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
  720. mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
  721. max_tx_serializers =
  722. mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
  723. max_rx_serializers = max_active_serializers;
  724. }
  725. for (i = 0; i < mcasp->num_serializer; i++) {
  726. mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
  727. mcasp->serial_dir[i]);
  728. if (mcasp->serial_dir[i] == TX_MODE &&
  729. tx_ser < max_tx_serializers) {
  730. mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
  731. mcasp->dismod, DISMOD_MASK);
  732. set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
  733. tx_ser++;
  734. } else if (mcasp->serial_dir[i] == RX_MODE &&
  735. rx_ser < max_rx_serializers) {
  736. clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
  737. rx_ser++;
  738. } else {
  739. /* Inactive or unused pin, set it to inactive */
  740. mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
  741. SRMOD_INACTIVE, SRMOD_MASK);
  742. /* If unused, set DISMOD for the pin */
  743. if (mcasp->serial_dir[i] != INACTIVE_MODE)
  744. mcasp_mod_bits(mcasp,
  745. DAVINCI_MCASP_XRSRCTL_REG(i),
  746. mcasp->dismod, DISMOD_MASK);
  747. clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
  748. }
  749. }
  750. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  751. active_serializers = tx_ser;
  752. numevt = mcasp->txnumevt;
  753. reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
  754. } else {
  755. active_serializers = rx_ser;
  756. numevt = mcasp->rxnumevt;
  757. reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
  758. }
  759. if (active_serializers < max_active_serializers) {
  760. dev_warn(mcasp->dev, "stream has more channels (%d) than are "
  761. "enabled in mcasp (%d)\n", channels,
  762. active_serializers * slots);
  763. return -EINVAL;
  764. }
  765. /* AFIFO is not in use */
  766. if (!numevt) {
  767. /* Configure the burst size for platform drivers */
  768. if (active_serializers > 1) {
  769. /*
  770. * If more than one serializers are in use we have one
  771. * DMA request to provide data for all serializers.
  772. * For example if three serializers are enabled the DMA
  773. * need to transfer three words per DMA request.
  774. */
  775. dma_data->maxburst = active_serializers;
  776. } else {
  777. dma_data->maxburst = 0;
  778. }
  779. goto out;
  780. }
  781. if (period_words % active_serializers) {
  782. dev_err(mcasp->dev, "Invalid combination of period words and "
  783. "active serializers: %d, %d\n", period_words,
  784. active_serializers);
  785. return -EINVAL;
  786. }
  787. /*
  788. * Calculate the optimal AFIFO depth for platform side:
  789. * The number of words for numevt need to be in steps of active
  790. * serializers.
  791. */
  792. numevt = (numevt / active_serializers) * active_serializers;
  793. while (period_words % numevt && numevt > 0)
  794. numevt -= active_serializers;
  795. if (numevt <= 0)
  796. numevt = active_serializers;
  797. mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
  798. mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
  799. /* Configure the burst size for platform drivers */
  800. if (numevt == 1)
  801. numevt = 0;
  802. dma_data->maxburst = numevt;
  803. out:
  804. mcasp->active_serializers[stream] = active_serializers;
  805. return 0;
  806. }
  807. static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
  808. int channels)
  809. {
  810. int i, active_slots;
  811. int total_slots;
  812. int active_serializers;
  813. u32 mask = 0;
  814. u32 busel = 0;
  815. total_slots = mcasp->tdm_slots;
  816. /*
  817. * If more than one serializer is needed, then use them with
  818. * all the specified tdm_slots. Otherwise, one serializer can
  819. * cope with the transaction using just as many slots as there
  820. * are channels in the stream.
  821. */
  822. if (mcasp->tdm_mask[stream]) {
  823. active_slots = hweight32(mcasp->tdm_mask[stream]);
  824. active_serializers = (channels + active_slots - 1) /
  825. active_slots;
  826. if (active_serializers == 1)
  827. active_slots = channels;
  828. for (i = 0; i < total_slots; i++) {
  829. if ((1 << i) & mcasp->tdm_mask[stream]) {
  830. mask |= (1 << i);
  831. if (--active_slots <= 0)
  832. break;
  833. }
  834. }
  835. } else {
  836. active_serializers = (channels + total_slots - 1) / total_slots;
  837. if (active_serializers == 1)
  838. active_slots = channels;
  839. else
  840. active_slots = total_slots;
  841. for (i = 0; i < active_slots; i++)
  842. mask |= (1 << i);
  843. }
  844. mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
  845. if (!mcasp->dat_port)
  846. busel = TXSEL;
  847. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  848. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
  849. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
  850. mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
  851. FSXMOD(total_slots), FSXMOD(0x1FF));
  852. } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
  853. mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
  854. mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
  855. mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
  856. FSRMOD(total_slots), FSRMOD(0x1FF));
  857. /*
  858. * If McASP is set to be TX/RX synchronous and the playback is
  859. * not running already we need to configure the TX slots in
  860. * order to have correct FSX on the bus
  861. */
  862. if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
  863. mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
  864. FSXMOD(total_slots), FSXMOD(0x1FF));
  865. }
  866. return 0;
  867. }
  868. /* S/PDIF */
  869. static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
  870. unsigned int rate)
  871. {
  872. u32 cs_value = 0;
  873. u8 *cs_bytes = (u8*) &cs_value;
  874. /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
  875. and LSB first */
  876. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
  877. /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
  878. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
  879. /* Set the TX tdm : for all the slots */
  880. mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
  881. /* Set the TX clock controls : div = 1 and internal */
  882. mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
  883. mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
  884. /* Only 44100 and 48000 are valid, both have the same setting */
  885. mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
  886. /* Enable the DIT */
  887. mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
  888. /* Set S/PDIF channel status bits */
  889. cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
  890. cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
  891. switch (rate) {
  892. case 22050:
  893. cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
  894. break;
  895. case 24000:
  896. cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
  897. break;
  898. case 32000:
  899. cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
  900. break;
  901. case 44100:
  902. cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
  903. break;
  904. case 48000:
  905. cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
  906. break;
  907. case 88200:
  908. cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
  909. break;
  910. case 96000:
  911. cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
  912. break;
  913. case 176400:
  914. cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
  915. break;
  916. case 192000:
  917. cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
  918. break;
  919. default:
  920. printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
  921. return -EINVAL;
  922. }
  923. mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
  924. mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
  925. return 0;
  926. }
  927. static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
  928. unsigned int sysclk_freq,
  929. unsigned int bclk_freq, bool set)
  930. {
  931. u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
  932. int div = sysclk_freq / bclk_freq;
  933. int rem = sysclk_freq % bclk_freq;
  934. int error_ppm;
  935. int aux_div = 1;
  936. if (div > (ACLKXDIV_MASK + 1)) {
  937. if (reg & AHCLKXE) {
  938. aux_div = div / (ACLKXDIV_MASK + 1);
  939. if (div % (ACLKXDIV_MASK + 1))
  940. aux_div++;
  941. sysclk_freq /= aux_div;
  942. div = sysclk_freq / bclk_freq;
  943. rem = sysclk_freq % bclk_freq;
  944. } else if (set) {
  945. dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
  946. sysclk_freq);
  947. }
  948. }
  949. if (rem != 0) {
  950. if (div == 0 ||
  951. ((sysclk_freq / div) - bclk_freq) >
  952. (bclk_freq - (sysclk_freq / (div+1)))) {
  953. div++;
  954. rem = rem - bclk_freq;
  955. }
  956. }
  957. error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
  958. (int)bclk_freq)) / div - 1000000;
  959. if (set) {
  960. if (error_ppm)
  961. dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
  962. error_ppm);
  963. __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
  964. if (reg & AHCLKXE)
  965. __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
  966. aux_div, 0);
  967. }
  968. return error_ppm;
  969. }
  970. static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
  971. {
  972. if (!mcasp->txnumevt)
  973. return 0;
  974. return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
  975. }
  976. static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
  977. {
  978. if (!mcasp->rxnumevt)
  979. return 0;
  980. return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
  981. }
  982. static snd_pcm_sframes_t davinci_mcasp_delay(
  983. struct snd_pcm_substream *substream,
  984. struct snd_soc_dai *cpu_dai)
  985. {
  986. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
  987. u32 fifo_use;
  988. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  989. fifo_use = davinci_mcasp_tx_delay(mcasp);
  990. else
  991. fifo_use = davinci_mcasp_rx_delay(mcasp);
  992. /*
  993. * Divide the used locations with the channel count to get the
  994. * FIFO usage in samples (don't care about partial samples in the
  995. * buffer).
  996. */
  997. return fifo_use / substream->runtime->channels;
  998. }
  999. static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
  1000. struct snd_pcm_hw_params *params,
  1001. struct snd_soc_dai *cpu_dai)
  1002. {
  1003. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
  1004. int word_length;
  1005. int channels = params_channels(params);
  1006. int period_size = params_period_size(params);
  1007. int ret;
  1008. switch (params_format(params)) {
  1009. case SNDRV_PCM_FORMAT_U8:
  1010. case SNDRV_PCM_FORMAT_S8:
  1011. word_length = 8;
  1012. break;
  1013. case SNDRV_PCM_FORMAT_U16_LE:
  1014. case SNDRV_PCM_FORMAT_S16_LE:
  1015. word_length = 16;
  1016. break;
  1017. case SNDRV_PCM_FORMAT_U24_3LE:
  1018. case SNDRV_PCM_FORMAT_S24_3LE:
  1019. word_length = 24;
  1020. break;
  1021. case SNDRV_PCM_FORMAT_U24_LE:
  1022. case SNDRV_PCM_FORMAT_S24_LE:
  1023. word_length = 24;
  1024. break;
  1025. case SNDRV_PCM_FORMAT_U32_LE:
  1026. case SNDRV_PCM_FORMAT_S32_LE:
  1027. word_length = 32;
  1028. break;
  1029. default:
  1030. printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
  1031. return -EINVAL;
  1032. }
  1033. ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
  1034. if (ret)
  1035. return ret;
  1036. /*
  1037. * If mcasp is BCLK master, and a BCLK divider was not provided by
  1038. * the machine driver, we need to calculate the ratio.
  1039. */
  1040. if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
  1041. int slots = mcasp->tdm_slots;
  1042. int rate = params_rate(params);
  1043. int sbits = params_width(params);
  1044. if (mcasp->slot_width)
  1045. sbits = mcasp->slot_width;
  1046. davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
  1047. rate * sbits * slots, true);
  1048. }
  1049. ret = mcasp_common_hw_param(mcasp, substream->stream,
  1050. period_size * channels, channels);
  1051. if (ret)
  1052. return ret;
  1053. if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
  1054. ret = mcasp_dit_hw_param(mcasp, params_rate(params));
  1055. else
  1056. ret = mcasp_i2s_hw_param(mcasp, substream->stream,
  1057. channels);
  1058. if (ret)
  1059. return ret;
  1060. davinci_config_channel_size(mcasp, word_length);
  1061. if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
  1062. mcasp->channels = channels;
  1063. if (!mcasp->max_format_width)
  1064. mcasp->max_format_width = word_length;
  1065. }
  1066. return 0;
  1067. }
  1068. static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
  1069. int cmd, struct snd_soc_dai *cpu_dai)
  1070. {
  1071. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
  1072. int ret = 0;
  1073. switch (cmd) {
  1074. case SNDRV_PCM_TRIGGER_RESUME:
  1075. case SNDRV_PCM_TRIGGER_START:
  1076. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1077. davinci_mcasp_start(mcasp, substream->stream);
  1078. break;
  1079. case SNDRV_PCM_TRIGGER_SUSPEND:
  1080. case SNDRV_PCM_TRIGGER_STOP:
  1081. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1082. davinci_mcasp_stop(mcasp, substream->stream);
  1083. break;
  1084. default:
  1085. ret = -EINVAL;
  1086. }
  1087. return ret;
  1088. }
  1089. static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
  1090. struct snd_pcm_hw_rule *rule)
  1091. {
  1092. struct davinci_mcasp_ruledata *rd = rule->private;
  1093. struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
  1094. struct snd_mask nfmt;
  1095. int i, slot_width;
  1096. snd_mask_none(&nfmt);
  1097. slot_width = rd->mcasp->slot_width;
  1098. for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
  1099. if (snd_mask_test(fmt, i)) {
  1100. if (snd_pcm_format_width(i) <= slot_width) {
  1101. snd_mask_set(&nfmt, i);
  1102. }
  1103. }
  1104. }
  1105. return snd_mask_refine(fmt, &nfmt);
  1106. }
  1107. static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
  1108. struct snd_pcm_hw_rule *rule)
  1109. {
  1110. struct davinci_mcasp_ruledata *rd = rule->private;
  1111. struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
  1112. struct snd_mask nfmt;
  1113. int i, format_width;
  1114. snd_mask_none(&nfmt);
  1115. format_width = rd->mcasp->max_format_width;
  1116. for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
  1117. if (snd_mask_test(fmt, i)) {
  1118. if (snd_pcm_format_width(i) == format_width) {
  1119. snd_mask_set(&nfmt, i);
  1120. }
  1121. }
  1122. }
  1123. return snd_mask_refine(fmt, &nfmt);
  1124. }
  1125. static const unsigned int davinci_mcasp_dai_rates[] = {
  1126. 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
  1127. 88200, 96000, 176400, 192000,
  1128. };
  1129. #define DAVINCI_MAX_RATE_ERROR_PPM 1000
  1130. static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
  1131. struct snd_pcm_hw_rule *rule)
  1132. {
  1133. struct davinci_mcasp_ruledata *rd = rule->private;
  1134. struct snd_interval *ri =
  1135. hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
  1136. int sbits = params_width(params);
  1137. int slots = rd->mcasp->tdm_slots;
  1138. struct snd_interval range;
  1139. int i;
  1140. if (rd->mcasp->slot_width)
  1141. sbits = rd->mcasp->slot_width;
  1142. snd_interval_any(&range);
  1143. range.empty = 1;
  1144. for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
  1145. if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
  1146. uint bclk_freq = sbits * slots *
  1147. davinci_mcasp_dai_rates[i];
  1148. unsigned int sysclk_freq;
  1149. int ppm;
  1150. if (rd->mcasp->auxclk_fs_ratio)
  1151. sysclk_freq = davinci_mcasp_dai_rates[i] *
  1152. rd->mcasp->auxclk_fs_ratio;
  1153. else
  1154. sysclk_freq = rd->mcasp->sysclk_freq;
  1155. ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
  1156. bclk_freq, false);
  1157. if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
  1158. if (range.empty) {
  1159. range.min = davinci_mcasp_dai_rates[i];
  1160. range.empty = 0;
  1161. }
  1162. range.max = davinci_mcasp_dai_rates[i];
  1163. }
  1164. }
  1165. }
  1166. dev_dbg(rd->mcasp->dev,
  1167. "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
  1168. ri->min, ri->max, range.min, range.max, sbits, slots);
  1169. return snd_interval_refine(hw_param_interval(params, rule->var),
  1170. &range);
  1171. }
  1172. static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
  1173. struct snd_pcm_hw_rule *rule)
  1174. {
  1175. struct davinci_mcasp_ruledata *rd = rule->private;
  1176. struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
  1177. struct snd_mask nfmt;
  1178. int rate = params_rate(params);
  1179. int slots = rd->mcasp->tdm_slots;
  1180. int i, count = 0;
  1181. snd_mask_none(&nfmt);
  1182. for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
  1183. if (snd_mask_test(fmt, i)) {
  1184. uint sbits = snd_pcm_format_width(i);
  1185. unsigned int sysclk_freq;
  1186. int ppm;
  1187. if (rd->mcasp->auxclk_fs_ratio)
  1188. sysclk_freq = rate *
  1189. rd->mcasp->auxclk_fs_ratio;
  1190. else
  1191. sysclk_freq = rd->mcasp->sysclk_freq;
  1192. if (rd->mcasp->slot_width)
  1193. sbits = rd->mcasp->slot_width;
  1194. ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
  1195. sbits * slots * rate,
  1196. false);
  1197. if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
  1198. snd_mask_set(&nfmt, i);
  1199. count++;
  1200. }
  1201. }
  1202. }
  1203. dev_dbg(rd->mcasp->dev,
  1204. "%d possible sample format for %d Hz and %d tdm slots\n",
  1205. count, rate, slots);
  1206. return snd_mask_refine(fmt, &nfmt);
  1207. }
  1208. static int davinci_mcasp_hw_rule_min_periodsize(
  1209. struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
  1210. {
  1211. struct snd_interval *period_size = hw_param_interval(params,
  1212. SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
  1213. struct snd_interval frames;
  1214. snd_interval_any(&frames);
  1215. frames.min = 64;
  1216. frames.integer = 1;
  1217. return snd_interval_refine(period_size, &frames);
  1218. }
  1219. static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
  1220. struct snd_soc_dai *cpu_dai)
  1221. {
  1222. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
  1223. struct davinci_mcasp_ruledata *ruledata =
  1224. &mcasp->ruledata[substream->stream];
  1225. u32 max_channels = 0;
  1226. int i, dir, ret;
  1227. int tdm_slots = mcasp->tdm_slots;
  1228. /* Do not allow more then one stream per direction */
  1229. if (mcasp->substreams[substream->stream])
  1230. return -EBUSY;
  1231. mcasp->substreams[substream->stream] = substream;
  1232. if (mcasp->tdm_mask[substream->stream])
  1233. tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
  1234. if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
  1235. return 0;
  1236. /*
  1237. * Limit the maximum allowed channels for the first stream:
  1238. * number of serializers for the direction * tdm slots per serializer
  1239. */
  1240. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  1241. dir = TX_MODE;
  1242. else
  1243. dir = RX_MODE;
  1244. for (i = 0; i < mcasp->num_serializer; i++) {
  1245. if (mcasp->serial_dir[i] == dir)
  1246. max_channels++;
  1247. }
  1248. ruledata->serializers = max_channels;
  1249. ruledata->mcasp = mcasp;
  1250. max_channels *= tdm_slots;
  1251. /*
  1252. * If the already active stream has less channels than the calculated
  1253. * limit based on the seirializers * tdm_slots, and only one serializer
  1254. * is in use we need to use that as a constraint for the second stream.
  1255. * Otherwise (first stream or less allowed channels or more than one
  1256. * serializer in use) we use the calculated constraint.
  1257. */
  1258. if (mcasp->channels && mcasp->channels < max_channels &&
  1259. ruledata->serializers == 1)
  1260. max_channels = mcasp->channels;
  1261. /*
  1262. * But we can always allow channels upto the amount of
  1263. * the available tdm_slots.
  1264. */
  1265. if (max_channels < tdm_slots)
  1266. max_channels = tdm_slots;
  1267. snd_pcm_hw_constraint_minmax(substream->runtime,
  1268. SNDRV_PCM_HW_PARAM_CHANNELS,
  1269. 0, max_channels);
  1270. snd_pcm_hw_constraint_list(substream->runtime,
  1271. 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1272. &mcasp->chconstr[substream->stream]);
  1273. if (mcasp->max_format_width) {
  1274. /*
  1275. * Only allow formats which require same amount of bits on the
  1276. * bus as the currently running stream
  1277. */
  1278. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  1279. SNDRV_PCM_HW_PARAM_FORMAT,
  1280. davinci_mcasp_hw_rule_format_width,
  1281. ruledata,
  1282. SNDRV_PCM_HW_PARAM_FORMAT, -1);
  1283. if (ret)
  1284. return ret;
  1285. }
  1286. else if (mcasp->slot_width) {
  1287. /* Only allow formats require <= slot_width bits on the bus */
  1288. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  1289. SNDRV_PCM_HW_PARAM_FORMAT,
  1290. davinci_mcasp_hw_rule_slot_width,
  1291. ruledata,
  1292. SNDRV_PCM_HW_PARAM_FORMAT, -1);
  1293. if (ret)
  1294. return ret;
  1295. }
  1296. /*
  1297. * If we rely on implicit BCLK divider setting we should
  1298. * set constraints based on what we can provide.
  1299. */
  1300. if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
  1301. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  1302. SNDRV_PCM_HW_PARAM_RATE,
  1303. davinci_mcasp_hw_rule_rate,
  1304. ruledata,
  1305. SNDRV_PCM_HW_PARAM_FORMAT, -1);
  1306. if (ret)
  1307. return ret;
  1308. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  1309. SNDRV_PCM_HW_PARAM_FORMAT,
  1310. davinci_mcasp_hw_rule_format,
  1311. ruledata,
  1312. SNDRV_PCM_HW_PARAM_RATE, -1);
  1313. if (ret)
  1314. return ret;
  1315. }
  1316. snd_pcm_hw_rule_add(substream->runtime, 0,
  1317. SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
  1318. davinci_mcasp_hw_rule_min_periodsize, NULL,
  1319. SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
  1320. return 0;
  1321. }
  1322. static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
  1323. struct snd_soc_dai *cpu_dai)
  1324. {
  1325. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
  1326. mcasp->substreams[substream->stream] = NULL;
  1327. mcasp->active_serializers[substream->stream] = 0;
  1328. if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
  1329. return;
  1330. if (!snd_soc_dai_active(cpu_dai)) {
  1331. mcasp->channels = 0;
  1332. mcasp->max_format_width = 0;
  1333. }
  1334. }
  1335. static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
  1336. .startup = davinci_mcasp_startup,
  1337. .shutdown = davinci_mcasp_shutdown,
  1338. .trigger = davinci_mcasp_trigger,
  1339. .delay = davinci_mcasp_delay,
  1340. .hw_params = davinci_mcasp_hw_params,
  1341. .set_fmt = davinci_mcasp_set_dai_fmt,
  1342. .set_clkdiv = davinci_mcasp_set_clkdiv,
  1343. .set_sysclk = davinci_mcasp_set_sysclk,
  1344. .set_tdm_slot = davinci_mcasp_set_tdm_slot,
  1345. };
  1346. static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
  1347. {
  1348. struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
  1349. dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
  1350. dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
  1351. return 0;
  1352. }
  1353. #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
  1354. #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
  1355. SNDRV_PCM_FMTBIT_U8 | \
  1356. SNDRV_PCM_FMTBIT_S16_LE | \
  1357. SNDRV_PCM_FMTBIT_U16_LE | \
  1358. SNDRV_PCM_FMTBIT_S24_LE | \
  1359. SNDRV_PCM_FMTBIT_U24_LE | \
  1360. SNDRV_PCM_FMTBIT_S24_3LE | \
  1361. SNDRV_PCM_FMTBIT_U24_3LE | \
  1362. SNDRV_PCM_FMTBIT_S32_LE | \
  1363. SNDRV_PCM_FMTBIT_U32_LE)
  1364. static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
  1365. {
  1366. .name = "davinci-mcasp.0",
  1367. .probe = davinci_mcasp_dai_probe,
  1368. .playback = {
  1369. .stream_name = "IIS Playback",
  1370. .channels_min = 1,
  1371. .channels_max = 32 * 16,
  1372. .rates = DAVINCI_MCASP_RATES,
  1373. .formats = DAVINCI_MCASP_PCM_FMTS,
  1374. },
  1375. .capture = {
  1376. .stream_name = "IIS Capture",
  1377. .channels_min = 1,
  1378. .channels_max = 32 * 16,
  1379. .rates = DAVINCI_MCASP_RATES,
  1380. .formats = DAVINCI_MCASP_PCM_FMTS,
  1381. },
  1382. .ops = &davinci_mcasp_dai_ops,
  1383. .symmetric_rates = 1,
  1384. },
  1385. {
  1386. .name = "davinci-mcasp.1",
  1387. .probe = davinci_mcasp_dai_probe,
  1388. .playback = {
  1389. .stream_name = "DIT Playback",
  1390. .channels_min = 1,
  1391. .channels_max = 384,
  1392. .rates = DAVINCI_MCASP_RATES,
  1393. .formats = DAVINCI_MCASP_PCM_FMTS,
  1394. },
  1395. .ops = &davinci_mcasp_dai_ops,
  1396. },
  1397. };
  1398. static const struct snd_soc_component_driver davinci_mcasp_component = {
  1399. .name = "davinci-mcasp",
  1400. };
  1401. /* Some HW specific values and defaults. The rest is filled in from DT. */
  1402. static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
  1403. .tx_dma_offset = 0x400,
  1404. .rx_dma_offset = 0x400,
  1405. .version = MCASP_VERSION_1,
  1406. };
  1407. static struct davinci_mcasp_pdata da830_mcasp_pdata = {
  1408. .tx_dma_offset = 0x2000,
  1409. .rx_dma_offset = 0x2000,
  1410. .version = MCASP_VERSION_2,
  1411. };
  1412. static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
  1413. .tx_dma_offset = 0,
  1414. .rx_dma_offset = 0,
  1415. .version = MCASP_VERSION_3,
  1416. };
  1417. static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
  1418. /* The CFG port offset will be calculated if it is needed */
  1419. .tx_dma_offset = 0,
  1420. .rx_dma_offset = 0,
  1421. .version = MCASP_VERSION_4,
  1422. };
  1423. static const struct of_device_id mcasp_dt_ids[] = {
  1424. {
  1425. .compatible = "ti,dm646x-mcasp-audio",
  1426. .data = &dm646x_mcasp_pdata,
  1427. },
  1428. {
  1429. .compatible = "ti,da830-mcasp-audio",
  1430. .data = &da830_mcasp_pdata,
  1431. },
  1432. {
  1433. .compatible = "ti,am33xx-mcasp-audio",
  1434. .data = &am33xx_mcasp_pdata,
  1435. },
  1436. {
  1437. .compatible = "ti,dra7-mcasp-audio",
  1438. .data = &dra7_mcasp_pdata,
  1439. },
  1440. { /* sentinel */ }
  1441. };
  1442. MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
  1443. static int mcasp_reparent_fck(struct platform_device *pdev)
  1444. {
  1445. struct device_node *node = pdev->dev.of_node;
  1446. struct clk *gfclk, *parent_clk;
  1447. const char *parent_name;
  1448. int ret;
  1449. if (!node)
  1450. return 0;
  1451. parent_name = of_get_property(node, "fck_parent", NULL);
  1452. if (!parent_name)
  1453. return 0;
  1454. dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
  1455. gfclk = clk_get(&pdev->dev, "fck");
  1456. if (IS_ERR(gfclk)) {
  1457. dev_err(&pdev->dev, "failed to get fck\n");
  1458. return PTR_ERR(gfclk);
  1459. }
  1460. parent_clk = clk_get(NULL, parent_name);
  1461. if (IS_ERR(parent_clk)) {
  1462. dev_err(&pdev->dev, "failed to get parent clock\n");
  1463. ret = PTR_ERR(parent_clk);
  1464. goto err1;
  1465. }
  1466. ret = clk_set_parent(gfclk, parent_clk);
  1467. if (ret) {
  1468. dev_err(&pdev->dev, "failed to reparent fck\n");
  1469. goto err2;
  1470. }
  1471. err2:
  1472. clk_put(parent_clk);
  1473. err1:
  1474. clk_put(gfclk);
  1475. return ret;
  1476. }
  1477. static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
  1478. struct platform_device *pdev)
  1479. {
  1480. struct device_node *np = pdev->dev.of_node;
  1481. struct davinci_mcasp_pdata *pdata = NULL;
  1482. const struct of_device_id *match =
  1483. of_match_device(mcasp_dt_ids, &pdev->dev);
  1484. struct of_phandle_args dma_spec;
  1485. const u32 *of_serial_dir32;
  1486. u32 val;
  1487. int i, ret = 0;
  1488. if (pdev->dev.platform_data) {
  1489. pdata = pdev->dev.platform_data;
  1490. pdata->dismod = DISMOD_LOW;
  1491. return pdata;
  1492. } else if (match) {
  1493. pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
  1494. GFP_KERNEL);
  1495. if (!pdata)
  1496. return NULL;
  1497. } else {
  1498. /* control shouldn't reach here. something is wrong */
  1499. ret = -EINVAL;
  1500. goto nodata;
  1501. }
  1502. ret = of_property_read_u32(np, "op-mode", &val);
  1503. if (ret >= 0)
  1504. pdata->op_mode = val;
  1505. ret = of_property_read_u32(np, "tdm-slots", &val);
  1506. if (ret >= 0) {
  1507. if (val < 2 || val > 32) {
  1508. dev_err(&pdev->dev,
  1509. "tdm-slots must be in rage [2-32]\n");
  1510. ret = -EINVAL;
  1511. goto nodata;
  1512. }
  1513. pdata->tdm_slots = val;
  1514. }
  1515. of_serial_dir32 = of_get_property(np, "serial-dir", &val);
  1516. val /= sizeof(u32);
  1517. if (of_serial_dir32) {
  1518. u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
  1519. (sizeof(*of_serial_dir) * val),
  1520. GFP_KERNEL);
  1521. if (!of_serial_dir) {
  1522. ret = -ENOMEM;
  1523. goto nodata;
  1524. }
  1525. for (i = 0; i < val; i++)
  1526. of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
  1527. pdata->num_serializer = val;
  1528. pdata->serial_dir = of_serial_dir;
  1529. }
  1530. ret = of_property_match_string(np, "dma-names", "tx");
  1531. if (ret < 0)
  1532. goto nodata;
  1533. ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
  1534. &dma_spec);
  1535. if (ret < 0)
  1536. goto nodata;
  1537. pdata->tx_dma_channel = dma_spec.args[0];
  1538. /* RX is not valid in DIT mode */
  1539. if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
  1540. ret = of_property_match_string(np, "dma-names", "rx");
  1541. if (ret < 0)
  1542. goto nodata;
  1543. ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
  1544. &dma_spec);
  1545. if (ret < 0)
  1546. goto nodata;
  1547. pdata->rx_dma_channel = dma_spec.args[0];
  1548. }
  1549. ret = of_property_read_u32(np, "tx-num-evt", &val);
  1550. if (ret >= 0)
  1551. pdata->txnumevt = val;
  1552. ret = of_property_read_u32(np, "rx-num-evt", &val);
  1553. if (ret >= 0)
  1554. pdata->rxnumevt = val;
  1555. ret = of_property_read_u32(np, "sram-size-playback", &val);
  1556. if (ret >= 0)
  1557. pdata->sram_size_playback = val;
  1558. ret = of_property_read_u32(np, "sram-size-capture", &val);
  1559. if (ret >= 0)
  1560. pdata->sram_size_capture = val;
  1561. ret = of_property_read_u32(np, "dismod", &val);
  1562. if (ret >= 0) {
  1563. if (val == 0 || val == 2 || val == 3) {
  1564. pdata->dismod = DISMOD_VAL(val);
  1565. } else {
  1566. dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
  1567. pdata->dismod = DISMOD_LOW;
  1568. }
  1569. } else {
  1570. pdata->dismod = DISMOD_LOW;
  1571. }
  1572. return pdata;
  1573. nodata:
  1574. if (ret < 0) {
  1575. dev_err(&pdev->dev, "Error populating platform data, err %d\n",
  1576. ret);
  1577. pdata = NULL;
  1578. }
  1579. return pdata;
  1580. }
  1581. enum {
  1582. PCM_EDMA,
  1583. PCM_SDMA,
  1584. PCM_UDMA,
  1585. };
  1586. static const char *sdma_prefix = "ti,omap";
  1587. static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
  1588. {
  1589. struct dma_chan *chan;
  1590. const char *tmp;
  1591. int ret = PCM_EDMA;
  1592. if (!mcasp->dev->of_node)
  1593. return PCM_EDMA;
  1594. tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
  1595. chan = dma_request_chan(mcasp->dev, tmp);
  1596. if (IS_ERR(chan)) {
  1597. if (PTR_ERR(chan) != -EPROBE_DEFER)
  1598. dev_err(mcasp->dev,
  1599. "Can't verify DMA configuration (%ld)\n",
  1600. PTR_ERR(chan));
  1601. return PTR_ERR(chan);
  1602. }
  1603. if (WARN_ON(!chan->device || !chan->device->dev)) {
  1604. dma_release_channel(chan);
  1605. return -EINVAL;
  1606. }
  1607. if (chan->device->dev->of_node)
  1608. ret = of_property_read_string(chan->device->dev->of_node,
  1609. "compatible", &tmp);
  1610. else
  1611. dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
  1612. dma_release_channel(chan);
  1613. if (ret)
  1614. return ret;
  1615. dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
  1616. if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
  1617. return PCM_SDMA;
  1618. else if (strstr(tmp, "udmap"))
  1619. return PCM_UDMA;
  1620. return PCM_EDMA;
  1621. }
  1622. static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
  1623. {
  1624. int i;
  1625. u32 offset = 0;
  1626. if (pdata->version != MCASP_VERSION_4)
  1627. return pdata->tx_dma_offset;
  1628. for (i = 0; i < pdata->num_serializer; i++) {
  1629. if (pdata->serial_dir[i] == TX_MODE) {
  1630. if (!offset) {
  1631. offset = DAVINCI_MCASP_TXBUF_REG(i);
  1632. } else {
  1633. pr_err("%s: Only one serializer allowed!\n",
  1634. __func__);
  1635. break;
  1636. }
  1637. }
  1638. }
  1639. return offset;
  1640. }
  1641. static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
  1642. {
  1643. int i;
  1644. u32 offset = 0;
  1645. if (pdata->version != MCASP_VERSION_4)
  1646. return pdata->rx_dma_offset;
  1647. for (i = 0; i < pdata->num_serializer; i++) {
  1648. if (pdata->serial_dir[i] == RX_MODE) {
  1649. if (!offset) {
  1650. offset = DAVINCI_MCASP_RXBUF_REG(i);
  1651. } else {
  1652. pr_err("%s: Only one serializer allowed!\n",
  1653. __func__);
  1654. break;
  1655. }
  1656. }
  1657. }
  1658. return offset;
  1659. }
  1660. #ifdef CONFIG_GPIOLIB
  1661. static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
  1662. {
  1663. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1664. if (mcasp->num_serializer && offset < mcasp->num_serializer &&
  1665. mcasp->serial_dir[offset] != INACTIVE_MODE) {
  1666. dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
  1667. return -EBUSY;
  1668. }
  1669. /* Do not change the PIN yet */
  1670. return pm_runtime_get_sync(mcasp->dev);
  1671. }
  1672. static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
  1673. {
  1674. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1675. /* Set the direction to input */
  1676. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
  1677. /* Set the pin as McASP pin */
  1678. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
  1679. pm_runtime_put_sync(mcasp->dev);
  1680. }
  1681. static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
  1682. unsigned offset, int value)
  1683. {
  1684. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1685. u32 val;
  1686. if (value)
  1687. mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
  1688. else
  1689. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
  1690. val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
  1691. if (!(val & BIT(offset))) {
  1692. /* Set the pin as GPIO pin */
  1693. mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
  1694. /* Set the direction to output */
  1695. mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
  1696. }
  1697. return 0;
  1698. }
  1699. static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
  1700. int value)
  1701. {
  1702. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1703. if (value)
  1704. mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
  1705. else
  1706. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
  1707. }
  1708. static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
  1709. unsigned offset)
  1710. {
  1711. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1712. u32 val;
  1713. val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
  1714. if (!(val & BIT(offset))) {
  1715. /* Set the direction to input */
  1716. mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
  1717. /* Set the pin as GPIO pin */
  1718. mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
  1719. }
  1720. return 0;
  1721. }
  1722. static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
  1723. {
  1724. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1725. u32 val;
  1726. val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
  1727. if (val & BIT(offset))
  1728. return 1;
  1729. return 0;
  1730. }
  1731. static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
  1732. unsigned offset)
  1733. {
  1734. struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
  1735. u32 val;
  1736. val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
  1737. if (val & BIT(offset))
  1738. return 0;
  1739. return 1;
  1740. }
  1741. static const struct gpio_chip davinci_mcasp_template_chip = {
  1742. .owner = THIS_MODULE,
  1743. .request = davinci_mcasp_gpio_request,
  1744. .free = davinci_mcasp_gpio_free,
  1745. .direction_output = davinci_mcasp_gpio_direction_out,
  1746. .set = davinci_mcasp_gpio_set,
  1747. .direction_input = davinci_mcasp_gpio_direction_in,
  1748. .get = davinci_mcasp_gpio_get,
  1749. .get_direction = davinci_mcasp_gpio_get_direction,
  1750. .base = -1,
  1751. .ngpio = 32,
  1752. };
  1753. static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
  1754. {
  1755. if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
  1756. return 0;
  1757. mcasp->gpio_chip = davinci_mcasp_template_chip;
  1758. mcasp->gpio_chip.label = dev_name(mcasp->dev);
  1759. mcasp->gpio_chip.parent = mcasp->dev;
  1760. #ifdef CONFIG_OF_GPIO
  1761. mcasp->gpio_chip.of_node = mcasp->dev->of_node;
  1762. #endif
  1763. return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
  1764. }
  1765. #else /* CONFIG_GPIOLIB */
  1766. static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
  1767. {
  1768. return 0;
  1769. }
  1770. #endif /* CONFIG_GPIOLIB */
  1771. static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
  1772. {
  1773. struct device_node *np = mcasp->dev->of_node;
  1774. int ret;
  1775. u32 val;
  1776. if (!np)
  1777. return 0;
  1778. ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
  1779. if (ret >= 0)
  1780. mcasp->auxclk_fs_ratio = val;
  1781. return 0;
  1782. }
  1783. static int davinci_mcasp_probe(struct platform_device *pdev)
  1784. {
  1785. struct snd_dmaengine_dai_dma_data *dma_data;
  1786. struct resource *mem, *res, *dat;
  1787. struct davinci_mcasp_pdata *pdata;
  1788. struct davinci_mcasp *mcasp;
  1789. char *irq_name;
  1790. int *dma;
  1791. int irq;
  1792. int ret;
  1793. if (!pdev->dev.platform_data && !pdev->dev.of_node) {
  1794. dev_err(&pdev->dev, "No platform data supplied\n");
  1795. return -EINVAL;
  1796. }
  1797. mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
  1798. GFP_KERNEL);
  1799. if (!mcasp)
  1800. return -ENOMEM;
  1801. pdata = davinci_mcasp_set_pdata_from_of(pdev);
  1802. if (!pdata) {
  1803. dev_err(&pdev->dev, "no platform data\n");
  1804. return -EINVAL;
  1805. }
  1806. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  1807. if (!mem) {
  1808. dev_warn(&pdev->dev,
  1809. "\"mpu\" mem resource not found, using index 0\n");
  1810. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1811. if (!mem) {
  1812. dev_err(&pdev->dev, "no mem resource?\n");
  1813. return -ENODEV;
  1814. }
  1815. }
  1816. mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
  1817. if (IS_ERR(mcasp->base))
  1818. return PTR_ERR(mcasp->base);
  1819. pm_runtime_enable(&pdev->dev);
  1820. mcasp->op_mode = pdata->op_mode;
  1821. /* sanity check for tdm slots parameter */
  1822. if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
  1823. if (pdata->tdm_slots < 2) {
  1824. dev_err(&pdev->dev, "invalid tdm slots: %d\n",
  1825. pdata->tdm_slots);
  1826. mcasp->tdm_slots = 2;
  1827. } else if (pdata->tdm_slots > 32) {
  1828. dev_err(&pdev->dev, "invalid tdm slots: %d\n",
  1829. pdata->tdm_slots);
  1830. mcasp->tdm_slots = 32;
  1831. } else {
  1832. mcasp->tdm_slots = pdata->tdm_slots;
  1833. }
  1834. }
  1835. mcasp->num_serializer = pdata->num_serializer;
  1836. #ifdef CONFIG_PM
  1837. mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
  1838. mcasp->num_serializer, sizeof(u32),
  1839. GFP_KERNEL);
  1840. if (!mcasp->context.xrsr_regs) {
  1841. ret = -ENOMEM;
  1842. goto err;
  1843. }
  1844. #endif
  1845. mcasp->serial_dir = pdata->serial_dir;
  1846. mcasp->version = pdata->version;
  1847. mcasp->txnumevt = pdata->txnumevt;
  1848. mcasp->rxnumevt = pdata->rxnumevt;
  1849. mcasp->dismod = pdata->dismod;
  1850. mcasp->dev = &pdev->dev;
  1851. irq = platform_get_irq_byname(pdev, "common");
  1852. if (irq >= 0) {
  1853. irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
  1854. dev_name(&pdev->dev));
  1855. if (!irq_name) {
  1856. ret = -ENOMEM;
  1857. goto err;
  1858. }
  1859. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  1860. davinci_mcasp_common_irq_handler,
  1861. IRQF_ONESHOT | IRQF_SHARED,
  1862. irq_name, mcasp);
  1863. if (ret) {
  1864. dev_err(&pdev->dev, "common IRQ request failed\n");
  1865. goto err;
  1866. }
  1867. mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
  1868. mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
  1869. }
  1870. irq = platform_get_irq_byname(pdev, "rx");
  1871. if (irq >= 0) {
  1872. irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
  1873. dev_name(&pdev->dev));
  1874. if (!irq_name) {
  1875. ret = -ENOMEM;
  1876. goto err;
  1877. }
  1878. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  1879. davinci_mcasp_rx_irq_handler,
  1880. IRQF_ONESHOT, irq_name, mcasp);
  1881. if (ret) {
  1882. dev_err(&pdev->dev, "RX IRQ request failed\n");
  1883. goto err;
  1884. }
  1885. mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
  1886. }
  1887. irq = platform_get_irq_byname(pdev, "tx");
  1888. if (irq >= 0) {
  1889. irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
  1890. dev_name(&pdev->dev));
  1891. if (!irq_name) {
  1892. ret = -ENOMEM;
  1893. goto err;
  1894. }
  1895. ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  1896. davinci_mcasp_tx_irq_handler,
  1897. IRQF_ONESHOT, irq_name, mcasp);
  1898. if (ret) {
  1899. dev_err(&pdev->dev, "TX IRQ request failed\n");
  1900. goto err;
  1901. }
  1902. mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
  1903. }
  1904. dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
  1905. if (dat)
  1906. mcasp->dat_port = true;
  1907. dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
  1908. if (dat)
  1909. dma_data->addr = dat->start;
  1910. else
  1911. dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
  1912. dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
  1913. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  1914. if (res)
  1915. *dma = res->start;
  1916. else
  1917. *dma = pdata->tx_dma_channel;
  1918. /* dmaengine filter data for DT and non-DT boot */
  1919. if (pdev->dev.of_node)
  1920. dma_data->filter_data = "tx";
  1921. else
  1922. dma_data->filter_data = dma;
  1923. /* RX is not valid in DIT mode */
  1924. if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
  1925. dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
  1926. if (dat)
  1927. dma_data->addr = dat->start;
  1928. else
  1929. dma_data->addr =
  1930. mem->start + davinci_mcasp_rxdma_offset(pdata);
  1931. dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
  1932. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  1933. if (res)
  1934. *dma = res->start;
  1935. else
  1936. *dma = pdata->rx_dma_channel;
  1937. /* dmaengine filter data for DT and non-DT boot */
  1938. if (pdev->dev.of_node)
  1939. dma_data->filter_data = "rx";
  1940. else
  1941. dma_data->filter_data = dma;
  1942. }
  1943. if (mcasp->version < MCASP_VERSION_3) {
  1944. mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
  1945. /* dma_params->dma_addr is pointing to the data port address */
  1946. mcasp->dat_port = true;
  1947. } else {
  1948. mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
  1949. }
  1950. /* Allocate memory for long enough list for all possible
  1951. * scenarios. Maximum number tdm slots is 32 and there cannot
  1952. * be more serializers than given in the configuration. The
  1953. * serializer directions could be taken into account, but it
  1954. * would make code much more complex and save only couple of
  1955. * bytes.
  1956. */
  1957. mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
  1958. devm_kcalloc(mcasp->dev,
  1959. 32 + mcasp->num_serializer - 1,
  1960. sizeof(unsigned int),
  1961. GFP_KERNEL);
  1962. mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
  1963. devm_kcalloc(mcasp->dev,
  1964. 32 + mcasp->num_serializer - 1,
  1965. sizeof(unsigned int),
  1966. GFP_KERNEL);
  1967. if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
  1968. !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
  1969. ret = -ENOMEM;
  1970. goto err;
  1971. }
  1972. ret = davinci_mcasp_set_ch_constraints(mcasp);
  1973. if (ret)
  1974. goto err;
  1975. dev_set_drvdata(&pdev->dev, mcasp);
  1976. mcasp_reparent_fck(pdev);
  1977. /* All PINS as McASP */
  1978. pm_runtime_get_sync(mcasp->dev);
  1979. mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
  1980. pm_runtime_put(mcasp->dev);
  1981. ret = davinci_mcasp_init_gpiochip(mcasp);
  1982. if (ret)
  1983. goto err;
  1984. ret = davinci_mcasp_get_dt_params(mcasp);
  1985. if (ret)
  1986. return -EINVAL;
  1987. ret = devm_snd_soc_register_component(&pdev->dev,
  1988. &davinci_mcasp_component,
  1989. &davinci_mcasp_dai[pdata->op_mode], 1);
  1990. if (ret != 0)
  1991. goto err;
  1992. ret = davinci_mcasp_get_dma_type(mcasp);
  1993. switch (ret) {
  1994. case PCM_EDMA:
  1995. ret = edma_pcm_platform_register(&pdev->dev);
  1996. break;
  1997. case PCM_SDMA:
  1998. ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
  1999. break;
  2000. case PCM_UDMA:
  2001. ret = udma_pcm_platform_register(&pdev->dev);
  2002. break;
  2003. default:
  2004. dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
  2005. case -EPROBE_DEFER:
  2006. goto err;
  2007. break;
  2008. }
  2009. if (ret) {
  2010. dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
  2011. goto err;
  2012. }
  2013. return 0;
  2014. err:
  2015. pm_runtime_disable(&pdev->dev);
  2016. return ret;
  2017. }
  2018. static int davinci_mcasp_remove(struct platform_device *pdev)
  2019. {
  2020. pm_runtime_disable(&pdev->dev);
  2021. return 0;
  2022. }
  2023. #ifdef CONFIG_PM
  2024. static int davinci_mcasp_runtime_suspend(struct device *dev)
  2025. {
  2026. struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
  2027. struct davinci_mcasp_context *context = &mcasp->context;
  2028. u32 reg;
  2029. int i;
  2030. for (i = 0; i < ARRAY_SIZE(context_regs); i++)
  2031. context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
  2032. if (mcasp->txnumevt) {
  2033. reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
  2034. context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
  2035. }
  2036. if (mcasp->rxnumevt) {
  2037. reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
  2038. context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
  2039. }
  2040. for (i = 0; i < mcasp->num_serializer; i++)
  2041. context->xrsr_regs[i] = mcasp_get_reg(mcasp,
  2042. DAVINCI_MCASP_XRSRCTL_REG(i));
  2043. return 0;
  2044. }
  2045. static int davinci_mcasp_runtime_resume(struct device *dev)
  2046. {
  2047. struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
  2048. struct davinci_mcasp_context *context = &mcasp->context;
  2049. u32 reg;
  2050. int i;
  2051. for (i = 0; i < ARRAY_SIZE(context_regs); i++)
  2052. mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
  2053. if (mcasp->txnumevt) {
  2054. reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
  2055. mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
  2056. }
  2057. if (mcasp->rxnumevt) {
  2058. reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
  2059. mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
  2060. }
  2061. for (i = 0; i < mcasp->num_serializer; i++)
  2062. mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
  2063. context->xrsr_regs[i]);
  2064. return 0;
  2065. }
  2066. #endif
  2067. static const struct dev_pm_ops davinci_mcasp_pm_ops = {
  2068. SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
  2069. davinci_mcasp_runtime_resume,
  2070. NULL)
  2071. };
  2072. static struct platform_driver davinci_mcasp_driver = {
  2073. .probe = davinci_mcasp_probe,
  2074. .remove = davinci_mcasp_remove,
  2075. .driver = {
  2076. .name = "davinci-mcasp",
  2077. .pm = &davinci_mcasp_pm_ops,
  2078. .of_match_table = mcasp_dt_ids,
  2079. },
  2080. };
  2081. module_platform_driver(davinci_mcasp_driver);
  2082. MODULE_AUTHOR("Steve Chen");
  2083. MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
  2084. MODULE_LICENSE("GPL");