davinci-i2s.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
  4. *
  5. * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
  6. * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  7. *
  8. * DT support (c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
  9. * based on davinci-mcasp.c DT support
  10. *
  11. * TODO:
  12. * on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/device.h>
  17. #include <linux/slab.h>
  18. #include <linux/delay.h>
  19. #include <linux/io.h>
  20. #include <linux/clk.h>
  21. #include <linux/platform_data/davinci_asp.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/initval.h>
  26. #include <sound/soc.h>
  27. #include <sound/dmaengine_pcm.h>
  28. #include "edma-pcm.h"
  29. #include "davinci-i2s.h"
  30. #define DRV_NAME "davinci-i2s"
  31. /*
  32. * NOTE: terminology here is confusing.
  33. *
  34. * - This driver supports the "Audio Serial Port" (ASP),
  35. * found on dm6446, dm355, and other DaVinci chips.
  36. *
  37. * - But it labels it a "Multi-channel Buffered Serial Port"
  38. * (McBSP) as on older chips like the dm642 ... which was
  39. * backward-compatible, possibly explaining that confusion.
  40. *
  41. * - OMAP chips have a controller called McBSP, which is
  42. * incompatible with the DaVinci flavor of McBSP.
  43. *
  44. * - Newer DaVinci chips have a controller called McASP,
  45. * incompatible with ASP and with either McBSP.
  46. *
  47. * In short: this uses ASP to implement I2S, not McBSP.
  48. * And it won't be the only DaVinci implemention of I2S.
  49. */
  50. #define DAVINCI_MCBSP_DRR_REG 0x00
  51. #define DAVINCI_MCBSP_DXR_REG 0x04
  52. #define DAVINCI_MCBSP_SPCR_REG 0x08
  53. #define DAVINCI_MCBSP_RCR_REG 0x0c
  54. #define DAVINCI_MCBSP_XCR_REG 0x10
  55. #define DAVINCI_MCBSP_SRGR_REG 0x14
  56. #define DAVINCI_MCBSP_PCR_REG 0x24
  57. #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
  58. #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
  59. #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
  60. #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
  61. #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
  62. #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
  63. #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
  64. #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
  65. #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
  66. #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
  67. #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
  68. #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
  69. #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
  70. #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
  71. #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
  72. #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
  73. #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
  74. #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
  75. #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
  76. #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
  77. #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
  78. #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
  79. #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
  80. #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
  81. #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
  82. #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
  83. #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
  84. #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
  85. #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
  86. #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
  87. #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
  88. #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
  89. #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
  90. #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
  91. enum {
  92. DAVINCI_MCBSP_WORD_8 = 0,
  93. DAVINCI_MCBSP_WORD_12,
  94. DAVINCI_MCBSP_WORD_16,
  95. DAVINCI_MCBSP_WORD_20,
  96. DAVINCI_MCBSP_WORD_24,
  97. DAVINCI_MCBSP_WORD_32,
  98. };
  99. static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
  100. [SNDRV_PCM_FORMAT_S8] = 1,
  101. [SNDRV_PCM_FORMAT_S16_LE] = 2,
  102. [SNDRV_PCM_FORMAT_S32_LE] = 4,
  103. };
  104. static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
  105. [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
  106. [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
  107. [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
  108. };
  109. static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
  110. [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
  111. [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
  112. };
  113. struct davinci_mcbsp_dev {
  114. struct device *dev;
  115. struct snd_dmaengine_dai_dma_data dma_data[2];
  116. int dma_request[2];
  117. void __iomem *base;
  118. #define MOD_DSP_A 0
  119. #define MOD_DSP_B 1
  120. int mode;
  121. u32 pcr;
  122. struct clk *clk;
  123. /*
  124. * Combining both channels into 1 element will at least double the
  125. * amount of time between servicing the dma channel, increase
  126. * effiency, and reduce the chance of overrun/underrun. But,
  127. * it will result in the left & right channels being swapped.
  128. *
  129. * If relabeling the left and right channels is not possible,
  130. * you may want to let the codec know to swap them back.
  131. *
  132. * It may allow x10 the amount of time to service dma requests,
  133. * if the codec is master and is using an unnecessarily fast bit clock
  134. * (ie. tlvaic23b), independent of the sample rate. So, having an
  135. * entire frame at once means it can be serviced at the sample rate
  136. * instead of the bit clock rate.
  137. *
  138. * In the now unlikely case that an underrun still
  139. * occurs, both the left and right samples will be repeated
  140. * so that no pops are heard, and the left and right channels
  141. * won't end up being swapped because of the underrun.
  142. */
  143. unsigned enable_channel_combine:1;
  144. unsigned int fmt;
  145. int clk_div;
  146. int clk_input_pin;
  147. bool i2s_accurate_sck;
  148. };
  149. static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
  150. int reg, u32 val)
  151. {
  152. __raw_writel(val, dev->base + reg);
  153. }
  154. static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
  155. {
  156. return __raw_readl(dev->base + reg);
  157. }
  158. static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
  159. {
  160. u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
  161. /* The clock needs to toggle to complete reset.
  162. * So, fake it by toggling the clk polarity.
  163. */
  164. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
  165. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
  166. }
  167. static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
  168. struct snd_pcm_substream *substream)
  169. {
  170. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  171. u32 spcr;
  172. u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
  173. /* Enable transmitter or receiver */
  174. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  175. spcr |= mask;
  176. if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
  177. /* Start frame sync */
  178. spcr |= DAVINCI_MCBSP_SPCR_FRST;
  179. }
  180. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  181. }
  182. static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
  183. {
  184. u32 spcr;
  185. /* Reset transmitter/receiver and sample rate/frame sync generators */
  186. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  187. spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
  188. spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
  189. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  190. toggle_clock(dev, playback);
  191. }
  192. #define DEFAULT_BITPERSAMPLE 16
  193. static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  194. unsigned int fmt)
  195. {
  196. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
  197. unsigned int pcr;
  198. unsigned int srgr;
  199. bool inv_fs = false;
  200. /* Attention srgr is updated by hw_params! */
  201. srgr = DAVINCI_MCBSP_SRGR_FSGM |
  202. DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
  203. DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
  204. dev->fmt = fmt;
  205. /* set master/slave audio interface */
  206. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  207. case SND_SOC_DAIFMT_CBS_CFS:
  208. /* cpu is master */
  209. pcr = DAVINCI_MCBSP_PCR_FSXM |
  210. DAVINCI_MCBSP_PCR_FSRM |
  211. DAVINCI_MCBSP_PCR_CLKXM |
  212. DAVINCI_MCBSP_PCR_CLKRM;
  213. break;
  214. case SND_SOC_DAIFMT_CBM_CFS:
  215. pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
  216. /*
  217. * Selection of the clock input pin that is the
  218. * input for the Sample Rate Generator.
  219. * McBSP FSR and FSX are driven by the Sample Rate
  220. * Generator.
  221. */
  222. switch (dev->clk_input_pin) {
  223. case MCBSP_CLKS:
  224. pcr |= DAVINCI_MCBSP_PCR_CLKXM |
  225. DAVINCI_MCBSP_PCR_CLKRM;
  226. break;
  227. case MCBSP_CLKR:
  228. pcr |= DAVINCI_MCBSP_PCR_SCLKME;
  229. break;
  230. default:
  231. dev_err(dev->dev, "bad clk_input_pin\n");
  232. return -EINVAL;
  233. }
  234. break;
  235. case SND_SOC_DAIFMT_CBM_CFM:
  236. /* codec is master */
  237. pcr = 0;
  238. break;
  239. default:
  240. printk(KERN_ERR "%s:bad master\n", __func__);
  241. return -EINVAL;
  242. }
  243. /* interface format */
  244. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  245. case SND_SOC_DAIFMT_I2S:
  246. /* Davinci doesn't support TRUE I2S, but some codecs will have
  247. * the left and right channels contiguous. This allows
  248. * dsp_a mode to be used with an inverted normal frame clk.
  249. * If your codec is master and does not have contiguous
  250. * channels, then you will have sound on only one channel.
  251. * Try using a different mode, or codec as slave.
  252. *
  253. * The TLV320AIC33 is an example of a codec where this works.
  254. * It has a variable bit clock frequency allowing it to have
  255. * valid data on every bit clock.
  256. *
  257. * The TLV320AIC23 is an example of a codec where this does not
  258. * work. It has a fixed bit clock frequency with progressively
  259. * more empty bit clock slots between channels as the sample
  260. * rate is lowered.
  261. */
  262. inv_fs = true;
  263. fallthrough;
  264. case SND_SOC_DAIFMT_DSP_A:
  265. dev->mode = MOD_DSP_A;
  266. break;
  267. case SND_SOC_DAIFMT_DSP_B:
  268. dev->mode = MOD_DSP_B;
  269. break;
  270. default:
  271. printk(KERN_ERR "%s:bad format\n", __func__);
  272. return -EINVAL;
  273. }
  274. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  275. case SND_SOC_DAIFMT_NB_NF:
  276. /* CLKRP Receive clock polarity,
  277. * 1 - sampled on rising edge of CLKR
  278. * valid on rising edge
  279. * CLKXP Transmit clock polarity,
  280. * 1 - clocked on falling edge of CLKX
  281. * valid on rising edge
  282. * FSRP Receive frame sync pol, 0 - active high
  283. * FSXP Transmit frame sync pol, 0 - active high
  284. */
  285. pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
  286. break;
  287. case SND_SOC_DAIFMT_IB_IF:
  288. /* CLKRP Receive clock polarity,
  289. * 0 - sampled on falling edge of CLKR
  290. * valid on falling edge
  291. * CLKXP Transmit clock polarity,
  292. * 0 - clocked on rising edge of CLKX
  293. * valid on falling edge
  294. * FSRP Receive frame sync pol, 1 - active low
  295. * FSXP Transmit frame sync pol, 1 - active low
  296. */
  297. pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
  298. break;
  299. case SND_SOC_DAIFMT_NB_IF:
  300. /* CLKRP Receive clock polarity,
  301. * 1 - sampled on rising edge of CLKR
  302. * valid on rising edge
  303. * CLKXP Transmit clock polarity,
  304. * 1 - clocked on falling edge of CLKX
  305. * valid on rising edge
  306. * FSRP Receive frame sync pol, 1 - active low
  307. * FSXP Transmit frame sync pol, 1 - active low
  308. */
  309. pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
  310. DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
  311. break;
  312. case SND_SOC_DAIFMT_IB_NF:
  313. /* CLKRP Receive clock polarity,
  314. * 0 - sampled on falling edge of CLKR
  315. * valid on falling edge
  316. * CLKXP Transmit clock polarity,
  317. * 0 - clocked on rising edge of CLKX
  318. * valid on falling edge
  319. * FSRP Receive frame sync pol, 0 - active high
  320. * FSXP Transmit frame sync pol, 0 - active high
  321. */
  322. break;
  323. default:
  324. return -EINVAL;
  325. }
  326. if (inv_fs == true)
  327. pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
  328. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
  329. dev->pcr = pcr;
  330. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
  331. return 0;
  332. }
  333. static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
  334. int div_id, int div)
  335. {
  336. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
  337. if (div_id != DAVINCI_MCBSP_CLKGDV)
  338. return -ENODEV;
  339. dev->clk_div = div;
  340. return 0;
  341. }
  342. static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
  343. struct snd_pcm_hw_params *params,
  344. struct snd_soc_dai *dai)
  345. {
  346. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
  347. struct snd_interval *i = NULL;
  348. int mcbsp_word_length, master;
  349. unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
  350. u32 spcr;
  351. snd_pcm_format_t fmt;
  352. unsigned element_cnt = 1;
  353. /* general line settings */
  354. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  355. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  356. spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
  357. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  358. } else {
  359. spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
  360. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  361. }
  362. master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
  363. fmt = params_format(params);
  364. mcbsp_word_length = asp_word_length[fmt];
  365. switch (master) {
  366. case SND_SOC_DAIFMT_CBS_CFS:
  367. freq = clk_get_rate(dev->clk);
  368. srgr = DAVINCI_MCBSP_SRGR_FSGM |
  369. DAVINCI_MCBSP_SRGR_CLKSM;
  370. srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
  371. 8 - 1);
  372. if (dev->i2s_accurate_sck) {
  373. clk_div = 256;
  374. do {
  375. framesize = (freq / (--clk_div)) /
  376. params->rate_num *
  377. params->rate_den;
  378. } while (((framesize < 33) || (framesize > 4095)) &&
  379. (clk_div));
  380. clk_div--;
  381. srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
  382. } else {
  383. /* symmetric waveforms */
  384. clk_div = freq / (mcbsp_word_length * 16) /
  385. params->rate_num * params->rate_den;
  386. srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
  387. 16 - 1);
  388. }
  389. clk_div &= 0xFF;
  390. srgr |= clk_div;
  391. break;
  392. case SND_SOC_DAIFMT_CBM_CFS:
  393. srgr = DAVINCI_MCBSP_SRGR_FSGM;
  394. clk_div = dev->clk_div - 1;
  395. srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
  396. srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
  397. clk_div &= 0xFF;
  398. srgr |= clk_div;
  399. break;
  400. case SND_SOC_DAIFMT_CBM_CFM:
  401. /* Clock and frame sync given from external sources */
  402. i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
  403. srgr = DAVINCI_MCBSP_SRGR_FSGM;
  404. srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
  405. pr_debug("%s - %d FWID set: re-read srgr = %X\n",
  406. __func__, __LINE__, snd_interval_value(i) - 1);
  407. i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
  408. srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
  409. break;
  410. default:
  411. return -EINVAL;
  412. }
  413. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
  414. rcr = DAVINCI_MCBSP_RCR_RFIG;
  415. xcr = DAVINCI_MCBSP_XCR_XFIG;
  416. if (dev->mode == MOD_DSP_B) {
  417. rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
  418. xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
  419. } else {
  420. rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
  421. xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
  422. }
  423. /* Determine xfer data type */
  424. fmt = params_format(params);
  425. if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
  426. printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
  427. return -EINVAL;
  428. }
  429. if (params_channels(params) == 2) {
  430. element_cnt = 2;
  431. if (double_fmt[fmt] && dev->enable_channel_combine) {
  432. element_cnt = 1;
  433. fmt = double_fmt[fmt];
  434. }
  435. switch (master) {
  436. case SND_SOC_DAIFMT_CBS_CFS:
  437. case SND_SOC_DAIFMT_CBS_CFM:
  438. rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
  439. xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
  440. rcr |= DAVINCI_MCBSP_RCR_RPHASE;
  441. xcr |= DAVINCI_MCBSP_XCR_XPHASE;
  442. break;
  443. case SND_SOC_DAIFMT_CBM_CFM:
  444. case SND_SOC_DAIFMT_CBM_CFS:
  445. rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
  446. xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
  447. break;
  448. default:
  449. return -EINVAL;
  450. }
  451. }
  452. mcbsp_word_length = asp_word_length[fmt];
  453. switch (master) {
  454. case SND_SOC_DAIFMT_CBS_CFS:
  455. case SND_SOC_DAIFMT_CBS_CFM:
  456. rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
  457. xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
  458. break;
  459. case SND_SOC_DAIFMT_CBM_CFM:
  460. case SND_SOC_DAIFMT_CBM_CFS:
  461. rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
  462. xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
  463. break;
  464. default:
  465. return -EINVAL;
  466. }
  467. rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
  468. DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
  469. xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
  470. DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
  471. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  472. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
  473. else
  474. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
  475. pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
  476. pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
  477. pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
  478. return 0;
  479. }
  480. static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
  481. struct snd_soc_dai *dai)
  482. {
  483. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
  484. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  485. u32 spcr;
  486. u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
  487. davinci_mcbsp_stop(dev, playback);
  488. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  489. if (spcr & mask) {
  490. /* start off disabled */
  491. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
  492. spcr & ~mask);
  493. toggle_clock(dev, playback);
  494. }
  495. if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
  496. DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
  497. /* Start the sample generator */
  498. spcr |= DAVINCI_MCBSP_SPCR_GRST;
  499. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  500. }
  501. if (playback) {
  502. /* Enable the transmitter */
  503. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  504. spcr |= DAVINCI_MCBSP_SPCR_XRST;
  505. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  506. /* wait for any unexpected frame sync error to occur */
  507. udelay(100);
  508. /* Disable the transmitter to clear any outstanding XSYNCERR */
  509. spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
  510. spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
  511. davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
  512. toggle_clock(dev, playback);
  513. }
  514. return 0;
  515. }
  516. static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  517. struct snd_soc_dai *dai)
  518. {
  519. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
  520. int ret = 0;
  521. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  522. switch (cmd) {
  523. case SNDRV_PCM_TRIGGER_START:
  524. case SNDRV_PCM_TRIGGER_RESUME:
  525. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  526. davinci_mcbsp_start(dev, substream);
  527. break;
  528. case SNDRV_PCM_TRIGGER_STOP:
  529. case SNDRV_PCM_TRIGGER_SUSPEND:
  530. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  531. davinci_mcbsp_stop(dev, playback);
  532. break;
  533. default:
  534. ret = -EINVAL;
  535. }
  536. return ret;
  537. }
  538. static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
  539. struct snd_soc_dai *dai)
  540. {
  541. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
  542. int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  543. davinci_mcbsp_stop(dev, playback);
  544. }
  545. #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
  546. #define DAVINCI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  547. SNDRV_PCM_FMTBIT_S32_LE)
  548. static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
  549. .shutdown = davinci_i2s_shutdown,
  550. .prepare = davinci_i2s_prepare,
  551. .trigger = davinci_i2s_trigger,
  552. .hw_params = davinci_i2s_hw_params,
  553. .set_fmt = davinci_i2s_set_dai_fmt,
  554. .set_clkdiv = davinci_i2s_dai_set_clkdiv,
  555. };
  556. static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
  557. {
  558. struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
  559. dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
  560. dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
  561. return 0;
  562. }
  563. static struct snd_soc_dai_driver davinci_i2s_dai = {
  564. .probe = davinci_i2s_dai_probe,
  565. .playback = {
  566. .channels_min = 2,
  567. .channels_max = 2,
  568. .rates = DAVINCI_I2S_RATES,
  569. .formats = DAVINCI_I2S_FORMATS,
  570. },
  571. .capture = {
  572. .channels_min = 2,
  573. .channels_max = 2,
  574. .rates = DAVINCI_I2S_RATES,
  575. .formats = DAVINCI_I2S_FORMATS,
  576. },
  577. .ops = &davinci_i2s_dai_ops,
  578. };
  579. static const struct snd_soc_component_driver davinci_i2s_component = {
  580. .name = DRV_NAME,
  581. };
  582. static int davinci_i2s_probe(struct platform_device *pdev)
  583. {
  584. struct snd_dmaengine_dai_dma_data *dma_data;
  585. struct davinci_mcbsp_dev *dev;
  586. struct resource *mem, *res;
  587. void __iomem *io_base;
  588. int *dma;
  589. int ret;
  590. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  591. if (!mem) {
  592. dev_warn(&pdev->dev,
  593. "\"mpu\" mem resource not found, using index 0\n");
  594. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  595. if (!mem) {
  596. dev_err(&pdev->dev, "no mem resource?\n");
  597. return -ENODEV;
  598. }
  599. }
  600. io_base = devm_ioremap_resource(&pdev->dev, mem);
  601. if (IS_ERR(io_base))
  602. return PTR_ERR(io_base);
  603. dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
  604. GFP_KERNEL);
  605. if (!dev)
  606. return -ENOMEM;
  607. dev->base = io_base;
  608. /* setup DMA, first TX, then RX */
  609. dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
  610. dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
  611. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  612. if (res) {
  613. dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
  614. *dma = res->start;
  615. dma_data->filter_data = dma;
  616. } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
  617. dma_data->filter_data = "tx";
  618. } else {
  619. dev_err(&pdev->dev, "Missing DMA tx resource\n");
  620. return -ENODEV;
  621. }
  622. dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
  623. dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
  624. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  625. if (res) {
  626. dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
  627. *dma = res->start;
  628. dma_data->filter_data = dma;
  629. } else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
  630. dma_data->filter_data = "rx";
  631. } else {
  632. dev_err(&pdev->dev, "Missing DMA rx resource\n");
  633. return -ENODEV;
  634. }
  635. dev->clk = clk_get(&pdev->dev, NULL);
  636. if (IS_ERR(dev->clk))
  637. return -ENODEV;
  638. ret = clk_enable(dev->clk);
  639. if (ret)
  640. goto err_put_clk;
  641. dev->dev = &pdev->dev;
  642. dev_set_drvdata(&pdev->dev, dev);
  643. ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
  644. &davinci_i2s_dai, 1);
  645. if (ret != 0)
  646. goto err_release_clk;
  647. ret = edma_pcm_platform_register(&pdev->dev);
  648. if (ret) {
  649. dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
  650. goto err_unregister_component;
  651. }
  652. return 0;
  653. err_unregister_component:
  654. snd_soc_unregister_component(&pdev->dev);
  655. err_release_clk:
  656. clk_disable(dev->clk);
  657. err_put_clk:
  658. clk_put(dev->clk);
  659. return ret;
  660. }
  661. static int davinci_i2s_remove(struct platform_device *pdev)
  662. {
  663. struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
  664. snd_soc_unregister_component(&pdev->dev);
  665. clk_disable(dev->clk);
  666. clk_put(dev->clk);
  667. dev->clk = NULL;
  668. return 0;
  669. }
  670. static const struct of_device_id davinci_i2s_match[] = {
  671. { .compatible = "ti,da850-mcbsp" },
  672. {},
  673. };
  674. MODULE_DEVICE_TABLE(of, davinci_i2s_match);
  675. static struct platform_driver davinci_mcbsp_driver = {
  676. .probe = davinci_i2s_probe,
  677. .remove = davinci_i2s_remove,
  678. .driver = {
  679. .name = "davinci-mcbsp",
  680. .of_match_table = of_match_ptr(davinci_i2s_match),
  681. },
  682. };
  683. module_platform_driver(davinci_mcbsp_driver);
  684. MODULE_AUTHOR("Vladimir Barinov");
  685. MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
  686. MODULE_LICENSE("GPL");