rockchip_spdif.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* sound/soc/rockchip/rk_spdif.c
  3. *
  4. * ALSA SoC Audio Layer - Rockchip I2S Controller driver
  5. *
  6. * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
  7. * Author: Jianqun <jay.xu@rock-chips.com>
  8. * Copyright (c) 2015 Collabora Ltd.
  9. * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/delay.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/clk.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/mfd/syscon.h>
  17. #include <linux/regmap.h>
  18. #include <sound/pcm_params.h>
  19. #include <sound/dmaengine_pcm.h>
  20. #include "rockchip_spdif.h"
  21. enum rk_spdif_type {
  22. RK_SPDIF_RK3066,
  23. RK_SPDIF_RK3188,
  24. RK_SPDIF_RK3288,
  25. RK_SPDIF_RK3366,
  26. };
  27. #define RK3288_GRF_SOC_CON2 0x24c
  28. struct rk_spdif_dev {
  29. struct device *dev;
  30. struct clk *mclk;
  31. struct clk *hclk;
  32. struct snd_dmaengine_dai_dma_data playback_dma_data;
  33. struct regmap *regmap;
  34. };
  35. static const struct of_device_id rk_spdif_match[] = {
  36. { .compatible = "rockchip,rk3066-spdif",
  37. .data = (void *)RK_SPDIF_RK3066 },
  38. { .compatible = "rockchip,rk3188-spdif",
  39. .data = (void *)RK_SPDIF_RK3188 },
  40. { .compatible = "rockchip,rk3228-spdif",
  41. .data = (void *)RK_SPDIF_RK3366 },
  42. { .compatible = "rockchip,rk3288-spdif",
  43. .data = (void *)RK_SPDIF_RK3288 },
  44. { .compatible = "rockchip,rk3328-spdif",
  45. .data = (void *)RK_SPDIF_RK3366 },
  46. { .compatible = "rockchip,rk3366-spdif",
  47. .data = (void *)RK_SPDIF_RK3366 },
  48. { .compatible = "rockchip,rk3368-spdif",
  49. .data = (void *)RK_SPDIF_RK3366 },
  50. { .compatible = "rockchip,rk3399-spdif",
  51. .data = (void *)RK_SPDIF_RK3366 },
  52. {},
  53. };
  54. MODULE_DEVICE_TABLE(of, rk_spdif_match);
  55. static int __maybe_unused rk_spdif_runtime_suspend(struct device *dev)
  56. {
  57. struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
  58. regcache_cache_only(spdif->regmap, true);
  59. clk_disable_unprepare(spdif->mclk);
  60. clk_disable_unprepare(spdif->hclk);
  61. return 0;
  62. }
  63. static int __maybe_unused rk_spdif_runtime_resume(struct device *dev)
  64. {
  65. struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
  66. int ret;
  67. ret = clk_prepare_enable(spdif->mclk);
  68. if (ret) {
  69. dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
  70. return ret;
  71. }
  72. ret = clk_prepare_enable(spdif->hclk);
  73. if (ret) {
  74. dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
  75. return ret;
  76. }
  77. regcache_cache_only(spdif->regmap, false);
  78. regcache_mark_dirty(spdif->regmap);
  79. ret = regcache_sync(spdif->regmap);
  80. if (ret) {
  81. clk_disable_unprepare(spdif->mclk);
  82. clk_disable_unprepare(spdif->hclk);
  83. }
  84. return ret;
  85. }
  86. static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
  87. struct snd_pcm_hw_params *params,
  88. struct snd_soc_dai *dai)
  89. {
  90. struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
  91. unsigned int val = SPDIF_CFGR_HALFWORD_ENABLE;
  92. int srate, mclk;
  93. int ret;
  94. srate = params_rate(params);
  95. mclk = srate * 128;
  96. switch (params_format(params)) {
  97. case SNDRV_PCM_FORMAT_S16_LE:
  98. val |= SPDIF_CFGR_VDW_16;
  99. break;
  100. case SNDRV_PCM_FORMAT_S20_3LE:
  101. val |= SPDIF_CFGR_VDW_20;
  102. break;
  103. case SNDRV_PCM_FORMAT_S24_LE:
  104. val |= SPDIF_CFGR_VDW_24;
  105. break;
  106. default:
  107. return -EINVAL;
  108. }
  109. /* Set clock and calculate divider */
  110. ret = clk_set_rate(spdif->mclk, mclk);
  111. if (ret != 0) {
  112. dev_err(spdif->dev, "Failed to set module clock rate: %d\n",
  113. ret);
  114. return ret;
  115. }
  116. ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
  117. SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE |
  118. SDPIF_CFGR_VDW_MASK,
  119. val);
  120. return ret;
  121. }
  122. static int rk_spdif_trigger(struct snd_pcm_substream *substream,
  123. int cmd, struct snd_soc_dai *dai)
  124. {
  125. struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
  126. int ret;
  127. switch (cmd) {
  128. case SNDRV_PCM_TRIGGER_START:
  129. case SNDRV_PCM_TRIGGER_RESUME:
  130. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  131. ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
  132. SPDIF_DMACR_TDE_ENABLE |
  133. SPDIF_DMACR_TDL_MASK,
  134. SPDIF_DMACR_TDE_ENABLE |
  135. SPDIF_DMACR_TDL(16));
  136. if (ret != 0)
  137. return ret;
  138. ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
  139. SPDIF_XFER_TXS_START,
  140. SPDIF_XFER_TXS_START);
  141. break;
  142. case SNDRV_PCM_TRIGGER_SUSPEND:
  143. case SNDRV_PCM_TRIGGER_STOP:
  144. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  145. ret = regmap_update_bits(spdif->regmap, SPDIF_DMACR,
  146. SPDIF_DMACR_TDE_ENABLE,
  147. SPDIF_DMACR_TDE_DISABLE);
  148. if (ret != 0)
  149. return ret;
  150. ret = regmap_update_bits(spdif->regmap, SPDIF_XFER,
  151. SPDIF_XFER_TXS_START,
  152. SPDIF_XFER_TXS_STOP);
  153. break;
  154. default:
  155. ret = -EINVAL;
  156. break;
  157. }
  158. return ret;
  159. }
  160. static int rk_spdif_dai_probe(struct snd_soc_dai *dai)
  161. {
  162. struct rk_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
  163. dai->playback_dma_data = &spdif->playback_dma_data;
  164. return 0;
  165. }
  166. static const struct snd_soc_dai_ops rk_spdif_dai_ops = {
  167. .hw_params = rk_spdif_hw_params,
  168. .trigger = rk_spdif_trigger,
  169. };
  170. static struct snd_soc_dai_driver rk_spdif_dai = {
  171. .probe = rk_spdif_dai_probe,
  172. .playback = {
  173. .stream_name = "Playback",
  174. .channels_min = 2,
  175. .channels_max = 2,
  176. .rates = (SNDRV_PCM_RATE_32000 |
  177. SNDRV_PCM_RATE_44100 |
  178. SNDRV_PCM_RATE_48000 |
  179. SNDRV_PCM_RATE_96000 |
  180. SNDRV_PCM_RATE_192000),
  181. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  182. SNDRV_PCM_FMTBIT_S20_3LE |
  183. SNDRV_PCM_FMTBIT_S24_LE),
  184. },
  185. .ops = &rk_spdif_dai_ops,
  186. };
  187. static const struct snd_soc_component_driver rk_spdif_component = {
  188. .name = "rockchip-spdif",
  189. };
  190. static bool rk_spdif_wr_reg(struct device *dev, unsigned int reg)
  191. {
  192. switch (reg) {
  193. case SPDIF_CFGR:
  194. case SPDIF_DMACR:
  195. case SPDIF_INTCR:
  196. case SPDIF_XFER:
  197. case SPDIF_SMPDR:
  198. return true;
  199. default:
  200. return false;
  201. }
  202. }
  203. static bool rk_spdif_rd_reg(struct device *dev, unsigned int reg)
  204. {
  205. switch (reg) {
  206. case SPDIF_CFGR:
  207. case SPDIF_SDBLR:
  208. case SPDIF_INTCR:
  209. case SPDIF_INTSR:
  210. case SPDIF_XFER:
  211. return true;
  212. default:
  213. return false;
  214. }
  215. }
  216. static bool rk_spdif_volatile_reg(struct device *dev, unsigned int reg)
  217. {
  218. switch (reg) {
  219. case SPDIF_INTSR:
  220. case SPDIF_SDBLR:
  221. return true;
  222. default:
  223. return false;
  224. }
  225. }
  226. static const struct regmap_config rk_spdif_regmap_config = {
  227. .reg_bits = 32,
  228. .reg_stride = 4,
  229. .val_bits = 32,
  230. .max_register = SPDIF_SMPDR,
  231. .writeable_reg = rk_spdif_wr_reg,
  232. .readable_reg = rk_spdif_rd_reg,
  233. .volatile_reg = rk_spdif_volatile_reg,
  234. .cache_type = REGCACHE_FLAT,
  235. };
  236. static int rk_spdif_probe(struct platform_device *pdev)
  237. {
  238. struct device_node *np = pdev->dev.of_node;
  239. struct rk_spdif_dev *spdif;
  240. const struct of_device_id *match;
  241. struct resource *res;
  242. void __iomem *regs;
  243. int ret;
  244. match = of_match_node(rk_spdif_match, np);
  245. if (match->data == (void *)RK_SPDIF_RK3288) {
  246. struct regmap *grf;
  247. grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
  248. if (IS_ERR(grf)) {
  249. dev_err(&pdev->dev,
  250. "rockchip_spdif missing 'rockchip,grf' \n");
  251. return PTR_ERR(grf);
  252. }
  253. /* Select the 8 channel SPDIF solution on RK3288 as
  254. * the 2 channel one does not appear to work
  255. */
  256. regmap_write(grf, RK3288_GRF_SOC_CON2, BIT(1) << 16);
  257. }
  258. spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
  259. if (!spdif)
  260. return -ENOMEM;
  261. spdif->hclk = devm_clk_get(&pdev->dev, "hclk");
  262. if (IS_ERR(spdif->hclk))
  263. return PTR_ERR(spdif->hclk);
  264. spdif->mclk = devm_clk_get(&pdev->dev, "mclk");
  265. if (IS_ERR(spdif->mclk))
  266. return PTR_ERR(spdif->mclk);
  267. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  268. regs = devm_ioremap_resource(&pdev->dev, res);
  269. if (IS_ERR(regs))
  270. return PTR_ERR(regs);
  271. spdif->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "hclk", regs,
  272. &rk_spdif_regmap_config);
  273. if (IS_ERR(spdif->regmap))
  274. return PTR_ERR(spdif->regmap);
  275. spdif->playback_dma_data.addr = res->start + SPDIF_SMPDR;
  276. spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  277. spdif->playback_dma_data.maxburst = 4;
  278. spdif->dev = &pdev->dev;
  279. dev_set_drvdata(&pdev->dev, spdif);
  280. pm_runtime_enable(&pdev->dev);
  281. if (!pm_runtime_enabled(&pdev->dev)) {
  282. ret = rk_spdif_runtime_resume(&pdev->dev);
  283. if (ret)
  284. goto err_pm_runtime;
  285. }
  286. ret = devm_snd_soc_register_component(&pdev->dev,
  287. &rk_spdif_component,
  288. &rk_spdif_dai, 1);
  289. if (ret) {
  290. dev_err(&pdev->dev, "Could not register DAI\n");
  291. goto err_pm_suspend;
  292. }
  293. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  294. if (ret) {
  295. dev_err(&pdev->dev, "Could not register PCM\n");
  296. goto err_pm_suspend;
  297. }
  298. return 0;
  299. err_pm_suspend:
  300. if (!pm_runtime_status_suspended(&pdev->dev))
  301. rk_spdif_runtime_suspend(&pdev->dev);
  302. err_pm_runtime:
  303. pm_runtime_disable(&pdev->dev);
  304. return ret;
  305. }
  306. static int rk_spdif_remove(struct platform_device *pdev)
  307. {
  308. pm_runtime_disable(&pdev->dev);
  309. if (!pm_runtime_status_suspended(&pdev->dev))
  310. rk_spdif_runtime_suspend(&pdev->dev);
  311. return 0;
  312. }
  313. static const struct dev_pm_ops rk_spdif_pm_ops = {
  314. SET_RUNTIME_PM_OPS(rk_spdif_runtime_suspend, rk_spdif_runtime_resume,
  315. NULL)
  316. };
  317. static struct platform_driver rk_spdif_driver = {
  318. .probe = rk_spdif_probe,
  319. .remove = rk_spdif_remove,
  320. .driver = {
  321. .name = "rockchip-spdif",
  322. .of_match_table = of_match_ptr(rk_spdif_match),
  323. .pm = &rk_spdif_pm_ops,
  324. },
  325. };
  326. module_platform_driver(rk_spdif_driver);
  327. MODULE_ALIAS("platform:rockchip-spdif");
  328. MODULE_DESCRIPTION("ROCKCHIP SPDIF transceiver Interface");
  329. MODULE_AUTHOR("Sjoerd Simons <sjoerd.simons@collabora.co.uk>");
  330. MODULE_LICENSE("GPL v2");