rockchip_pdm.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver
  4. *
  5. * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
  6. */
  7. #include <linux/module.h>
  8. #include <linux/clk.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/pm_runtime.h>
  12. #include <linux/rational.h>
  13. #include <linux/regmap.h>
  14. #include <linux/reset.h>
  15. #include <sound/dmaengine_pcm.h>
  16. #include <sound/pcm_params.h>
  17. #include "rockchip_pdm.h"
  18. #define PDM_DMA_BURST_SIZE (8) /* size * width: 8*4 = 32 bytes */
  19. #define PDM_SIGNOFF_CLK_RATE (100000000)
  20. enum rk_pdm_version {
  21. RK_PDM_RK3229,
  22. RK_PDM_RK3308,
  23. };
  24. struct rk_pdm_dev {
  25. struct device *dev;
  26. struct clk *clk;
  27. struct clk *hclk;
  28. struct regmap *regmap;
  29. struct snd_dmaengine_dai_dma_data capture_dma_data;
  30. struct reset_control *reset;
  31. enum rk_pdm_version version;
  32. };
  33. struct rk_pdm_clkref {
  34. unsigned int sr;
  35. unsigned int clk;
  36. unsigned int clk_out;
  37. };
  38. struct rk_pdm_ds_ratio {
  39. unsigned int ratio;
  40. unsigned int sr;
  41. };
  42. static struct rk_pdm_clkref clkref[] = {
  43. { 8000, 40960000, 2048000 },
  44. { 11025, 56448000, 2822400 },
  45. { 12000, 61440000, 3072000 },
  46. { 8000, 98304000, 2048000 },
  47. { 12000, 98304000, 3072000 },
  48. };
  49. static struct rk_pdm_ds_ratio ds_ratio[] = {
  50. { 0, 192000 },
  51. { 0, 176400 },
  52. { 0, 128000 },
  53. { 1, 96000 },
  54. { 1, 88200 },
  55. { 1, 64000 },
  56. { 2, 48000 },
  57. { 2, 44100 },
  58. { 2, 32000 },
  59. { 3, 24000 },
  60. { 3, 22050 },
  61. { 3, 16000 },
  62. { 4, 12000 },
  63. { 4, 11025 },
  64. { 4, 8000 },
  65. };
  66. static unsigned int get_pdm_clk(struct rk_pdm_dev *pdm, unsigned int sr,
  67. unsigned int *clk_src, unsigned int *clk_out)
  68. {
  69. unsigned int i, count, clk, div, rate;
  70. clk = 0;
  71. if (!sr)
  72. return clk;
  73. count = ARRAY_SIZE(clkref);
  74. for (i = 0; i < count; i++) {
  75. if (sr % clkref[i].sr)
  76. continue;
  77. div = sr / clkref[i].sr;
  78. if ((div & (div - 1)) == 0) {
  79. *clk_out = clkref[i].clk_out;
  80. rate = clk_round_rate(pdm->clk, clkref[i].clk);
  81. if (rate != clkref[i].clk)
  82. continue;
  83. clk = clkref[i].clk;
  84. *clk_src = clkref[i].clk;
  85. break;
  86. }
  87. }
  88. if (!clk) {
  89. clk = clk_round_rate(pdm->clk, PDM_SIGNOFF_CLK_RATE);
  90. *clk_src = clk;
  91. }
  92. return clk;
  93. }
  94. static unsigned int get_pdm_ds_ratio(unsigned int sr)
  95. {
  96. unsigned int i, count, ratio;
  97. ratio = 0;
  98. if (!sr)
  99. return ratio;
  100. count = ARRAY_SIZE(ds_ratio);
  101. for (i = 0; i < count; i++) {
  102. if (sr == ds_ratio[i].sr)
  103. ratio = ds_ratio[i].ratio;
  104. }
  105. return ratio;
  106. }
  107. static inline struct rk_pdm_dev *to_info(struct snd_soc_dai *dai)
  108. {
  109. return snd_soc_dai_get_drvdata(dai);
  110. }
  111. static void rockchip_pdm_rxctrl(struct rk_pdm_dev *pdm, int on)
  112. {
  113. if (on) {
  114. regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
  115. PDM_DMA_RD_MSK, PDM_DMA_RD_EN);
  116. regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
  117. PDM_RX_MASK, PDM_RX_START);
  118. } else {
  119. regmap_update_bits(pdm->regmap, PDM_DMA_CTRL,
  120. PDM_DMA_RD_MSK, PDM_DMA_RD_DIS);
  121. regmap_update_bits(pdm->regmap, PDM_SYSCONFIG,
  122. PDM_RX_MASK | PDM_RX_CLR_MASK,
  123. PDM_RX_STOP | PDM_RX_CLR_WR);
  124. }
  125. }
  126. static int rockchip_pdm_hw_params(struct snd_pcm_substream *substream,
  127. struct snd_pcm_hw_params *params,
  128. struct snd_soc_dai *dai)
  129. {
  130. struct rk_pdm_dev *pdm = to_info(dai);
  131. unsigned int val = 0;
  132. unsigned int clk_rate, clk_div, samplerate;
  133. unsigned int clk_src, clk_out = 0;
  134. unsigned long m, n;
  135. bool change;
  136. int ret;
  137. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  138. return 0;
  139. samplerate = params_rate(params);
  140. clk_rate = get_pdm_clk(pdm, samplerate, &clk_src, &clk_out);
  141. if (!clk_rate)
  142. return -EINVAL;
  143. ret = clk_set_rate(pdm->clk, clk_src);
  144. if (ret)
  145. return -EINVAL;
  146. if (pdm->version == RK_PDM_RK3308) {
  147. rational_best_approximation(clk_out, clk_src,
  148. GENMASK(16 - 1, 0),
  149. GENMASK(16 - 1, 0),
  150. &m, &n);
  151. val = (m << PDM_FD_NUMERATOR_SFT) |
  152. (n << PDM_FD_DENOMINATOR_SFT);
  153. regmap_update_bits_check(pdm->regmap, PDM_CTRL1,
  154. PDM_FD_NUMERATOR_MSK |
  155. PDM_FD_DENOMINATOR_MSK,
  156. val, &change);
  157. if (change) {
  158. reset_control_assert(pdm->reset);
  159. reset_control_deassert(pdm->reset);
  160. rockchip_pdm_rxctrl(pdm, 0);
  161. }
  162. clk_div = n / m;
  163. if (clk_div >= 40)
  164. val = PDM_CLK_FD_RATIO_40;
  165. else if (clk_div <= 35)
  166. val = PDM_CLK_FD_RATIO_35;
  167. else
  168. return -EINVAL;
  169. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL,
  170. PDM_CLK_FD_RATIO_MSK,
  171. val);
  172. }
  173. val = get_pdm_ds_ratio(samplerate);
  174. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_DS_RATIO_MSK, val);
  175. regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
  176. PDM_HPF_CF_MSK, PDM_HPF_60HZ);
  177. regmap_update_bits(pdm->regmap, PDM_HPF_CTRL,
  178. PDM_HPF_LE | PDM_HPF_RE, PDM_HPF_LE | PDM_HPF_RE);
  179. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, PDM_CLK_EN, PDM_CLK_EN);
  180. if (pdm->version != RK_PDM_RK3229)
  181. regmap_update_bits(pdm->regmap, PDM_CTRL0,
  182. PDM_MODE_MSK, PDM_MODE_LJ);
  183. val = 0;
  184. switch (params_format(params)) {
  185. case SNDRV_PCM_FORMAT_S8:
  186. val |= PDM_VDW(8);
  187. break;
  188. case SNDRV_PCM_FORMAT_S16_LE:
  189. val |= PDM_VDW(16);
  190. break;
  191. case SNDRV_PCM_FORMAT_S20_3LE:
  192. val |= PDM_VDW(20);
  193. break;
  194. case SNDRV_PCM_FORMAT_S24_LE:
  195. val |= PDM_VDW(24);
  196. break;
  197. case SNDRV_PCM_FORMAT_S32_LE:
  198. val |= PDM_VDW(32);
  199. break;
  200. default:
  201. return -EINVAL;
  202. }
  203. switch (params_channels(params)) {
  204. case 8:
  205. val |= PDM_PATH3_EN;
  206. fallthrough;
  207. case 6:
  208. val |= PDM_PATH2_EN;
  209. fallthrough;
  210. case 4:
  211. val |= PDM_PATH1_EN;
  212. fallthrough;
  213. case 2:
  214. val |= PDM_PATH0_EN;
  215. break;
  216. default:
  217. dev_err(pdm->dev, "invalid channel: %d\n",
  218. params_channels(params));
  219. return -EINVAL;
  220. }
  221. regmap_update_bits(pdm->regmap, PDM_CTRL0,
  222. PDM_PATH_MSK | PDM_VDW_MSK,
  223. val);
  224. /* all channels share the single FIFO */
  225. regmap_update_bits(pdm->regmap, PDM_DMA_CTRL, PDM_DMA_RDL_MSK,
  226. PDM_DMA_RDL(8 * params_channels(params)));
  227. return 0;
  228. }
  229. static int rockchip_pdm_set_fmt(struct snd_soc_dai *cpu_dai,
  230. unsigned int fmt)
  231. {
  232. struct rk_pdm_dev *pdm = to_info(cpu_dai);
  233. unsigned int mask = 0, val = 0;
  234. mask = PDM_CKP_MSK;
  235. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  236. case SND_SOC_DAIFMT_NB_NF:
  237. val = PDM_CKP_NORMAL;
  238. break;
  239. case SND_SOC_DAIFMT_IB_NF:
  240. val = PDM_CKP_INVERTED;
  241. break;
  242. default:
  243. return -EINVAL;
  244. }
  245. pm_runtime_get_sync(cpu_dai->dev);
  246. regmap_update_bits(pdm->regmap, PDM_CLK_CTRL, mask, val);
  247. pm_runtime_put(cpu_dai->dev);
  248. return 0;
  249. }
  250. static int rockchip_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
  251. struct snd_soc_dai *dai)
  252. {
  253. struct rk_pdm_dev *pdm = to_info(dai);
  254. int ret = 0;
  255. switch (cmd) {
  256. case SNDRV_PCM_TRIGGER_START:
  257. case SNDRV_PCM_TRIGGER_RESUME:
  258. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  259. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  260. rockchip_pdm_rxctrl(pdm, 1);
  261. break;
  262. case SNDRV_PCM_TRIGGER_SUSPEND:
  263. case SNDRV_PCM_TRIGGER_STOP:
  264. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  265. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  266. rockchip_pdm_rxctrl(pdm, 0);
  267. break;
  268. default:
  269. ret = -EINVAL;
  270. break;
  271. }
  272. return ret;
  273. }
  274. static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai)
  275. {
  276. struct rk_pdm_dev *pdm = to_info(dai);
  277. dai->capture_dma_data = &pdm->capture_dma_data;
  278. return 0;
  279. }
  280. static const struct snd_soc_dai_ops rockchip_pdm_dai_ops = {
  281. .set_fmt = rockchip_pdm_set_fmt,
  282. .trigger = rockchip_pdm_trigger,
  283. .hw_params = rockchip_pdm_hw_params,
  284. };
  285. #define ROCKCHIP_PDM_RATES SNDRV_PCM_RATE_8000_192000
  286. #define ROCKCHIP_PDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  287. SNDRV_PCM_FMTBIT_S20_3LE | \
  288. SNDRV_PCM_FMTBIT_S24_LE | \
  289. SNDRV_PCM_FMTBIT_S32_LE)
  290. static struct snd_soc_dai_driver rockchip_pdm_dai = {
  291. .probe = rockchip_pdm_dai_probe,
  292. .capture = {
  293. .stream_name = "Capture",
  294. .channels_min = 2,
  295. .channels_max = 8,
  296. .rates = ROCKCHIP_PDM_RATES,
  297. .formats = ROCKCHIP_PDM_FORMATS,
  298. },
  299. .ops = &rockchip_pdm_dai_ops,
  300. .symmetric_rates = 1,
  301. };
  302. static const struct snd_soc_component_driver rockchip_pdm_component = {
  303. .name = "rockchip-pdm",
  304. };
  305. static int rockchip_pdm_runtime_suspend(struct device *dev)
  306. {
  307. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  308. clk_disable_unprepare(pdm->clk);
  309. clk_disable_unprepare(pdm->hclk);
  310. return 0;
  311. }
  312. static int rockchip_pdm_runtime_resume(struct device *dev)
  313. {
  314. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  315. int ret;
  316. ret = clk_prepare_enable(pdm->clk);
  317. if (ret) {
  318. dev_err(pdm->dev, "clock enable failed %d\n", ret);
  319. return ret;
  320. }
  321. ret = clk_prepare_enable(pdm->hclk);
  322. if (ret) {
  323. dev_err(pdm->dev, "hclock enable failed %d\n", ret);
  324. return ret;
  325. }
  326. return 0;
  327. }
  328. static bool rockchip_pdm_wr_reg(struct device *dev, unsigned int reg)
  329. {
  330. switch (reg) {
  331. case PDM_SYSCONFIG:
  332. case PDM_CTRL0:
  333. case PDM_CTRL1:
  334. case PDM_CLK_CTRL:
  335. case PDM_HPF_CTRL:
  336. case PDM_FIFO_CTRL:
  337. case PDM_DMA_CTRL:
  338. case PDM_INT_EN:
  339. case PDM_INT_CLR:
  340. case PDM_DATA_VALID:
  341. return true;
  342. default:
  343. return false;
  344. }
  345. }
  346. static bool rockchip_pdm_rd_reg(struct device *dev, unsigned int reg)
  347. {
  348. switch (reg) {
  349. case PDM_SYSCONFIG:
  350. case PDM_CTRL0:
  351. case PDM_CTRL1:
  352. case PDM_CLK_CTRL:
  353. case PDM_HPF_CTRL:
  354. case PDM_FIFO_CTRL:
  355. case PDM_DMA_CTRL:
  356. case PDM_INT_EN:
  357. case PDM_INT_CLR:
  358. case PDM_INT_ST:
  359. case PDM_DATA_VALID:
  360. case PDM_RXFIFO_DATA:
  361. case PDM_VERSION:
  362. return true;
  363. default:
  364. return false;
  365. }
  366. }
  367. static bool rockchip_pdm_volatile_reg(struct device *dev, unsigned int reg)
  368. {
  369. switch (reg) {
  370. case PDM_SYSCONFIG:
  371. case PDM_FIFO_CTRL:
  372. case PDM_INT_CLR:
  373. case PDM_INT_ST:
  374. case PDM_RXFIFO_DATA:
  375. return true;
  376. default:
  377. return false;
  378. }
  379. }
  380. static bool rockchip_pdm_precious_reg(struct device *dev, unsigned int reg)
  381. {
  382. switch (reg) {
  383. case PDM_RXFIFO_DATA:
  384. return true;
  385. default:
  386. return false;
  387. }
  388. }
  389. static const struct reg_default rockchip_pdm_reg_defaults[] = {
  390. {0x04, 0x78000017},
  391. {0x08, 0x0bb8ea60},
  392. {0x18, 0x0000001f},
  393. };
  394. static const struct regmap_config rockchip_pdm_regmap_config = {
  395. .reg_bits = 32,
  396. .reg_stride = 4,
  397. .val_bits = 32,
  398. .max_register = PDM_VERSION,
  399. .reg_defaults = rockchip_pdm_reg_defaults,
  400. .num_reg_defaults = ARRAY_SIZE(rockchip_pdm_reg_defaults),
  401. .writeable_reg = rockchip_pdm_wr_reg,
  402. .readable_reg = rockchip_pdm_rd_reg,
  403. .volatile_reg = rockchip_pdm_volatile_reg,
  404. .precious_reg = rockchip_pdm_precious_reg,
  405. .cache_type = REGCACHE_FLAT,
  406. };
  407. static const struct of_device_id rockchip_pdm_match[] = {
  408. { .compatible = "rockchip,pdm",
  409. .data = (void *)RK_PDM_RK3229 },
  410. { .compatible = "rockchip,px30-pdm",
  411. .data = (void *)RK_PDM_RK3308 },
  412. { .compatible = "rockchip,rk1808-pdm",
  413. .data = (void *)RK_PDM_RK3308 },
  414. { .compatible = "rockchip,rk3308-pdm",
  415. .data = (void *)RK_PDM_RK3308 },
  416. {},
  417. };
  418. MODULE_DEVICE_TABLE(of, rockchip_pdm_match);
  419. static int rockchip_pdm_probe(struct platform_device *pdev)
  420. {
  421. const struct of_device_id *match;
  422. struct rk_pdm_dev *pdm;
  423. struct resource *res;
  424. void __iomem *regs;
  425. int ret;
  426. pdm = devm_kzalloc(&pdev->dev, sizeof(*pdm), GFP_KERNEL);
  427. if (!pdm)
  428. return -ENOMEM;
  429. match = of_match_device(rockchip_pdm_match, &pdev->dev);
  430. if (match)
  431. pdm->version = (enum rk_pdm_version)match->data;
  432. if (pdm->version == RK_PDM_RK3308) {
  433. pdm->reset = devm_reset_control_get(&pdev->dev, "pdm-m");
  434. if (IS_ERR(pdm->reset))
  435. return PTR_ERR(pdm->reset);
  436. }
  437. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  438. regs = devm_ioremap_resource(&pdev->dev, res);
  439. if (IS_ERR(regs))
  440. return PTR_ERR(regs);
  441. pdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
  442. &rockchip_pdm_regmap_config);
  443. if (IS_ERR(pdm->regmap))
  444. return PTR_ERR(pdm->regmap);
  445. pdm->capture_dma_data.addr = res->start + PDM_RXFIFO_DATA;
  446. pdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  447. pdm->capture_dma_data.maxburst = PDM_DMA_BURST_SIZE;
  448. pdm->dev = &pdev->dev;
  449. dev_set_drvdata(&pdev->dev, pdm);
  450. pdm->clk = devm_clk_get(&pdev->dev, "pdm_clk");
  451. if (IS_ERR(pdm->clk))
  452. return PTR_ERR(pdm->clk);
  453. pdm->hclk = devm_clk_get(&pdev->dev, "pdm_hclk");
  454. if (IS_ERR(pdm->hclk))
  455. return PTR_ERR(pdm->hclk);
  456. ret = clk_prepare_enable(pdm->hclk);
  457. if (ret)
  458. return ret;
  459. pm_runtime_enable(&pdev->dev);
  460. if (!pm_runtime_enabled(&pdev->dev)) {
  461. ret = rockchip_pdm_runtime_resume(&pdev->dev);
  462. if (ret)
  463. goto err_pm_disable;
  464. }
  465. ret = devm_snd_soc_register_component(&pdev->dev,
  466. &rockchip_pdm_component,
  467. &rockchip_pdm_dai, 1);
  468. if (ret) {
  469. dev_err(&pdev->dev, "could not register dai: %d\n", ret);
  470. goto err_suspend;
  471. }
  472. rockchip_pdm_rxctrl(pdm, 0);
  473. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  474. if (ret) {
  475. dev_err(&pdev->dev, "could not register pcm: %d\n", ret);
  476. goto err_suspend;
  477. }
  478. return 0;
  479. err_suspend:
  480. if (!pm_runtime_status_suspended(&pdev->dev))
  481. rockchip_pdm_runtime_suspend(&pdev->dev);
  482. err_pm_disable:
  483. pm_runtime_disable(&pdev->dev);
  484. clk_disable_unprepare(pdm->hclk);
  485. return ret;
  486. }
  487. static int rockchip_pdm_remove(struct platform_device *pdev)
  488. {
  489. struct rk_pdm_dev *pdm = dev_get_drvdata(&pdev->dev);
  490. pm_runtime_disable(&pdev->dev);
  491. if (!pm_runtime_status_suspended(&pdev->dev))
  492. rockchip_pdm_runtime_suspend(&pdev->dev);
  493. clk_disable_unprepare(pdm->clk);
  494. clk_disable_unprepare(pdm->hclk);
  495. return 0;
  496. }
  497. #ifdef CONFIG_PM_SLEEP
  498. static int rockchip_pdm_suspend(struct device *dev)
  499. {
  500. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  501. regcache_mark_dirty(pdm->regmap);
  502. return 0;
  503. }
  504. static int rockchip_pdm_resume(struct device *dev)
  505. {
  506. struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
  507. int ret;
  508. ret = pm_runtime_get_sync(dev);
  509. if (ret < 0) {
  510. pm_runtime_put(dev);
  511. return ret;
  512. }
  513. ret = regcache_sync(pdm->regmap);
  514. pm_runtime_put(dev);
  515. return ret;
  516. }
  517. #endif
  518. static const struct dev_pm_ops rockchip_pdm_pm_ops = {
  519. SET_RUNTIME_PM_OPS(rockchip_pdm_runtime_suspend,
  520. rockchip_pdm_runtime_resume, NULL)
  521. SET_SYSTEM_SLEEP_PM_OPS(rockchip_pdm_suspend, rockchip_pdm_resume)
  522. };
  523. static struct platform_driver rockchip_pdm_driver = {
  524. .probe = rockchip_pdm_probe,
  525. .remove = rockchip_pdm_remove,
  526. .driver = {
  527. .name = "rockchip-pdm",
  528. .of_match_table = of_match_ptr(rockchip_pdm_match),
  529. .pm = &rockchip_pdm_pm_ops,
  530. },
  531. };
  532. module_platform_driver(rockchip_pdm_driver);
  533. MODULE_AUTHOR("Sugar <sugar.zhang@rock-chips.com>");
  534. MODULE_DESCRIPTION("Rockchip PDM Controller Driver");
  535. MODULE_LICENSE("GPL v2");